Search results for "subthreshold"

Hits ?▲	Authors	Title	Venue	Year	Link
15	N. Lakhdar, Fayçal Djeffal	New optimized Dual-Material (DM) gate design to improve the submicron GaN-MESFETs reliability in subthreshold regime.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
15	S.-L. Siu, Wing-Shan Tam, Hei Wong, Chi-Wah Kok, K. Kakusima, Hiroshi Iwai	Influence of multi-finger layout on the subthreshold behavior of nanometer MOS transistors.	Microelectron. Reliab.	2012	DBLP DOI BibTeX RDF
15	Mukund Kalyanaraman, Michael Orshansky	Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation.	IACR Cryptol. ePrint Arch.	2012	DBLP BibTeX RDF
15	Benjamin Torben-Nielsen, Idan Segev, Yosef Yarom	The Generation of Phase Differences and Frequency Changes in a Network Model of Inferior Olive Subthreshold Oscillations.	PLoS Comput. Biol.	2012	DBLP DOI BibTeX RDF
15	Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang	A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Fabio Frustaci, Pasquale Corsonello, Stefania Perri	Analytical Delay Model Considering Variability Effects in Subthreshold Domain.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Woojin Rim, Woong Choi, Jongsun Park 0001	Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Ming-Hung Chang, Yi-Te Chiu, Wei Hwang	Design and Iso-Area Vmin Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Chenchang Zhan, Wing-Hung Ki	An Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator With Subthreshold Undershoot-Reduction for SoC.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
15	Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang	Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Peter Grossmann, Miriam Leeser, Marvin Onabajo	Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Yingchieh Ho, Chiachi Chang, Chauchin Su	Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL.	IEEE Trans. Circuits Syst. II Express Briefs	2012	DBLP DOI BibTeX RDF
15	Morteza Nabavi, Maitham Shams	A gate sizing and transistor fingering strategy for subthreshold CMOS circuits.	IEICE Electron. Express	2012	DBLP DOI BibTeX RDF
15	Michael J. Roy, Michelle E. Costanzo, Suzanne Leaman	Psychophysiologic Identification of Subthreshold PTSD in Combat Veterans.	Annual Review of Cybertherapy and Telemedicine	2012	DBLP DOI BibTeX RDF
15	Shilpa Pendyala, Srinivas Katkoori	Interval arithmetic based input vector control for RTL subthreshold leakage minimization.	VLSI-SoC	2012	DBLP DOI BibTeX RDF
15	Viviane S. Ghaderi, Shane M. Roach, Dong Song, Vasilis Z. Marmarelis, John Choma Jr., Theodore W. Berger	Analog low-power hardware implementation of a Laguerre-Volterra model of intracellular subthreshold neuronal activity.	EMBC	2012	DBLP DOI BibTeX RDF
15	Weiwei Shi 0001, Oliver Chiu-sing Choy	A process-compatible passive RFID tag's digital design for subthreshold operation.	ICECS	2012	DBLP DOI BibTeX RDF
15	Kiyohiko Sakakibara, Toshio Kumamoto, K. Arimoto	Impact of subthreshold hump on bulk-bias dependence of offset voltage variability in weak and moderate inversion regions.	CICC	2012	DBLP DOI BibTeX RDF
15	Sven Lütkemeier, Thorsten Jungeblut, Mario Porrmann, Ulrich Rückert 0001	A 200mV 32b subthreshold processor with adaptive supply voltage control.	ISSCC	2012	DBLP DOI BibTeX RDF
15	Kyle Craig, Yousef Shakhsheer, Benton H. Calhoun	Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation.	ISLPED	2012	DBLP DOI BibTeX RDF
15	A. R. Aravinth Kumar, Ashudeb Dutta, Shiv Govind Singh	A 1.5-7.5GHz low power low noise amplifier (LNA) design using subthreshold technique for Wireless Sensor Network (WSN) application.	ISCAS	2012	DBLP DOI BibTeX RDF
15	Shien-Chun Luo, Chi-Ray Huang, Lih-Yih Chiou	Minimum convertible voltage analysis for ratioless and robust subthreshold level conversion.	ISCAS	2012	DBLP DOI BibTeX RDF
15	Erkka Laulainen, Matthew J. Turnquist, Jani Mäkipää, Lauri Koskinen	Adaptive subthreshold timing-error detection 8 bit microcontroller in 65 nm CMOS.	ISCAS	2012	DBLP DOI BibTeX RDF
15	A. R. Aravinth Kumar, Ashudeb Dutta, Shiv Govind Singh	Noise-cancelled subthreshold UWB LNA for Wireless Sensor Network application.	ICUWB	2012	DBLP DOI BibTeX RDF
15	Ming Liu 0015, Xu Zhang 0010, Hong Chen 0002, Chun Zhang, Zhihua Wang 0001	A fast computable delay model for subthreshold circuit.	CCECE	2012	DBLP DOI BibTeX RDF
15	Wei-Bin Yang, Chi-Hsiung Wang, I-Ting Chuo, Huang-Hsuan Hsu	A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application.	ISPACS	2012	DBLP DOI BibTeX RDF
15	Yasuhiro Takahashi, Toshikazu Sekine, Nazrul Anuar Nayan, Michio Yokoyama	Power-saving analysis of adiabatic logic in subthreshold region.	ISPACS	2012	DBLP DOI BibTeX RDF
15	Jun Zhang, Yunling Luo, Qiaobo Wang, Jingjing Li, Zhuqian Gong, Hong-Zhou Tan, Yunliang Long	A low-voltage, low-power subthreshold CMOS voltage reference without resistors and high threshold voltage devices.	APCCAS	2012	DBLP DOI BibTeX RDF
15	Tsung-Sum Lee, Wen-Zhe Lu, Yi-Cheng Huang	A 0.6-V subthreshold-leakage supressed CMOS fully differential switched-capacitor amplifier.	APCCAS	2012	DBLP DOI BibTeX RDF
15	Bo Liu, Maryam Ashouei, Jos Huisken, José Pineda de Gyvez	Standard cell sizing for subthreshold operation.	DAC	2012	DBLP DOI BibTeX RDF
15	Luca Magnelli	Subthreshold design of ultra low-power analog modules.		2012	RDF
15	Meng-Fan Chang, Shi-Wei Chang, Po-Wei Chou, Wei-Cheng Wu	A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
15	Cheng-Hung Lo, Shi-Yu Huang	P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
15	Luca Magnelli, Felice Crupi, Pasquale Corsonello, Calogero Pace, Giuseppe Iannaccone	A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference.	IEEE J. Solid State Circuits	2011	DBLP DOI BibTeX RDF
15	Michael B. Henry, Leyla Nazhandali	Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture.	Trans. High Perform. Embed. Archit. Compil.	2011	DBLP DOI BibTeX RDF
15	Michiel W. H. Remme, John Rinzel	Role of active dendritic conductances in subthreshold input integration.	J. Comput. Neurosci.	2011	DBLP DOI BibTeX RDF
15	Woochang Lim, Sang-Yoon Kim	Statistical-mechanical measure of stochastic spiking coherence in a population of inhibitory subthreshold neurons.	J. Comput. Neurosci.	2011	DBLP DOI BibTeX RDF
15	Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa	Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
15	Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa	Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit.	IEICE Trans. Electron.	2011	DBLP DOI BibTeX RDF
15	Saurav Chakraborty, Abhijit Mallik, Chandan Kumar Sarkar	Subthreshold performance of pocket-implanted silicon-on-insulator CMOS devices and circuits for ultra-low-power analogue/mixed-signal applications.	IET Circuits Devices Syst.	2011	DBLP DOI BibTeX RDF
15	Amir Hasanbegovic, Snorre Aunet	Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process.	Microprocess. Microsystems	2011	DBLP DOI BibTeX RDF
15	Osamu Hoshino	Neuronal Responses Below Firing Threshold for Subthreshold Cross-Modal Enhancement.	Neural Comput.	2011	DBLP DOI BibTeX RDF
15	Osamu Hoshino	Subthreshold Membrane Depolarization as Memory Trace for Perceptual Learning.	Neural Comput.	2011	DBLP DOI BibTeX RDF
15	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2011	DBLP DOI BibTeX RDF
15	Zhihao Ding, Guangxi Hu, Jinglun Gu, Ran Liu 0001, Lingli Wang, Tingao Tang	An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
15	S. D. Pable, Mohd. Hasan	High speed interconnect through device optimization for subthreshold FPGA.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
15	Fayçal Djeffal, Toufik Bendib, Mohamed Amir Abdi	A two-dimensional semi-analytical analysis of the subthreshold-swing behavior including free carriers and interfacial traps effects for nanoscale double-gate MOSFETs.	Microelectron. J.	2011	DBLP DOI BibTeX RDF
15	J. Kevin Hicks, Dhireesha Kudithipudi	Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
15	Abhijit Sil, Magdy A. Bayoumi	A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm.	J. Low Power Electron.	2011	DBLP DOI BibTeX RDF
15	Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2011	DBLP DOI BibTeX RDF
15	Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, Jiun-In Guo	Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2011	DBLP DOI BibTeX RDF
15	Hak-Kee Jung	Analysis of Subthreshold Characteristics for Device Parameter of DGMOSFET Using Gaussian Function.	J. Inform. and Commun. Convergence Engineering	2011	DBLP DOI BibTeX RDF
15	Ji-Hyeong Han, Hak-Kee Jung, Choon-Shik Park	Structure-Dependent Subthreshold Swings for Double-gate MOSFETs.	J. Inform. and Commun. Convergence Engineering	2011	DBLP DOI BibTeX RDF
15	Hiroshi Fuketa, Dan Kuroda, Masanori Hashimoto, Takao Onoye	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion.	IEEE Trans. Circuits Syst. II Express Briefs	2011	DBLP DOI BibTeX RDF
15	Chutham Sawigun, Wouter A. Serdijn	Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
15	Manmit Muker, Maitham Shams	Preference of designing CMOS subthreshold logic circuits using uniform-size transistors.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
15	Indika U. K. Bogoda Appuhamylage, Daisuke Kanemoto, Kenji Taniguchi 0001	A Novel 100ppm/°C current reference for ultra-low-power subthreshold applications.	IEICE Electron. Express	2011	DBLP DOI BibTeX RDF
15	Bipul C. Paul, Arijit Raychowdhury	Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges.	Low-Power Variation-Tolerant Design in Nanometer Silicon	2011	DBLP DOI BibTeX RDF
15	Antonio Cerdeira, Magali Estrada, Benjamín Iñíguez, S. Soto	Modeling the subthreshold region of OTFTs.	CCE	2011	DBLP DOI BibTeX RDF
15	Joseph Sankman, Dongsheng Ma 0001	A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
15	Peter Grossmann, Miriam Leeser	A prototype FPGA for subthreshold-optimized CMOS (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
15	Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa	A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.	ASP-DAC	2011	DBLP DOI BibTeX RDF
15	Matthew J. Turnquist, Erkka Laulainen, Jani Mäkipää, Lauri Koskinen	Measurement of a system-adaptive error-detection sequential circuit with subthreshold SCL.	NORCHIP	2011	DBLP DOI BibTeX RDF
15	Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang	A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS.	ISLPED	2011	DBLP BibTeX RDF
15	Roghayeh Saeidi, Mohammad Sharifkhani, Khosrow Hajsadeghi	A subthreshold dynamic read SRAM (DRSRAM) based on dynamic stability criteria.	ISCAS	2011	DBLP DOI BibTeX RDF
15	Hao Zhang 0087, Yimeng Zhang, Mengshu Huang, Tsutomu Yoshihara	CMOS low-power subthreshold reference voltage utilizing self-biased body effect.	ASICON	2011	DBLP DOI BibTeX RDF
15	Yilei Li, Yu Wang 0046, Na Yan, Xi Tan, Hao Min	A subthreshold MOSFET bandgap reference with ultra-low power supply voltage.	ASICON	2011	DBLP DOI BibTeX RDF
15	Kyungseok Kim, Vishwani D. Agrawal	Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates.	ISQED	2011	DBLP DOI BibTeX RDF
15	Adnan Abdul-Aziz Gutub	Subthreshold SRAM Designs for Cryptography Security Computations.	ICSECS (1)	2011	DBLP DOI BibTeX RDF
15	Chen Hu, Jun Yang, Meng Zhang, Xiulong Wu	A 12T Subthreshold SRAM Bit-Cell for Medical Device Application.	CyberC	2011	DBLP DOI BibTeX RDF
15	Ik Joon Chang, Sang Phill Park, Kaushik Roy 0001	Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
15	Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe 0001, Marios C. Papaefthymiou	187 MHz Subthreshold-Supply Charge-Recovery FIR.	IEEE J. Solid State Circuits	2010	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, David M. Brooks	Can Subthreshold and Near-Threshold Circuits Go Mainstream?	IEEE Micro	2010	DBLP DOI BibTeX RDF
15	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
15	Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
15	Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya	High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
15	Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal	Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic.	IET Circuits Devices Syst.	2010	DBLP DOI BibTeX RDF
15	Pramod Kumar Tiwari, Chinmay R. Panda, Anupam Agarwal, Pratik Sharma, Satyabrata Jit	Modelling of doping-dependent subthreshold swing of symmetric double-gate MOSFETs.	IET Circuits Devices Syst.	2010	DBLP DOI BibTeX RDF
15	Lars Wolff, Benjamin Lindner	Mean, Variance, and Autocorrelation of Subthreshold Potential Fluctuations Driven by Filtered Conductance Shot Noise.	Neural Comput.	2010	DBLP DOI BibTeX RDF
15	Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal	Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.	Microelectron. J.	2010	DBLP DOI BibTeX RDF
15	David Bol, Denis Flandre, Jean-Didier Legat	Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
15	David Coleman, Jia Di	Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
15	Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal	Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits.	J. Low Power Electron.	2010	DBLP DOI BibTeX RDF
15	Hak-Kee Jung, Ji-Hyeong Han	Design of DGMOSFET for Optimum Subthreshold Characteristics using MicroTec.	J. Inform. and Commun. Convergence Engineering	2010	DBLP DOI BibTeX RDF
15	Udit Monga, H. Børli, Tor A. Fjeldly	Compact subthreshold current and capacitance modeling of short-channel double-gate MOSFETs.	Math. Comput. Model.	2010	DBLP DOI BibTeX RDF
15	Steven A. Vitale, Peter W. Wyatt, Nisha Checka, Jakub Kedzierski, Craig L. Keast	FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics.	Proc. IEEE	2010	DBLP DOI BibTeX RDF
15	Sumeet Kumar Gupta, Arijit Raychowdhury, Kaushik Roy 0001	Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective.	Proc. IEEE	2010	DBLP DOI BibTeX RDF
15	Ryan D. Jorgenson, Lief Sorensen, Dan Leet, Michael S. Hagedorn, David R. Lamb, Thomas Hal Friddell, Warren P. Snapp	Ultralow-Power Operation in Subthreshold Regimes Applying Clockless Logic.	Proc. IEEE	2010	DBLP DOI BibTeX RDF
15	Stuart N. Wooters, Benton H. Calhoun, Travis N. Blalock	An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
15	Massimo Alioto	Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
15	Ling Su, Dongsheng Ma 0001, A. Paul Brokaw	Design and Analysis of Monolithic Step-Down SC Power Converter With Subthreshold DPWM Control for Self-Powered Wireless Sensors.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
15	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
15	Sven Lütkemeier, Ulrich Rückert 0001	A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror.	IEEE Trans. Circuits Syst. II Express Briefs	2010	DBLP DOI BibTeX RDF
15	Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang	Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
15	Kapil K. Rajput, Anil K. Saini, Subash Chandra Bose	DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation.	ISVLSI	2010	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits.	DATE	2010	DBLP DOI BibTeX RDF
15	Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye	Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.	ASP-DAC	2010	DBLP DOI BibTeX RDF
15	Armin Tajalli, Yusuf Leblebici	Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution.	ESSCIRC	2010	DBLP DOI BibTeX RDF