Search results for "D-latch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	M. J. Foster	Avoiding Latch Formation in Regular Expression Recognizers.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF
16	Anthony Correale	Design Considerations of a Static LSSD Polarity Hold Latch Pair.	IBM J. Res. Dev.	1984	DBLP DOI BibTeX RDF
16	José C. Barros, Brian W. Johnson	Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF
16	Donald B. Estreich, Robert W. Dutton	Modeling Latch-Up in CMOS Integrated Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1982	DBLP DOI BibTeX RDF
16	Paul M. Almy, Jose L. Rivero	Using error latch trace to obtain diagnostic information.	DAC	1981	DBLP BibTeX RDF
16	Kenneth S. Gray	Cross-Coupled Charge-Transfer Sense Amplifier and Latch Sense Scheme for High-Density FET Memories.	IBM J. Res. Dev.	1980	DBLP DOI BibTeX RDF
11	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
11	Jiaoyan Chen, Dilip P. Vasudevan, Emanuel M. Popovici, Michel P. Schellekens	Reversible online BIST using bidirectional BILBO.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	bilbo, bist, testing, reversible logic
11	Ying-Chieh Liu 0001, Su-Ju Lu	An Investigation of Function Based Design Considering Affordances in Conceptual Design of Mechanical Movement.	HCI (17)	2009	DBLP DOI BibTeX RDF	function based design, mechanical movement, engineering design process, affordances, conceptual design
11	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
11	Samed Maltabas, Martin Margala, Ugur Çilingiroglu	Varicap threshold logic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	minnick tl network, variable capacitance, threshold logic, parallel counter
11	Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal	Characterization of sequential cells for constraint sensitivities.	ISQED	2009	DBLP DOI BibTeX RDF
11	Hai Yu, Michael Nicolaidis, Lorena Anghel	An effective approach to detect logic soft errors in digital circuits based on GRAAL.	ISQED	2009	DBLP DOI BibTeX RDF
11	V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani	Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004	Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit
11	Charu Nagpal, Rajesh Garg, Sunil P. Khatri	A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.	DATE	2008	DBLP DOI BibTeX RDF
11	Hamed Abrishami, Safar Hatami, Massoud Pedram	Characterization and design of sequential circuit elements to combat soft error.	ICCD	2008	DBLP DOI BibTeX RDF
11	Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki	Safe clocking register assignment in datapath synthesis.	ICCD	2008	DBLP DOI BibTeX RDF
11	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
11	Vikas Chandra, Robert C. Aitken	Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS.	DFT	2008	DBLP DOI BibTeX RDF
11	Joseph F. Ryan 0002, Benton H. Calhoun	Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation.	ISQED	2008	DBLP DOI BibTeX RDF	Sub-threshold Circuits, Sub-Vt, Sense-Amplifiers, Variation, Offset
11	Charbel J. Akl, Magdy A. Bayoumi	Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.	VLSI Design	2008	DBLP DOI BibTeX RDF
11	Montek Singh, Steven M. Nowick	MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Love Kothari, Nicholas P. Carter	Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	memory technologies, low-power design, Emerging technologies
11	Julien Lamoureux, Steven J. E. Wilton	Clock-Aware Placement for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
11	Jeni McIntosh-Elkins, Karen McRitchie, Maureen Scoones	From the silent generation to generation x, y and z: strategies for managing the generation mix.	SIGUCCS	2007	DBLP DOI BibTeX RDF	baby boomers, generation mix, generation x, generation y, staff management, student management
11	Yan Lin 0001, Lei He 0001	Device and architecture concurrent optimization for FPGA transient soft error rate.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Álvaro Vázquez, Elisardo Antelo, Paolo Montuschi	A radix-10 SRT divider based on alternative BCD codings.	ICCD	2007	DBLP DOI BibTeX RDF
11	Man Kay Law, Amine Bermak	A CMOS Image Sensor using Variable Reference Time Domain Encoding.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Sandeep Patil, Michael Wieckowski, Martin Margala	A Self-Biased Charge-Transfer Sense Amplifier.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Soon-Ik Cho, Suki Kim, Shin-Il Lim, Kwang-Hyun Baek	A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Jere A. M. Järvinen, Mikko Saukoski, Kari Halonen	A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Liang Wang 0024, Suge Yue, Yuanfu Zhao, Long Fan	An SEU-Tolerant Programmable Frequency Divider.	ISQED	2007	DBLP DOI BibTeX RDF
11	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
11	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Chen Kong Teh, Mototsugu Hamada, Tetsuya Fujita, Hiroyuki Hara, N. Ikumi, Yukihito Oowaki	Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Christos P. Sotiriou	Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Chuan-Yu Cho, Sheng-Kai Chang, Jia-Shung Wang	A Multiframe Motion Estimation Architecture for H.264/AVC.	ICIP	2006	DBLP DOI BibTeX RDF
11	Eslam Yahya, Marc Renaudin	QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
11	Tomohiro Yoshihara, Dai Kobayashi, Ryo Taguchi, Haruo Yokota	A Concurrency Control Method for Parallel Btree Structures.	ICDE Workshops	2006	DBLP DOI BibTeX RDF
11	Dmitri B. Strukov, Konstantin K. Likharev	A reconfigurable architecture for hybrid CMOS/Nanodevice circuits.	FPGA	2006	DBLP DOI BibTeX RDF	integrated hybrid circuits, architecture, programmable logic, nanoelectronics, programmable interconnect
11	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
11	Mark R. Greenstreet, Jihong Ren	Surfing Interconnect.	ASYNC	2006	DBLP DOI BibTeX RDF
11	Julien Lamoureux, Steven J. E. Wilton	Architecture and CAD for FPGA Clock Networks.	FPL	2006	DBLP DOI BibTeX RDF
11	Todd M. Austin	Razor: a low-power pipeline based on circuit-level timing speculation.	SBCCI	2006	DBLP DOI BibTeX RDF
11	Haque Mohammad Munirul, Michitaka Kameyama	Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.	ISMVL	2006	DBLP DOI BibTeX RDF
11	Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu	Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.	ISMVL	2006	DBLP DOI BibTeX RDF
11	Reza Molavi, Shahriar Mirabbasi, Resve A. Saleh	A high-speed low-energy dynamic PLA using an input-isolation scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Dongsheng Ma	Automatic substrate switching circuit for on-chip adaptive power supply system.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Yasutaka Haga, Richard C. S. Morling, Izzet Kale	A new bulk-driven input stage design for sub 1-volt CMOS op-amps.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique.	DFT	2006	DBLP DOI BibTeX RDF
11	S. M. Rezaul Hasan	A Novel 16-bit CMOS Digitally Controlled Oscillator.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Fatemeh Aezinia, Ali Afzali-Kusha, Caro Lucas	Optimizing High Speed Flip-Flop Using Genetic Algorithm.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A micropower low-voltage multiplier with reduced spurious switching.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Robert B. Reese, Mitchell A. Thornton, Cherrice Traver	A Coarse-Grain Phased Logic CPU.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	asynchronous, pipelined processor, Automatic synthesis, self-timed, micropipelines
11	Gang Luo 0001, Jeffrey F. Naughton, Curt J. Ellmann, Michael Watzke	Locking Protocols for Materialized Aggregate Join Views.	IEEE Trans. Knowl. Data Eng.	2005	DBLP DOI BibTeX RDF
11	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy 0001	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
11	Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin	DVS for On-Chip Bus Designs Based on Timing Error Correction.	DATE	2005	DBLP DOI BibTeX RDF
11	Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang	Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers.	SBCCI	2005	DBLP DOI BibTeX RDF	burst-mode, automatic synthesis, hazard, asynchronous logic, speed-independent
11	Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang	A 12.5 Gbps CMOS input sampler for serial link receiver front end.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
11	Dinh Hung Dang, Yvon Savaria, Mohamad Sawan	A novel approach for implementing ultra-high speed flash ADC using MCML circuits.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	David Levacq, Vincent Dessard, Denis Flandre	Ultra-low power flip-flops for MTCMOS circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
11	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	Low-voltage micropower multipliers with reduced spurious switching.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
11	Javier A. Salcedo, Juin J. Liou, Muhammad Yaqub Afridi, Allen R. Hefner	Novel electrostatic discharge protection structure for a monolithic gas sensor systems-on-a-chip.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
11	Trent McConaghy, Georges G. E. Gielen	IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
11	Harmander Deogun, Dennis Sylvester, David T. Blaauw	Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate.	ISQED	2005	DBLP DOI BibTeX RDF
11	Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee	Transition Tests for High Performance Microprocessors.	VTS	2005	DBLP DOI BibTeX RDF
11	Lukás Sekanina, Ricardo Salem Zebulum	Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
11	Aliakbar Ghadiri, Hamid Mahmoodi-Meimand	Dual-Edge Triggered Static Pulsed Flip-Flops.	VLSI Design	2005	DBLP DOI BibTeX RDF
11	Chua-Chin Wang, Yih-Long Tseng, Hon-Yuan Leo, Ron Hu	A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
11	Jing-Ling Yang, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	A high-efficiency strongly self-checking asynchronous datapath.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
11	Allan Hartstein, Thomas R. Puzak	The optimum pipeline depth considering both power and performance.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	Pipeline Depth, Power and Performance, Workload Specificity, Simulation
11	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	Pipelines in Dynamic Dual-Rail Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
11	Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev	A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
11	Abdel Ejnioui, Abdelhalim Alsharqawi	Pipeline-Level Control of Self-Resetting Pipelines.	DSD	2004	DBLP DOI BibTeX RDF
11	Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou	Handshake Protocols for De-Synchronization.	ASYNC	2004	DBLP DOI BibTeX RDF
11	Chirayu S. Amin, Florentin Dartu, Yehea I. Ismail	Modeling unbuffered latches for timing analysis.	ICCAD	2004	DBLP DOI BibTeX RDF
11	Omid Mirmotahari, Yngvar Berg	A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC.	ISMVL	2004	DBLP DOI BibTeX RDF
11	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy 0001	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
11	Madhur Khandelwal, Andruid Kerne, J. Michael Mistrot	Manipulating history in generative hypermedia.	Hypertext	2004	DBLP DOI BibTeX RDF	generative, history, non-linear, time travel
11	Todd M. Austin	Designing robust microarchitectures.	DAC	2004	DBLP DOI BibTeX RDF	computer system design, reliable microarchitecture design, low-power, microarchitecture, system-on-a-chip
11	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, statistical timing analysis
11	Hai Zhou 0001	Timing Verification with Crosstalk for Transparently Latched Circuits.	DATE	2003	DBLP DOI BibTeX RDF
11	Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge	Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.	MICRO	2003	DBLP DOI BibTeX RDF
11	Allan Hartstein, Thomas R. Puzak	Optimum Power/Performance Pipeline Depth.	MICRO	2003	DBLP DOI BibTeX RDF
11	Aristides Efthymiou, Jim D. Garside	Adaptive Pipeline Structures fo Speculation Control.	ASYNC	2003	DBLP DOI BibTeX RDF
11	Kenneth S. Stevens	Energy and Performance Models for Clocked and Asynchronous Communication.	ASYNC	2003	DBLP DOI BibTeX RDF
11	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi	Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology.	SBCCI	2003	DBLP DOI BibTeX RDF
11	Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic	Level conversion for dual-supply systems.	ISLPED	2003	DBLP DOI BibTeX RDF	level conversion, flip-flop, dual-supply voltage
11	Hing-mo Lam, Chi-Ying Tsui	High performance and low power completion detection circuit.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang	A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang	A new robust handshake for asymmetric asynchronous micro-pipelines.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Kuo-Hsing Cheng, Yung-Hsiang Lin	A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
11	Frank Grassert, Dirk Timmermann	Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	redundant numbers, self-timed logic, single-rail logic, low power, dynamic logic
11	Ching-Hwa Cheng	Design Scan Test Strategy for Single Phase Dynamic Circuits.	DFT	2003	DBLP DOI BibTeX RDF
11	Jing-Ling Yang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun	Design for Self-Checking and Self-Timed Datapath.	VTS	2003	DBLP DOI BibTeX RDF	asynchronous datapath, differential cascode voltage switch logic, Self-checking, dynamic circuits
11	Miguel Garvie, Adrian Thompson	Evolution of Combinatonial and Sequential On-Line Self-Diagnosing Hardware.	Evolvable Hardware	2003	DBLP DOI BibTeX RDF
11	Sangyong Hwang, Keunjoo Kwon, Sang Kyun Cha, Byung Suk Lee 0001	Performance Evaluation of Main-Memory R-tree Variants.	SSTD	2003	DBLP DOI BibTeX RDF
11	Kuo-Hsing Cheng, Wei-Chun Chang, Chia Ming Tu	A Robust Handshake for Asynchronous System.	IWSOC	2003	DBLP DOI BibTeX RDF
11	Wei-Yu Chen, Sandeep K. Gupta 0001, Melvin A. Breuer	Test Generation for Crosstalk-Induced Faults: Framework and Computational Results.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	time-based test generation, fault modeling, crosstalk, mixed-signal test