Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Qingshan Tang, Matthieu Tuna, Habib Mehrez	Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Karim M. Abdellatif, Roselyne Chotin-Avot, Zied Marrakchi, Habib Mehrez, Qingshan Tang	Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Viktor Pus, Pavel Benácek	Application specific processor with high level synthesized instructions (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Yosi Ben-Asher, Jacob Gendel, Gadi Haber, Oren Segal, Yousef Shajrawi	1K manycore FPGA shared memory architecture for SOC (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Ahmad Alzahrani 0001, Ronald F. DeMara	Non-adaptive sparse recovery and fault evasion using disjunct design configurations (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Mohammed Alawad, Yu Bai 0004, Ronald F. DeMara, Mingjie Lin	Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation.	FPGA	2014	DBLP DOI BibTeX RDF
1	Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner, Arun Kundu	Rent's rule based FPGA packing for routability optimization.	FPGA	2014	DBLP DOI BibTeX RDF
1	Santhosh Kumar Rethinagiri, Oscar Palomar, Adrián Cristal, Osman S. Unsal	Power estimation tool for system on programmable chip based platforms (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Ameer Abdelhadi, Guy G. F. Lemieux	Modular multi-ported SRAM-based memories.	FPGA	2014	DBLP DOI BibTeX RDF
1	Roshan Silwal, Mohammed Y. Niamat	Asynchronous physical unclonable function using FPGA-based self-timed ring oscillator (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Brad L. Hutchings, Joshua S. Monson, Danny Savory, Jared Keeley	A power side-channel-based digital to analog converterfor Xilinx FPGAs.	FPGA	2014	DBLP DOI BibTeX RDF
1	Peng Li 0031, Louis-Noël Pouchet, Deming Chen, Jason Cong	Transformations for throughput optimization in high-level synthesis (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
1	Jason Cong, Bingjun Xiao	Defect recovery in nanodevice-based programmable interconnects (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Jungwook Choi, Rob A. Rutenbar	Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform.	FPGA	2013	DBLP DOI BibTeX RDF
1	Masakazu Hioki, Toshihiro Sekigawa, Tadashi Nakagawa, Hanpei Koike, Yohei Matsumoto, Takashi Kawanami, Toshiyuki Tsutsumi	Fully-functional FPGA prototype with fine-grain programmable body biasing.	FPGA	2013	DBLP DOI BibTeX RDF
1	Peng Chen 0004, Chao Wang 0003, Xi Li 0003, Xuehai Zhou	Acceleration of the long read mapping on a PC-FPGA architecture (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Bruno da Silva 0001, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire	Performance and toolchain of a combined GPU/FPGA desktop (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Jinsong Mao, Hao Zhou, Haijiang Ye, Jinmei Lai	FPGA bitstream compression and decompression using LZ and golomb coding (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Soon Ee Ong, Siaw Chen Lee, Noohul Basheer Zain Ali	Hardware implemented real-time operating system (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Hasan Baig, Jeong-A Lee	A novel run-time auto-reconfigurable FPGA architecture for fast fault recovery with backward compatibility (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Pavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis	High performance architecture for object detection in streamed video (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe	Cross-platform FPGA accelerator development using CoRAM and CONNECT.	FPGA	2013	DBLP DOI BibTeX RDF
1	Meng Yang 0013, Jiarong Tong, A. E. A. Almaini	Indirect connection aware attraction for FPGA clustering (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi	High-level synthesis with LegUp: a crash course for users and researchers.	FPGA	2013	DBLP DOI BibTeX RDF
1	Martin Langhammer, Bogdan Pasca 0001	Faithful single-precision floating-point tangent for FPGAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Marc-André Daigneault, Jean-Pierre David	Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Udit Dhawan, André DeHon	Area-efficient near-associative memories on FPGAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Nick Ni, Yi Peng	Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Gabriel Weisz, James C. Hoe	C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction.	FPGA	2013	DBLP DOI BibTeX RDF
1	David Boland, George A. Constantinides	Word-length optimization beyond straight line code.	FPGA	2013	DBLP DOI BibTeX RDF
1	Chia-Hsiang Chen, Shiming Song, Zhengya Zhang	An FPGA-based transient error simulator for evaluating resilient system designs (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Jing Zhou, Lei Chen 0010, Shuo Wang	Precision fault injection method based on correspondence between configuration bitstream and architecture (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Yun Qu, Viktor K. Prasanna	Scalable high-throughput architecture for large balanced tree structures on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Chao Wang 0003, Xi Li 0003, Xuehai Zhou, Jim Martin 0001, Ray C. C. Cheung	Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Qian Zhao 0001, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi	A novel FPGA design framework with VLSI post-routing performance analysis (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Yu Bai 0004, Abigail Fuentes-Rivera, Mingjie Lin, Mike Riera	Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	David Uliana, Krzysztof Kepa, Peter Athanas	FPGA-based HPC application design for non-experts (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Seyyed Ahmad Razavi, Morteza Saheb Zamani	Improving bitstream compression by modifying FPGA architecture.	FPGA	2013	DBLP DOI BibTeX RDF
1	Andrew Love, Peter Athanas	FPGA meta-data management system for accelerating implementation time with incremental compilation (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Yuxin Wang, Peng Li 0031, Peng Zhang 0007, Chen Zhang 0001, Jason Cong	Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Michel A. Kinsy, Michael Pellauer, Srinivas Devadas	Heracles: a tool for fast RTL-based design space exploration of multicore processors.	FPGA	2013	DBLP DOI BibTeX RDF
1	Sheng Wei 0001, Jason Xin Zheng, Miodrag Potkonjak	Low power FPGA design using post-silicon device aging (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Eric S. Chung, Michael Papamichael	Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto, Masahiro Fujita	Rectification of advanced microprocessors without changing routing on FPGAs (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Bailey Miller, Frank Vahid, Tony Givargis	Embedding-based placement of processing element networks on FPGAs for physical model simulation.	FPGA	2013	DBLP DOI BibTeX RDF
1	Kenneth M. Zick, Meeta Srivastav, Wei Zhang 0044, Matthew French	Sensing nanosecond-scale voltage attacks and natural transients in FPGAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Sezer Gören 0001, Yusuf Turk, Ozgur Ozkurt, Abdullah Yildiz, H. Fatih Ugurdag	Achieving modular dynamic partial reconfiguration with a difference-based flow (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Nathaniel McVicar, Walter L. Ruzzo, Scott Hauck	Accelerating ncRNA homology search with FPGAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Wei Zuo, Yun Liang 0001, Peng Li 0031, Kyle Rupnow, Deming Chen, Jason Cong	Improving high level synthesis optimization opportunity through polyhedral transformations.	FPGA	2013	DBLP DOI BibTeX RDF
1	Chun Zhu, Qiuli Li, Jian Wang 0036, Jinmei Lai	A novel multithread routing method for FPGAs (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Christos Kyrkou, Christos-Savvas Bouganis, Theocharis Theocharides	FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Michael J. Wirthlin, Joshua E. Jensen, Alex Wilson, William Howes, Shi-Jie Wen, Rick Wong	Placement of repair circuits for in-field FPGA repair.	FPGA	2013	DBLP DOI BibTeX RDF
1	Deshanand P. Singh, Tomasz S. Czajkowski, Andrew C. Ling	Harnessing the power of FPGAs using altera's OpenCL compiler.	FPGA	2013	DBLP DOI BibTeX RDF
1	Vivek Venugopal, Devu Manikantan Shila	Hardware acceleration of TEA and XTEA algorithms on FPGA, GPU and multi-core processors (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	André DeHon	Location, location, location: the role of spatial locality in asymptotic energy minimization.	FPGA	2013	DBLP DOI BibTeX RDF
1	Stephen Neuendorffer, Fernando Martinez-Vallina	Building zynq® accelerators with Vivado® high level synthesis.	FPGA	2013	DBLP DOI BibTeX RDF
1	Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu 0011	Automating resource optimisation in reconfigurable design (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Swapnil Haria, Viktor K. Prasanna	AutoMapper: an automated tool for optimal hardware resource allocation for networking applications on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Brad L. Hutchings, Vaughn Betz (eds.)	The 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA '13, Monterey, CA, USA, February 11-13, 2013	FPGA	2013	DBLP DOI BibTeX RDF
1	Ruediger Willenberg, Paul Chow	A remote memory access infrastructure for global address space programming models in FPGAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Wenjuan Deng, Yiqun Zhu	A memory-efficient hardware architecture for real-time feature detection of the SIFT algorithm (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Jason Cong, Karthik Gururaj	Architecture support for custom instructions with memory operations.	FPGA	2013	DBLP DOI BibTeX RDF
1	Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne	Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Amir Moradi 0001, David F. Oswald, Christof Paar, Pawel Swierczynski	Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering.	FPGA	2013	DBLP DOI BibTeX RDF
1	Hao Wang, Jyh-Charn Liu	An FPGA based parallel architecture for music melody matching.	FPGA	2013	DBLP DOI BibTeX RDF
1	Jeremy Fowers, Greg Stitt	Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations.	FPGA	2013	DBLP DOI BibTeX RDF
1	Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, André DeHon	GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction.	FPGA	2013	DBLP DOI BibTeX RDF
1	Zilong Wang, Sitao Huang, Lanjun Wang, Hao Li, Yu Wang 0002, Huazhong Yang	Accelerating subsequence similarity search based on dynamic time warping distance with FPGA.	FPGA	2013	DBLP DOI BibTeX RDF
1	Peter Grossmann, Miriam Leeser, Marvin Onabajo	Minimum energy operation for clustered island-style FPGAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu	Elastic CGRAs.	FPGA	2013	DBLP DOI BibTeX RDF
1	Oluseyi A. Ayorinde, Benton H. Calhoun	Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Jingfei Jiang, Rongdong Hu, Mikel Luján	Effect of fixed-point arithmetic on deep belief networks (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Louis-Noël Pouchet, Peng Zhang 0007, P. Sadayappan, Jason Cong	Polyhedral-based data reuse optimization for configurable computing.	FPGA	2013	DBLP DOI BibTeX RDF
1	Da Tong, Lu Sun, Kiran Kumar Matam, Viktor K. Prasanna	High throughput and programmable online trafficclassifier on FPGA.	FPGA	2013	DBLP DOI BibTeX RDF
1	David M. Lewis, David Cashman, Mark Chan, Jeffrey Chromczak, Gary Lai, Andy Lee, Tim Vanderhoek, Haiming Yu	Architectural enhancements in Stratix V™.	FPGA	2013	DBLP DOI BibTeX RDF
1	Anh-Tuan Hoang, Takeshi Fujino	Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt	A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Vaughn Betz, Jason Cong	Are FPGAs suffering from the innovator's dilemna?	FPGA	2013	DBLP DOI BibTeX RDF
1	Eddie Hung, Steven J. E. Wilton	Towards simulator-like observability for FPGAs: a virtual overlay network for trace-buffers.	FPGA	2013	DBLP DOI BibTeX RDF
1	Trevor Bunker, Steven Swanson	A latency-optimized hybrid network for clustering FPGAs (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Chao Wang 0003, Xi Li 0003, Huizhen Zhang, Jinsong Ji, Xuehai Zhou	Custom instruction generation and mapping for reconfigurable instruction set processors (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Sai Rahul Chalamalasetti, Kevin T. Lim, Mitch Wright, Alvin AuYoung, Parthasarathy Ranganathan, Martin Margala	An FPGA memcached appliance.	FPGA	2013	DBLP DOI BibTeX RDF
1	Jason Cong, Muhuan Huang, Peng Zhang 0007	Efficient system-level mapping from streaming applications to FPGAs (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
1	Hui Yan Cheah, Suhaib A. Fahmy, Douglas L. Maskell, Chidamber Kulkarni	A lean FPGA soft processor built using a DSP block.	FPGA	2012	DBLP DOI BibTeX RDF
1	Hugo A. Andrade, Arkadeb Ghosal, Rhishikesh Limaye, Sadia Malik, Newton Petersen, Kaushik Ravindran, Trung N. Tran, Guoqiang Wang, Guang Yang	Early timing estimation for system-level design using FPGAs (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
1	Minxi Jin, Tsutomu Maruyama	A real-time stereo vision system using a tree-structured dynamic programming on FPGA.	FPGA	2012	DBLP DOI BibTeX RDF
1	Scott Bailie, Miriam Leeser	Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation.	FPGA	2012	DBLP DOI BibTeX RDF
1	Charles Eric LaForest, Ming G. Liu, Emma Rae Rapati, J. Gregory Steffan	Multi-ported memories for FPGAs via XOR.	FPGA	2012	DBLP DOI BibTeX RDF
1	Matthias Hinkfoth, Enrico Heinrich, Sebastian Vorköper, Volker Kühn 0001, Ralf Salomon	X-ORCA: FPGA-based wireless localization in the sub-millimeter range.	FPGA	2012	DBLP DOI BibTeX RDF
1	Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux	Accelerator compiler for the VENICE vector processor.	FPGA	2012	DBLP DOI BibTeX RDF
1	Jason Xin Zheng, Miodrag Potkonjak	Securing netlist-level FPGA design through exploiting process variation and degradation.	FPGA	2012	DBLP DOI BibTeX RDF
1	Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam	VirtualRC: a virtual FPGA platform for applications and tools portability.	FPGA	2012	DBLP DOI BibTeX RDF
1	Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe	Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
1	Mei Wen, Nan Wu 0003, Qianming Yang, Chunyuan Zhang, Liang Zhao	The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
1	Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer	Leveraging latency-insensitivity to ease multiple FPGA design.	FPGA	2012	DBLP DOI BibTeX RDF
1	Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson	The VTR project: architecture and CAD for FPGAs from verilog to routing.	FPGA	2012	DBLP DOI BibTeX RDF
1	Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski	Impact of FPGA architecture on resource sharing in high-level synthesis.	FPGA	2012	DBLP DOI BibTeX RDF
1	David Boland, George A. Constantinides	A scalable approach for automated precision analysis.	FPGA	2012	DBLP DOI BibTeX RDF
1	Sameh W. Asaad, Ralph Bellofatto, Bernard Brezzo, Chuck Haymes, Mohit Kapur, Benjamin D. Parker, Thomas Roewer, Proshanta Saha, Todd Takken, José A. Tierno	A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation.	FPGA	2012	DBLP DOI BibTeX RDF
1	Maysam Lavasani, Larry Dennison, Derek Chiou	Compiling high throughput network processors.	FPGA	2012	DBLP DOI BibTeX RDF

Publications at "FPGA"( http://dblp.L3S.de/Venues/FPGA )