Search results for "PATMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Raimundo S. Barreto, Fernando F. Carvalho	Towards a Software Power Cost Analysis Framework Using Colored Petri Net.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Y. S. Son, Jong Whoa Na	A New Logic Transformation Method for Both Low Power and High Testability.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Ali Manzak, Chaitali Chakrabarti	Optimum Buffer Size for Dynamic Voltage Processors.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kiyoo Itoh 0001, Kenichi Osada, Takayuki Kawahara	Low-Voltage Embedded RAMs - Current Status and Future Trends.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Hugo De Man	Connecting E-Dreams to Deep-Submicron Realities.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Uri Frank, Ran Ginosar	A Predictive Synchronizer for Periodic Clock Domains.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Patricia Guitton-Ouhamou, Hanene Ben Fradj, Cécile Belleudy, Michel Auguin	Low Power Co-design Tool and Power Optimization of Schedules and Memory System.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Albert Koelmans, Danil Sokolov, Alexandre Yakovlev	A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Christos Drosos, Labros Bisdounis, Dimitris Metafas, Spyros Blionas, Anna Tatsaki	A Multi-level Validation Methodology for Wireless Network Applications.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Geoff V. Merrett, Bashir M. Al-Hashimi	Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø	A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Nick Kanopoulos	Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Sabino Salerno, Enrico Macii, Massimo Poncino	A Low-Power Encoding Scheme for GigaByte Video Interfaces.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Idris Kaya, Silke Salewski, Markus Olbrich, Erich Barke	Wirelength Reduction Using 3-D Physical Design.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Alberto García Ortiz, Tudor Murgan, Manfred Glesner	Moment-Based Estimation of Switching Activity for Correlated Distributions.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson	An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Myeong-Hoon Oh, Dong-Soo Har	A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis 0001	Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti	Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel	Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet	Noise Margin in Low Power SRAM Cells.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis 0001	A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo	Power Aware Dividers in FPGA.	PATMOS	2004	DBLP DOI BibTeX RDF
1	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne	Temperature Dependence in Low Power CMOS UDSM Process.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors	On Skin Effect in On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Domenik Helms, Eike Schmidt, Wolfgang Nebel	Leakage in CMOS Circuits - An Introduction.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Amjad Mohsen, Richard Hofmann	Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Yijun Liu, Stephen B. Furber	Minimizing the Power Consumption of an Asynchronous Multiplier.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar	The Certainty of Uncertainty: Randomness in Nanometer Design.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti	A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.	PATMOS	2004	DBLP DOI BibTeX RDF	chipcards, cryptography, Differential power analysis, DPA, power analysis, countermeasures
1	Lap-Fai Leung, Chi-Ying Tsui, Xiaobo Sharon Hu	Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis	Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Panagiotis D. Vouzis, Vassilis Paliouras	Optimal Logarithmic Representation in Terms of SNR Behavior.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Jihong Ren, Mark R. Greenstreet	Crosstalk Cancellation for Realistic PCB Buses.	PATMOS	2004	DBLP DOI BibTeX RDF
1	André K. Nieuwland, Atul Katoch, Maurice Meijer	Reducing Cross-Talk Induced Power Consumption and Delay.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Emanuele Lattanzi, Andrea Acquaviva, Alessandro Bogliolo	Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Markus Tahedl, Hans-Jörg Pfleiderer	Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Anders Brødløs Olsen, Finn Büttner, Peter Koch 0001	On Combined DVS and Processor Evaluation.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger	A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Peter Celinski, Derek Abbott, Sorin Cotofana	Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Athanasios Kakarountas, Vassilis Spiliotopoulos, Spiridon Nikolaidis 0001, Constantinos E. Goutis	The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Milos Krstic, Eckhard Grass	GALSification of IEEE 802.11a Baseband Processor.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Matthias Müller 0002, Andreas Wortmann 0002, Dominik Mader, Sven Simon 0001	Register Isolation for Synthesizable Register Files.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Howard Chen 0001, Daniel L. Ostapko	Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Tobias Gemmeke, Tobias G. Noll	A Physically Oriented Model to Quantify the Noise-on-Delay Effect.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel	Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Jun-Cheol Park, Vincent John Mooney III, Philipp Pfeiffenberger	Sleepy Stack Reduction of Leakage Power.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Gabriella Trucco, Giorgio Boselli, Valentino Liberali	A Study of Crosstalk Through Bonding and Package Parasitics in CMOS Mixed Analog-Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Sonia López, Oscar Garnica, José Manuel Colmenar	Enhancing GALS Processor Performance Using Data Classification Based on Data Latency.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae	A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne	Design Optimization with Automated Cell Generation.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Gianluca Palermo, Cristina Silvano	PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures.	PATMOS	2004	DBLP DOI BibTeX RDF
1	D. J. Kinniment, Alexandre Yakovlev	Low Latency Synchronization Through Speculation.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
1	Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin 0001	SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani	High Yield Standard Cell Libraries: Optimization and Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Mark G. Arnold	LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS.	PATMOS	2004	DBLP DOI BibTeX RDF
1	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne	Physical Extension of the Logical Effort Model.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin	TAST Profiler and Low Energy Asynchronous Design Methodology.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Jürgen Fischer, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, Doris Schmitt-Landsiedel	Power Supply Net for Adiabatic Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Murali Jayapala, Tom Vander Aa, Francisco Barat, Francky Catthoor, Henk Corporaal, Geert Deconinck	L0 Cluster Synthesis and Operation Shuffling.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Jie Ruan, Mark G. Arnold	Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos	Design of High-Speed Low-Power Parallel-Prefix VLSI Adders.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Claudia Kretzschmar, Torsten Bitterlich, Dietmar Müller 0001	A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada	A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Christian Schuster, Jean-Luc Nagel, Christian Piguet, Pierre-André Farine	Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat	Power Consumption of Performance-Scaled SIMD Processors.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Nikolaos Vassiliadis, A. Chormoviti, Nikolaos Kavvadias, Spiridon Nikolaidis 0001	The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Armin Wellig, Julien Zory, Norbert Wehn	Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
1	David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris	Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Fei Li 0003, Lei He 0001, Joseph M. Basile, Rakesh J. Patel, Hema Ramamurthy	High Level Area and Current Estimation.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Amirali Baniasadi	Power-Aware Branch Predictor Update for High-Performance Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Milos Krstic, Eckhard Grass	New GALS Technique for Datapath Architectures.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev 0001, Kanad Ghose	Energy Efficient Register Renaming.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Konstantinos Tatas, Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas	Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.	PATMOS	2003	DBLP DOI BibTeX RDF
1	M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Paul Flugger	RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Vissarion Ferentinos, M. Milia, Gauthier Lafruit, Jan Bormans, Francky Catthoor	Memory Compaction and Power Optimization for Wavelet-Based Coders.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Josep Rius 0001, Alejandro Peidro, Salvador Manich, Rosa Rodríguez-Sánchez	Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Seyed Reza Abdollahi, Bertan Bakkaloglu, S. K. Hosseini	A Fully Digital Numerical-Controlled-Oscillator.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién	A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo	State Encoding for Low-Power FSMs in FPGA.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Ricardo Augusto da Luz Reis	Power and Timing Driven Physical Design Automation.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Hoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija	Energy Optimization of High-Performance Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
1		Power Management in Synopsys Galaxy Design Platform.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Theodore Laopoulos, Labros Bisdounis, Spyros Blionas	Instruction Level Energy Modeling for Pipelined Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
1	S. Cservany, Jean-Marc Masgonty, Christian Piguet	Stand-by Power Reduction for Storage Circuits.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Tim Schoenauer, Jörg Berthold, Christoph Heer	Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies.	PATMOS	2003	DBLP DOI BibTeX RDF
1		Open Multimedia Platform for Next-Generation Mobile Devices.	PATMOS	2003	DBLP DOI BibTeX RDF
1	José L. Ayala, Marisa Luisa López-Vallejo	A Unified Framework for Power-Aware Design of Embedded Systems.	PATMOS	2003	DBLP DOI BibTeX RDF
1	E. Seebacher, Gerhard Rappitsch, H. Höller	Process Characterization for Low VTH and Low Power Design.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor	Instruction Buffering Exploration for Low Energy Embedded Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Bahman Javadi, Mohsen Naderi, Hossein Pedram, Ali Afzali-Kusha, Mohammad K. Akbari	An Asynchronous Viterbi Decoder for Low-Power Applications.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Antun Domic	The Emergency of Design for Energy Efficiency: An EDA Perspective.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Raúl Jiménez, Pilar Parra Fernández, Pedro Sanmartín, Antonio J. Acosta 0001	A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Sampo Tuuna, Jouni Isoaho	Estimation of Crosstalk Noise for On-Chip Buses.	PATMOS	2003	DBLP DOI BibTeX RDF
1	B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu	Statistical Power Estimation of Behavioral Descriptions.	PATMOS	2003	DBLP DOI BibTeX RDF

Publications at "PATMOS"( http://dblp.L3S.de/Venues/PATMOS )