Search results for "SBCCI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Daniel N. Ruiz, Robson L. Moreno, Tales Cleber Pimenta	Design of a class D amplifier for hearing aid devices.	SBCCI	2007	DBLP DOI BibTeX RDF	class D amplifier, hearing aid devices
1	Fernando de Souza Campos, Ognian Marinov, Naser Faramarzpour, Fayçal Saffih, M. Jamal Deen, Jacobus W. Swart	A multisampling time-domain CMOS imager with synchronous readout circuit.	SBCCI	2007	DBLP DOI BibTeX RDF	fill-factor, dynamic range, CMOS imager, active pixel sensor
1	Agnes Sarolta Nagy, Alicia Polanco, Manuel Alvarez	Contributions to improve design accuracy of bipolar ics via physical effects.	SBCCI	2007	DBLP DOI BibTeX RDF	base-emitter capacitance model, emission coefficient, physical effects
1	Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis 0001	Cell placement on graphics processing units.	SBCCI	2007	DBLP DOI BibTeX RDF	cell placement, CAD, GPU, GPGPU, quadratic placement, stream processor
1	Walter J. Lancioni, Pablo A. Petrashin, Luis E. Toledo, Carlos Dualibe	A 9.6 kb/s CMOS FSK modem for data transmission through power lines.	SBCCI	2007	DBLP DOI BibTeX RDF	analog CMOS, power line transceiver, switched capacitor amplifier
1	J. V. R. Ravindra, Srinivas Bala Mandalika	Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.	SBCCI	2007	DBLP DOI BibTeX RDF	RC, distributed RLC, interconnect, SPICE, circuit, RL
1	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Bus encoding schemes for minimizing delay in VLSI interconnects.	SBCCI	2007	DBLP DOI BibTeX RDF	bus encoding technique, crosstalk class, delay, encoder, decoder, VLSI interconnects
1	Jens Petter Abrahamsen, Tor Sverre Lande	Soft-well digital circuit design.	SBCCI	2007	DBLP DOI BibTeX RDF	well biasing, reliability, low power design
1	Marcio Barbosa Lucks, Nobuo Oki	Radial basis function network applied to the linearization of a voltage controlled oscillator.	SBCCI	2007	DBLP DOI BibTeX RDF	artificial neural networks, radial basis function, linearization, VCO, operational transconductance amplifier
1	Jose Marcelo Lima Duarte, Francisco das Chagas Mota, Manoel J. M. Carvalho	Digital PM demodulator for brazilian data collecting system.	SBCCI	2007	DBLP DOI BibTeX RDF	BDCS, control system theory, FPGA, PLL, phase locked loop
1	Edgard de Faria Corrêa, Leonardo Alves de Paula e Silva, Flávio Rech Wagner, Luigi Carro	Fitting the router characteristics in NoCs to meet QoS requirements.	SBCCI	2007	DBLP DOI BibTeX RDF	QoS, embedded systems, real time, systems-on-chip, networks-on-chip
1	César Augusto Prior, Cesar Ramos Rodrigues, João Baptista dos Santos Martins, André Luiz Aita, Filipe Costa Beber Vieira	Design of an integrated low power high CMRR instrumentation amplifier for biomedical applications.	SBCCI	2007	DBLP DOI BibTeX RDF	higth CMRR, low power, analog integrated circuits, current mode, instrumentation amplifier
1	Juan Núñez 0002, José M. Quintana, Maria J. Avedillo	A quasi-differential quantizer based on SMOBILE.	SBCCI	2007	DBLP DOI BibTeX RDF	multi-valued logic circuits, emerging technologies, resonant tunneling diode
1	John M. Espinosa-Duran, Jaime Velasco-Medina, Gloria Huertas, José Luis Huertas	Total ionizing dose effects in switched-capacitor filters using oscillation-based test.	SBCCI	2007	DBLP DOI BibTeX RDF	design for testability, oscillation-based test
1	Leonel Tedesco, Fernando Moraes 0001, Ney Calazans	Buffer sizing for QoS flows in wormhole packet switching NoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	quality of service, networks on chip, traffic modeling, buffer sizing
1	C. N. M. Marins, Luiz C. Kretly	Minimizing the mismatch errors at the VCO and cascode buffer connections in front end of BiCMOS RFICs operating on S band.	SBCCI	2007	DBLP DOI BibTeX RDF	Gm LC configuration oscillator, SiGe BiCMOS .35?m technology, cascode configuration, VCO, front-ends
1	Fernando da Rocha Paixão Cortes, Sergio Bampi	A fully integrated CMOS RF front-end for a multi-band analog mixed-signal interface.	SBCCI	2007	DBLP DOI BibTeX RDF	RF front-end, VGA, analog/RF design, frequency translation, mixer
1	Mauricio Ayala-Rincón, Thomas Mailleux Santana	SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS.	SBCCI	2006	DBLP DOI BibTeX RDF
1	Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski	Using a software testing technique to identify registers for partial scan implementation.	SBCCI	2006	DBLP DOI BibTeX RDF	hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
1	Leonel Tedesco, Aline Mello 0001, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes	Application driven traffic modeling for NoCs.	SBCCI	2006	DBLP DOI BibTeX RDF	QoS, applications, networks on chip, traffic modeling
1	Reiner W. Hartenstein	The re-definition of low power design for HPC: a paradigm shift.	SBCCI	2006	DBLP DOI BibTeX RDF
1	Ana Isabela Araújo Cunha, Ali M. Niknejad	A general domain CMOS companding integrator.	SBCCI	2006	DBLP DOI BibTeX RDF	CMOS integrators, companding circuits, log-domain integrators, square-root domain integrators
1	Francisco Assis Moreira do Nascimento, Marcio F. da S. Oliveira, Marco A. Wehrmeister, Carlos Eduardo Pereira, Flávio Rech Wagner	MDA-based approach for embedded software generation from a UML/MOF repository.	SBCCI	2006	DBLP DOI BibTeX RDF	UML, MDA, design space exploration, embedded systems design
1	Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón, Rudi H. van Els, Renato P. Almeida	Implementation of dispatching algorithms for elevator systems using reconfigurable architectures.	SBCCI	2006	DBLP DOI BibTeX RDF	elevator group control system, field programmable gate arrays
1	Leomar S. da Rosa Jr., Felipe S. Marques 0001, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	Fast disjoint transistor networks from BDDs.	SBCCI	2006	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, switch theory, CMOS gates
1	Andrès E. Lagos	High performance silicon MEMS for niche market applications.	SBCCI	2006	DBLP DOI BibTeX RDF
1	Pablo Aguirre, Fernando Silveira	Bias circuit design for low-voltage cascode transistors.	SBCCI	2006	DBLP DOI BibTeX RDF	CMOS, low voltage, analog design
1	Paulo Sérgio B. do Nascimento, Manoel Eusébio de Lima, Stelita M. da Silva, Jordana L. Seixas	Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGA-computers, area-time trade-offs, temporal partitioning techniques, image processing, design space exploration
1	Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota	Evaluation of SEU and crosstalk effects in network-on-chip switches.	SBCCI	2006	DBLP DOI BibTeX RDF	network-on-chip, crosstalk, single-event upset
1	Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali	Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs.	SBCCI	2006	DBLP DOI BibTeX RDF	crosstalk, mixed-signal ICs
1	Alessandro Girardi, Sergio Bampi	Power constrained design optimization of analog circuits based on physical gm/ID characteristics.	SBCCI	2006	DBLP DOI BibTeX RDF	simulated annealing, synthesis, analog design
1	Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro	A cell library for low power high performance CMOS voltage-mode quaternary logic.	SBCCI	2006	DBLP DOI BibTeX RDF	quaternary logic design, voltage-mode, multi-valued logic
1	Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi	A band-pass Gm-C Filter design based on gm/ID methodology and characterization.	SBCCI	2006	DBLP DOI BibTeX RDF	continuous-time band-pass filter, transconductor amplifier, design methodology, analog circuits
1	Valeria Bertacco	Formal verification for real-world designs.	SBCCI	2006	DBLP DOI BibTeX RDF
1	Jozias Oliveira, André Printes, R. C. S. Freire, Elmar U. K. Melcher, Ivan S. S. Silva	FPGA architecture for static background subtraction in real time.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGA, real time, background subtraction
1	Valeria Bertacco	Low maintenance verification.	SBCCI	2006	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro	Cache performance impacts for stack machines in embedded systems.	SBCCI	2006	DBLP DOI BibTeX RDF	stack machines, Java, power consumption, cache memory, MIPS
1	Sandro A. P. Haddad, Wouter A. Serdijn	An ultra low-power class-AB sinh integrator.	SBCCI	2006	DBLP DOI BibTeX RDF	Sinh integrator, analog electronics, class-AB integrator, log-domain filters, low-power circuit design
1	Heiner Giefers, Achim Rettberg	Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	high-level synthesis, low power design, voltage scaling, bit-serial architecture
1	Gilson I. Wirth, Ivandro Ribeiro, Michele G. Vieira, Fernanda Gusmão de Lima Kastensmidt	Single event transients in dynamic logic.	SBCCI	2006	DBLP DOI BibTeX RDF	integrated circuits, dynamic logic, single event transients
1	Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi	ByZFAD: a low switching activity architecture for shift-and-add multipliers.	SBCCI	2006	DBLP DOI BibTeX RDF	adder bypass, byZFAD, hot-block ring counter, shiftand-add multiplier, low-power, switching activity
1	Mário P. Véstias, Horácio C. Neto	Area and performance optimization of a generic network-on-chip architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGA, system-on-chip, network-on-chip
1	Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes 0001	Infrastructure for dynamic reconfigurable systems: choices and trade-offs.	SBCCI	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, NoCs, configuration controllers
1	David Déharbe, Sérgio Medeiros 0001	Aspect-oriented design in systemC: implementation and applications.	SBCCI	2006	DBLP DOI BibTeX RDF	aspect-oriented programming, systemC, hardware description languages
1	Katarina Paulsson, Michael Hübner 0001, Jürgen Becker 0001	On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives.	SBCCI	2006	DBLP DOI BibTeX RDF	dynamic and partial FPGA reconfiguration, on-line adaptation, power dissipation
1	Todd M. Austin	Robust low power computing in the nanoscale era.	SBCCI	2006	DBLP DOI BibTeX RDF
1	Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich	Dynamic task binding for hardware/software reconfigurable networks.	SBCCI	2006	DBLP DOI BibTeX RDF	online hardware/software partitioning, fault-tolerance, reconfigurable system
1	Luis Henrique de Carvalho Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije	Ultra low-voltage ultra low-power CMOS threshold voltage reference.	SBCCI	2006	DBLP DOI BibTeX RDF	low power, CMOS, low voltage, threshold voltage, voltage reference
1	Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis 0001	Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.	SBCCI	2006	DBLP DOI BibTeX RDF	fault-tolerant microprocessor, soft errors, single event upsets, single event transients
1	Fabio Lacerda, Stefano Pietri, Alfredo Olmos	A differential switched-capacitor amplifier with programmable gain and output offset voltage.	SBCCI	2006	DBLP DOI BibTeX RDF	differential to single ended, switched capacitor stage, analog integrated circuits
1	A. A. Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Bégueret	4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversion.	SBCCI	2006	DBLP DOI BibTeX RDF	bandpass delta-sigma modulator, continuous-time delta-sigma modulator, high order noise-shaping, high-IF sampling, multi-feedback architecture, A/D conversion
1	Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami	REDEFIS: a system with a redefinable instruction set processor.	SBCCI	2006	DBLP DOI BibTeX RDF	ISA customization, dynamically reconfigurable processor, low power, SoC, high performance
1	Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi	Ant colony based routing architecture for minimizing hot spots in NOCs.	SBCCI	2006	DBLP DOI BibTeX RDF	dynamic routing algorithm, network on chip
1	Todd M. Austin	Razor: a low-power pipeline based on circuit-level timing speculation.	SBCCI	2006	DBLP DOI BibTeX RDF
1	André V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira 0001	Using NEXUS compliant debuggers for real time fault injection on microprocessors.	SBCCI	2006	DBLP DOI BibTeX RDF	on chip debug, real time systems, fault injection
1	Elias Teodoro Silva Jr., Flávio Rech Wagner, Edison Pignaton de Freitas, Carlos Eduardo Pereira	Hardware support in a middleware for distributed and real-time embedded applications.	SBCCI	2006	DBLP DOI BibTeX RDF	real-time systems, middleware, energy efficiency, MPSoCs, embedded applications
1	Jürgen Becker 0001, Michael Hübner 0001	Run-time reconfigurabilility and other future trends.	SBCCI	2006	DBLP DOI BibTeX RDF	dynamic and partial reconfiguration, reconfigurable hardware and systems, embedded systems, adaptivity
1	Carlos Roberto Moratelli, Érika F. Cota, Marcelo Lubaszewski	A cryptography core tolerant to DFA fault attacks.	SBCCI	2006	DBLP DOI BibTeX RDF	cryptography, smart cards, fault attacks
1	Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis 0001	Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.	SBCCI	2006	DBLP DOI BibTeX RDF	3d circuits, cell shifting, placement, quadratic placement
1	Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro 0001	Exploiting general coefficient representation for the optimal sharing of partial products in MCMs.	SBCCI	2006	DBLP DOI BibTeX RDF	common subexpression elimination (CSE), digital filter design, minimal signed digit (MSD), multiple constant multiplication (MCM)
1	Claudionor José Nunes Coelho Jr., Ricardo P. Jacobi, Jürgen Becker 0001 (eds.)	Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006	SBCCI	2006	DBLP BibTeX RDF
1	Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.	A fast SAT solver algorithm best suited to reconfigurable hardware.	SBCCI	2006	DBLP DOI BibTeX RDF	formal verification, SAT, CNF, DPLL
1	R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis	Asynchronous circuit design on reconfigurable devices.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGAs, asynchronous circuits
1	Michael Hübner 0001, Jürgen Becker 0001	Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration.	SBCCI	2006	DBLP DOI BibTeX RDF	designflow, dynamic and partial reconfiguration, reconfigurable hardware
1	Hamilton Klimach, Márcio C. Schneider, Carlos Galup-Montoro	A test chip for automatic MOSFET mismatch characterization.	SBCCI	2006	DBLP DOI BibTeX RDF	matching, characterization, analog design, MOSFET, mismatch
1	Alfredo Arnaud	An efficient chopper amplifier, using a switched Gm-C Filter technique.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, CMOS, analog design
1	Shugang Wei	Number conversions between RNS and mixed-radix number system based on Modulo (2p - 1) signed-digit arithmetic.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Renato Fernandes Hentschke, Jagannathan Narasimhan, David S. Kung 0001	Improving run times by pruned application of synthesis transforms.	SBCCI	2005	DBLP DOI BibTeX RDF	synthesis, filtering, buffering, driver, resizing
1	Carlos Galup-Montoro, Sergio Bampi, Alex Orailoglu (eds.)	Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005	SBCCI	2005	DBLP DOI BibTeX RDF
1	Carlos Galup-Montoro, Márcio C. Schneider, Viriato C. Pahim	Fundamentals of next generation compact MOSFET models.	SBCCI	2005	DBLP DOI BibTeX RDF	MOSFET model, inversion-charge model, surface potential model, compact model
1	Luca Benini	Energy efficient NoC design.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Mariano Aguirre, Mónico Linares Aranda	An alternative logic approach to implement high-speed low-power full adder cells.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, high-speed, full adder
1	Bastian Knerr, Martin Holzer 0002, Markus Rupp	Task sheduling for power optimisation of multi frequency synchronous data flow graphs.	SBCCI	2005	DBLP DOI BibTeX RDF	multi frequency systems, power optimisation, synchronous data flow graphs, task scheduling, frequency scaling
1	Luca Benini	Advanced power management of SoC platforms.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Alfredo Arnaud, Rafaella Fiorelli, Carlos Galup-Montoro	On the design of very small transconductance OTAs with reduced input offset.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, CMOS, analog design
1	Sujan Pandey, Manfred Glesner, Max Mühlhäuser	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.	SBCCI	2005	DBLP DOI BibTeX RDF	on-chip communication architecture synthesis, optimization, algorithms
1	Frank Sill, Frank Grassert, Dirk Timmermann	Total leakage power optimization with improved mixed gates.	SBCCI	2005	DBLP DOI BibTeX RDF	MVT, leakage currents, threshold voltage
1	Carlos Dualibe, Pablo A. Petrashin, Luis E. Toledo, Walter J. Lancioni	New low-voltage electrically tunable triode-MOSFET transconductor and its application to low-frequency Gm-C filtering.	SBCCI	2005	DBLP DOI BibTeX RDF	Gm-C filter, analog CMOS, low-frequency, transconductor, low-power, low-voltage, instrumentation amplifier
1	Paul L. Jespers	A survey of multistep A to D converters and error correction mechanisms.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Carlos Arthur Lang Lisbôa, Erik Schüler, Luigi Carro	Going beyond TMR for protection against multiple faults.	SBCCI	2005	DBLP DOI BibTeX RDF	future technologies, simultaneous transient faults, fault tolerance, design techniques
1	Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski	A constraint-based solution for on-line testing of processors embedded in real-time applications.	SBCCI	2005	DBLP DOI BibTeX RDF	test space exploration, real-time systems, embedded processors, on-line testing, software-based self-test
1	Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes 0001	Current mask generation: a transistor level security against DPA attacks.	SBCCI	2005	DBLP DOI BibTeX RDF	cryptography, side channel attacks, DPA, countermeasures
1	Angel M. Gómez Argüello, João Navarro Jr., Wilhelmus A. M. Van Noije	A 3.5 mW programmable high speed frequency divider for a 2.4 GHz CMOS frequency synthesizer.	SBCCI	2005	DBLP DOI BibTeX RDF	high speed digital circuit, low power, prescaler, frequency synthesizer
1	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
1	José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin	Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.	SBCCI	2005	DBLP DOI BibTeX RDF	traffic effect, networks-on-chip, energy estimation, application mapping
1	Florian Dittmann 0001, Markus Heberling	Placement of intermodule connections on partially reconfigurable devices.	SBCCI	2005	DBLP DOI BibTeX RDF	intermodule communication, reconfigurable computing, run-time reconfiguration
1	Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro	Exploiting Java through binary translation for low power embedded reconfigurable systems.	SBCCI	2005	DBLP DOI BibTeX RDF	java, power consumption, binary translation, reconfigurable processors
1	Armando Gomes, Edevaldo Pereira S. Júnior, Ivan Carlos Ribeiro do Nascimento	EMC-EMI optimized high speed CAN line driver.	SBCCI	2005	DBLP DOI BibTeX RDF	CAN interface, driver circuits, line driver, twisted-pair, physical interface
1	Leonel Tedesco, Aline Mello 0001, Diego Garibotti, Ney Calazans, Fernando Moraes 0001	Traffic generation and performance evaluation for mesh-based NoCs.	SBCCI	2005	DBLP DOI BibTeX RDF	performance evaluation, networks on chip, traffic modeling
1	Edson P. Santana, N. R. Ferreira, Carlos Eduardo Trabuco Dórea, Ana Isabela Araújo Cunha	On the adequate transistor modeling for optimal design of CMOS OTA.	SBCCI	2005	DBLP DOI BibTeX RDF	ACM model, CMOS integrated circuits, operational transconductance amplifiers
1	John Sanguinetti	High level design: the future is now.	SBCCI	2005	DBLP DOI BibTeX RDF
1	Élvio Dutra, Leandro Soares Indrusiak, Manfred Glesner	Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator.	SBCCI	2005	DBLP DOI BibTeX RDF	addressing scheme, gauss, noise generator, noise, lookup-table, normal distribution, white noise, LUT, transformation function, probability distribution function
1	Nikolay Rubanov	An efficient subcircuit recognition using the nonlinear graph matching.	SBCCI	2005	DBLP DOI BibTeX RDF	subcircuit recognition, graph matching, design verification
1	Conrado Rossi, Pablo Aguirre	Ultra-low power CMOS cells for temperature sensors.	SBCCI	2005	DBLP DOI BibTeX RDF	micropower, CMOS, voltage reference, temperature sensor, current reference
1	Júlio C. B. de Mattos, Emilena Specht, Bruno Neves, Luigi Carro	Making object oriented efficient for embedded system applications.	SBCCI	2005	DBLP DOI BibTeX RDF	java, object-oriented, design space exploration, embedded software
1	Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001	Design of a radix-2m hybrid array multiplier using carry save adder format.	SBCCI	2005	DBLP DOI BibTeX RDF	hybrid multiplier, low power, carry save adder
1	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi	T-shaped association of transistors: modeling of multiple channel lengths and regular associations.	SBCCI	2005	DBLP DOI BibTeX RDF	associations of transistors, modeling, analog design, MOSFET
1	C. P. Moreira, Eric Kerherve, Pierre Jarry, Didier Belot	Dual-standard BiCMOS LNA for DCS1800/W-CDMA applications.	SBCCI	2005	DBLP DOI BibTeX RDF	dual-standard dual-mode operation, noise/input impedance optimization methodology, low-noise amplifier, BiCMOS
1	Leonardo Barboni, Rafaella Fiorelli	Design and power optimization of CMOS RF blocks operating in the moderate inversion region.	SBCCI	2005	DBLP DOI BibTeX RDF	amplifier design, radio frequency integrated circuits, CMOS integrated circuits, power optimization
1	Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt	Single event transients in combinatorial circuits.	SBCCI	2005	DBLP DOI BibTeX RDF	soft errors, integrated circuits, single event transients

Publications at "SBCCI"( http://dblp.L3S.de/Venues/SBCCI )