Search results for "SOC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Luca Larcher, Paolo Pavan, Alfonso Maurelli	Flash Memories for SoC: An Overview on System Constraints and Technology Issues, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
22	Holger Blume, Thorsten von Sydow, Tobias G. Noll	Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets.	SAMOS	2004	DBLP DOI BibTeX RDF
22	Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane, Michel Langevin, Damien Lyonnard	Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding.	DATE	2004	DBLP DOI BibTeX RDF
22	Nikolaos D. Liveris, Prithviraj Banerjee	Power Aware Interface Synthesis for Bus-Based SoC Design.	DATE	2004	DBLP DOI BibTeX RDF
22	Krisztián Flautner, David Flynn, David Roberts, Dipesh I. Patel	IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling.	DATE	2004	DBLP DOI BibTeX RDF
22	Dan Hillman	Using Mobilize Power Management IP for Dynamic & Static Power Reduction in SoC at 130 nm.	DATE	2004	DBLP DOI BibTeX RDF
22	Mohamed-Anouar Dziri, Wander O. Cesário, Flávio Rech Wagner, Ahmed Amine Jerraya	Unified Component Integration Flow for Multi-Processor SoC Design and Validation.	DATE	2004	DBLP DOI BibTeX RDF
22	Sungjoo Yoo, Mohamed-Wassim Youssef, Aimen Bouchhima, Ahmed Amine Jerraya, Mario Diaz-Nava	Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software.	DATE	2004	DBLP DOI BibTeX RDF
22	Wei-Lun Wang	March Based Memory Core Test Scheduling for SOC.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
22	Mark Holland, Scott Hauck	Automatic Creation of Reconfigurable PALs/PLAs for SoC.	FPL	2004	DBLP DOI BibTeX RDF
22	Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski	Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.	SBCCI	2004	DBLP DOI BibTeX RDF	system-on-chip, BIST, power aware, mixed-signal test
22	Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu	Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, embedded software, multi-processor systems
22	Adriano Sarmento, Wander O. Cesário, Ahmed Amine Jerraya	Automatic Building of Executable Models from Abstract SoC Architectures Made of Heterogeneous Subsystems.	IEEE International Workshop on Rapid System Prototyping	2004	DBLP DOI BibTeX RDF
22	Javier Vicente, Juan Miguel García-Gómez, César Vidal, Luis Martí-Bonmatí, Aurora del Arco, Montserrat Robles	SOC: A Distributed Decision Support Architecture for Clinical Diagnosis.	ISBMDA	2004	DBLP DOI BibTeX RDF
22	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	A Scalable Communication-Centric SoC Interconnect Architecture.	ISQED	2004	DBLP DOI BibTeX RDF	switch-based interconnect, butterfly fat-tree, global wire delay, System on chip, interconnect architecture, timing closure
22	Lane Albanese	Managing Derivative SoC Design Projects to Better Results.	ISQED	2004	DBLP DOI BibTeX RDF
22	Jitendra Khare	Memory Yield Improvement - SoC Design Perspective.	ITC	2004	DBLP DOI BibTeX RDF
22	Yervant Zorian	Investment vs. Yield Relationship for Memories in SOC.	ITC	2004	DBLP DOI BibTeX RDF
22	K. Nikila, Rubin A. Parekhji	DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.	ITC	2004	DBLP DOI BibTeX RDF
22	Ramalingam Sridhar	System-on-Chip (SoC): Clocking and Synchronization Issues.	VLSI Design	2004	DBLP DOI BibTeX RDF
22	Jörg Henkel	Closing the SoC Design Gap.	Computer	2003	DBLP DOI BibTeX RDF
22	Ozgur Sinanoglu, Alex Orailoglu	Compacting Test Responses for Deeply Embedded SoC Cores.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
22	Md. Saffat Quasem, Zhigang Jiang, Sandeep K. Gupta 0001	Benefits of a SoC-Specific Test Methodology.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
22	M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.	PATMOS	2003	DBLP DOI BibTeX RDF
22	François Rémond, Pierre Bricaud	Set Top Box SoC Design Methodology at STMicroelectronics.	DATE	2003	DBLP DOI BibTeX RDF
22	Sungjoo Yoo, Ahmed Amine Jerraya	Introduction to Hardware Abstraction Layers for SoC.	DATE	2003	DBLP DOI BibTeX RDF
22	Gordon J. Brebner	Eccentric SoC Architectures as the Future Norm.	DSD	2003	DBLP DOI BibTeX RDF
22	Yervant Zorian	Leveraging Infrastructure IP for SoC Yield.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
22	James O. Hamblen	Using an FPGA-based SOC Approach for Senior Design Projects.	MSE	2003	DBLP DOI BibTeX RDF
22	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	SoC design integration by using automatic interconnection rectification.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
22	Mama Hamour, Resve A. Saleh, Shahriar Mirabbasi, André Ivanov	Analog IP design flow for SoC applications.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
22	Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann 0002	Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization.	ASAP	2003	DBLP DOI BibTeX RDF
22	Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi	Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.	DFT	2003	DBLP DOI BibTeX RDF
22	Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang	Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC.	ISQED	2003	DBLP DOI BibTeX RDF
22	Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani	Testing SoC Interconnects for Signal Integrity Using Boundary Scan.	VTS	2003	DBLP DOI BibTeX RDF	Integrity Loss Sensor, System-on-Chip Interconnects, Data Compression, Boundary Scan, Signal Integrity
22	Mohsen Nahvi, André Ivanov	An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores.	VTS	2003	DBLP DOI BibTeX RDF
22	Qiang Xu 0001, Nicola Nicolici	On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.	ITC	2003	DBLP DOI BibTeX RDF
22	Chris Rowen	Reducing SoC Simulation and Development Time.	Computer	2002	DBLP DOI BibTeX RDF
22	Sandeep Koranne	Formulating SoC test scheduling as a network transportation problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
22	Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke	Enhanced Reusability for SoC-Based HW/SW Co-Design.	DSD	2002	DBLP DOI BibTeX RDF
22	Yu Huang 0005, Sudhakar M. Reddy, Wu-Tung Cheng	Core - Clustering Based SOC Test Scheduling Optimization.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
22	Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi	Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model.	CODES	2002	DBLP DOI BibTeX RDF
22	Sazzadur Chowdhury, Majid Ahmadi, Graham A. Jullien, William C. Miller	A MEMS socket system for high density SoC interconnection.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
22	Charlie Chung-Ping Chen, Ed Cheng	Future SoC Design Challenges and Solutions (invited).	ISQED	2002	DBLP DOI BibTeX RDF
22	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	VTS	2002	DBLP DOI BibTeX RDF
22	Yu Huang 0005, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee 0001, Chien-Chung Tsai, Omer Samman, Yahya Zaidan	Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.	ITC	2002	DBLP DOI BibTeX RDF
22	Mohammad H. Tehranipour, Mehrdad Nourani	Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor.	ITC	2002	DBLP DOI BibTeX RDF	Embedded Microprocessor, Integrity Loss, System-on-Chip, Diagnosis, Test Pattern Generation, Signal Integrity, Interconnect Testing, Noise Detection
22	Yu Huang 0005, Nilanjan Mukherjee 0001, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy	Constraint Driven Pin Mapping for Concurrent SOC Testing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
22	Dongxiao Li, Qingdong Yao, Peng Liu 0016, Li Zhou	A bus arbitration scheme for HDTV decoder SoC.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
22	Yervant Zorian	Embedding infrastructure IP for SOC yield improvement.	DAC	2002	DBLP DOI BibTeX RDF	embedded test & repair, semiconductor IP, yield optimization, test resource partitioning
22	Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III	A Comparison of Five Different Multiprocessor SoC Bus Architectures.	DSD	2001	DBLP DOI BibTeX RDF
22	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
22	Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou	An AVPG for SOC design verification with port order fault model.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
22	Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau	Architecture Exploration of Parameterizable EPIC SOC Architectures.	DATE	2000	DBLP DOI BibTeX RDF
21	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre	Test data compression and TAM design.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
21	Davide Pandini, Giuseppe Desoli, Alessandro Cremonesi	Computing and design for software and silicon manufacturing.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
21	Chin-Cheng Kuo, Chien-Nan Jimmy Liu	On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi	Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Sujan Pandey, Nurten Utlu, Manfred Glesner	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann 0001, Wolfgang Rosenstiel	Organic Computing at the System on Chip Level.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu 0001	SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design.	CoRR	2023	DBLP DOI BibTeX RDF
21	Hsun-Wei Cho, Kang G. Shin	Unify: Turning BLE/FSK SoC into WiFi SoC.	MobiCom	2023	DBLP DOI BibTeX RDF
21	Shibo Tang, Xingxin Wang, Yifei Gao, Wei Hu 0008	Accelerating SoC Security Verification and Vulnerability Detection Through Symbolic Execution.	ISOCC	2022	DBLP DOI BibTeX RDF
21	Tian Feng, Haojie Pei, Zhou Jin 0001, Xiao Wu	A survey and perspective on electronic design automation tools for ensuring SoC security.	ISOCC	2022	DBLP DOI BibTeX RDF
21	Wen-Hsin Tsai, Kuei-Ann Wen	SoC Design for Mobile Real-time Badminton Stroke Classification Design.	ISOCC	2022	DBLP DOI BibTeX RDF
21	Syed Muhammad Abubakar, Hanjun Jiang, Yue Yin, Jiahua Shi, Xiaofeng Yang, Wen Jia, Zhihua Wang 0001	A 1.92 μA Always-on ECG Monitoring Mixed-Signal SoC for Implantable Medical Application.	ISOCC	2022	DBLP DOI BibTeX RDF
21	Xingxin Wang, Shibo Tang, Wei Hu 0008	Towards Automatic Property Generation for SoC Security Verification.	ISOCC	2022	DBLP DOI BibTeX RDF
21	Antonio Genov	Power estimation framework based on SystemC-TLM performance models of SoC interconnect and memory systems. (Estimation de la consommation basée sur les modèles de performance SystemC-TLM des systèmes d'interconnexion et de mémoire des SoC).		2021	RDF
21	Tuy Nguyen Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee	Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design.	ISOCC	2021	DBLP DOI BibTeX RDF
21	Jinshan Yue, Wenyu Sun, Huazhong Yang, Yongpan Liu	Challenges and Opportunities of Energy-Efficient CIM SoC Design for Edge AI Devices.	ISOCC	2021	DBLP DOI BibTeX RDF
21	Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Khai-Duy Nguyen, Trong-Thuc Hoang, Koichiro Ishibashi, Cong-Kha Pham	A Low-Power Low-Area SoC based in RISC-V Processor for IoT Applications.	ISOCC	2021	DBLP DOI BibTeX RDF
21	Marco Pagani	Enabling Predictable Hardware Acceleration in Heterogeneous SoC-FPGA Computing Platforms. (Techniques pour l'amélioration de la prévisibilité de l'accélération matérielle pour les plateformes informatiques hétérogènes SoC-FPGA).		2020	RDF
21	Van Loi Le, Taegeun Yoo, Ju Eon Kim, Kwang-Hyun Baek, Tony Tae-Hyoung Kim	A Low-Power Smart Gesture Sensing SoC with On-chip Image Sensor for Smart Devices.	ISOCC	2020	DBLP DOI BibTeX RDF
21	Minji Lee, Changseok Choi, Donghyeon Seo, Byeongjun Bang, Yongseok Kang, Woohyun Paik	Improving Analysis Coverage for Dynamic IR Drop Sign-off in FinFET SoC Design.	ISOCC	2020	DBLP DOI BibTeX RDF
21	Junyoung Kim, Changsun Ahn	Rapid Optimization of Battery Charging- Discharging Profiles Using SOC-SOC Rate Domain for Cruising Hybrid Vehicles.	IEEE Access	2019	DBLP DOI BibTeX RDF
21	Krishnendu Guha, Debasri Saha, Amlan Chakrabarti	Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components.	ACM Trans. Embed. Comput. Syst.	2019	DBLP DOI BibTeX RDF
21	Amal Ben Ameur	Transactional simulation approach for modelling performance and energy of a heterogeneous SoC memory system. (Approche de simulation transactionnelle pour la modélisation des performances et de l'énergie d'un système mémoire pour SoC hétérogènes).		2019	RDF
21	Chabha Hireche	Etude et implémentation sur SoC-FPGA d'une méthode probabiliste pour le contrôle de mission de véhicule autonome. (Study and implementation on SoC-FPGA of a probabilistic method for mission planning in autonomous vehicle).		2019	RDF
21	Prokash Ghosh, Rohit Srivastava	Case Study: SoC Performance Verification and Static Verification of RTL Parameters.	MTV	2019	DBLP DOI BibTeX RDF
21	Mohammad Amir Mansoori, Mario R. Casu	HLS-Based Flexible Hardware Accelerator for PCA Algorithm on a Low-Cost ZYNQ SoC.	NORCAS	2019	DBLP DOI BibTeX RDF
21	Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee	Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications.	ISOCC	2019	DBLP DOI BibTeX RDF
21	Manas Ranjan Meher, Wolfgang Ullmann	An Innovative I/O Budgeting Methodology for Hierarchical SoC Development.	ISOCC	2019	DBLP DOI BibTeX RDF
21	Ines Baccouche, Sabeur Jemmali, Asma Mlayah, Bilal Manai, Najoua Essoukri Ben Amara	Implementation of an Improved Coulomb-Counting Algorithm Based on a Piecewise SOC-OCV Relationship for SOC Estimation of Li-IonBattery.	CoRR	2018	DBLP BibTeX RDF
21	Jie Tang 0003, Bo Yu 0014, Shaoshan Liu, Zhe Zhang 0006, Weikang Fang, Yanjun Zhang	π-SoC: Heterogeneous SoC Architecture for Visual Inertial SLAM Applications.	IROS	2018	DBLP DOI BibTeX RDF
21	Pratheema Mohandoss, Archana Rengaraj	Pre-Silicon DFT Verification on SOC Slim Model.	MTV	2018	DBLP DOI BibTeX RDF
21	Sameh El-Ashry, Ahmed Adel	Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage.	MTV	2018	DBLP DOI BibTeX RDF
21	Luis Cavo, Sebastien Fuhrmann, Liang Liu 0002	Implementation of an Area Efficient Crypto Processor for a NB-IoT SoC Platform.	NORCAS	2018	DBLP DOI BibTeX RDF
21	Erwin Setiawan, Trio Adiono, Syifaul Fuada	PHY Layer Design of OFDM-VLC System based on SoC using Reuse Methodology.	ISOCC	2018	DBLP DOI BibTeX RDF
21	Jill C. Mayeda, Donald Y. C. Lie, Jerry Lopez	A 24-28GHz Reconfigurable CMOS Power Amplifier in 22nm FD-SOI for Intelligent SoC Applications.	ISOCC	2018	DBLP DOI BibTeX RDF
21	Erwin Setiawan, Trio Adiono	Implementation of Systolic Co-processor for Deep Neural Network Inference based on SoC.	ISOCC	2018	DBLP DOI BibTeX RDF
21	Minseo Kim, Jaeeun Jang, Hyunki Kim, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyoung-Rog Lee, Kwantae Kim, Yongsu Lee, Kyuho Jason Lee, Hoi-Jun Yoo	A 1.4-m $\Omega$ -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System.	IEEE J. Solid State Circuits	2017	DBLP DOI BibTeX RDF
21	Minseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, Hoi-Jun Yoo	21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring system.	ISSCC	2017	DBLP DOI BibTeX RDF
21	Sara Zermani	Implémentation sur SoC des réseaux Bayésiens pour l'état de santé et la décision dans le cadre de missions de véhicules autonomes. (SoC implementation of Bayesian networks for health management and decision making for autonomous vehicles missions).		2017	RDF
21	Anand Raman, Yorgos Koutsoyannopoulos, Magdy Abadir	Electromagnetic (EM) Crosstalk Failures and Symptoms in SoC Designs.	MTV	2017	DBLP DOI BibTeX RDF
21	Trio Adiono, Angga Pratama Putra	Hardware/software model of DCO-OFDM based visible light communication SoC using DMA.	ISOCC	2017	DBLP DOI BibTeX RDF
21	Byungki Han, Jongwoo Lee, Seunghyun Oh, Jae-Kwon Kim, Eswar Mamidala, Thomas Byunghak Cho	A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation.	ISOCC	2017	DBLP DOI BibTeX RDF
21	Yonatan Shoshan, Slava Yuzhaninov, Noa Edri, Shay Harari, Yehuda Rudin, Yoav Weizman, Itai Nadler, Nir Rosenberg, Benjamin Flom, Dotan Bechor, Gilad Morag, Evgeny Grigoriants, Naftaly Blum, Ronen Daly, Maya Reuveni, Alexander Fish	A SoC platform for emerging technologies.	ISOCC	2017	DBLP DOI BibTeX RDF
21	Hyoung-Ro Lee, Chi-Ho Lin, Ki-Hyuk Park, Won-Jong Kim, Han-Jin Cho	Development of SoC virtual platform for IoT terminals based on OneM2M.	ISOCC	2017	DBLP DOI BibTeX RDF