Search results for "inductance"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Michael W. Beattie, Lawrence T. Pileggi	Efficient inductance extraction via windowing.	DATE	2001	DBLP DOI BibTeX RDF
16	Tom Chen 0001	On the impact of on-chip inductance on signal nets under the influence of power grid noise.	DATE	2001	DBLP DOI BibTeX RDF
16	Minqing Liu, Tiejun Yu, Wayne Wei-Ming Dai	Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate.	ICCAD	2001	DBLP DOI BibTeX RDF
16	Haitian Hu, Sachin S. Sapatnekar	Circuit-aware on-chip inductance extraction.	CICC	2001	DBLP DOI BibTeX RDF
16	Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton	A fast analytical technique for estimating the bounds of on-chip clock wire inductance.	CICC	2001	DBLP DOI BibTeX RDF
16	Min Xu, Lei He 0001	An efficient model for frequency-dependent on-chip inductance.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF
16	Tak Young	On-Chip Inductance Extraction and Modeling.	ISQED	2001	DBLP DOI BibTeX RDF
16	Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi	Min/max On-Chip Inductance Models and Delay Metrics.	DAC	2001	DBLP DOI BibTeX RDF
16	Michael W. Beattie, Lawrence T. Pileggi	Inductance 101: Modeling and Extraction.	DAC	2001	DBLP DOI BibTeX RDF
16	Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao 0001	Inductance 101: Analysis and Design Issues.	DAC	2001	DBLP DOI BibTeX RDF
16	Kaustav Banerjee, Amit Mehrotra	Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects.	DAC	2001	DBLP DOI BibTeX RDF
16	Li-Fu Chang, Keh-Jeng Chang, Robert Mathews	Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects.	ISPD	2000	DBLP DOI BibTeX RDF	cladding material, copper interconnect, electromagnetic field solvers, skin-effect current distribution
16	Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai	How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K.	ICCAD	2000	DBLP DOI BibTeX RDF
16	Xiaoning Qi, Gaofeng Wang, Zhiping Yu, Robert W. Dutton, Tak Young, Norman Chang	On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation.	CICC	2000	DBLP DOI BibTeX RDF
16	Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis	Theoretical limits for signal reflections due to inductance for on-chip interconnections.	SLIP	2000	DBLP DOI BibTeX RDF
16	Yehea I. Ismail, Eby G. Friedman	Sensitivity of interconnect delay to on-chip inductance.	ISCAS	2000	DBLP DOI BibTeX RDF
16	Chandramouli V. Kashyap, Byron Krauter	A realizable driving point model for on-chip interconnect with inductance.	DAC	2000	DBLP DOI BibTeX RDF	SPICE
16	Tadeusz Skubis, Andrzej Met, Marian Kampik	A bridge for maintenance of inductance standard.	IEEE Trans. Instrum. Meas.	1999	DBLP DOI BibTeX RDF
16	Grégory Servel, L. B. Kenmei, Fabrice Huret, Erick Paleczny, Patrick Kennis, Denis Deschacht	Inductance effect for interconnection timing analysis in submicronic circuits.	ICECS	1999	DBLP DOI BibTeX RDF
16	Lei He 0001, Norman Chang, Shen Lin, O. Sam Nakagawa	An efficient inductance modeling for on-chip interconnects.	CICC	1999	DBLP DOI BibTeX RDF
16	Kenneth L. Shepard, Zhong Tian	Return-limited inductances: a practical approach to on-chip inductance extraction.	CICC	1999	DBLP DOI BibTeX RDF
16	Arani Sinha, Salim Chowdhury	Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction.	CICC	1999	DBLP DOI BibTeX RDF
16	Phillip J. Restle, Albert E. Ruehli, Steven G. Walker	Dealing with Inductance in High-Speed Chip Design.	DAC	1999	DBLP DOI BibTeX RDF
16	Yehea I. Ismail, Eby G. Friedman	Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits.	DAC	1999	DBLP DOI BibTeX RDF
16	Henry Shu-Hung Chung, S. Y. Ron Hui, W. H. Wang	An isolated ZVS/ZCS flyback converter using the leakage inductance of the coupled inductor.	IEEE Trans. Ind. Electron.	1998	DBLP DOI BibTeX RDF
16	Zhijiang He, Lawrence T. Pileggi	A simple algorithm for calculating frequency-dependent inductance bounds.	CICC	1998	DBLP DOI BibTeX RDF
16	Byron Krauter, Sharad Mehrotra	Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
16	Robert A. Groves, David L. Harame, Dale Jadus	Temperature dependence of Q and inductance in spiral inductors fabricated in a silicon-germanium/BiCMOS technology.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
16	Kevin P. Cohen, William M. Ladd, David M. Beams, William S. Sheers, Robert G. Radwin, Willis J. Tompkins, John G. Webster	Comparison of impedance and inductance ventilation sensors on adults during breathing, motion, and simulated airway obstruction.	IEEE Trans. Biomed. Eng.	1997	DBLP DOI BibTeX RDF
16	Sandip Kundu, Uttam Ghoshal	Inductance analysis of on-chip interconnects [deep submicron CMOS].	ED&TC	1997	DBLP DOI BibTeX RDF
16	Tomás Dostál	Synthesis of Switched-Capacitor Inductance Simulation Circuits.	ISCAS	1994	DBLP DOI BibTeX RDF
16	Liviu Goras, Cornelia Marcuta	On linear inductance- and capacitance-time conversions using NIC-type configurations.	IEEE Trans. Ind. Electron.	1993	DBLP DOI BibTeX RDF
16	Mattan Kamon, Michael J. Tsuk, Jacob White 0001	FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program.	DAC	1993	DBLP DOI BibTeX RDF
16	James N. Humenik, James M. Oberschmidt, Leon L. Wu, Scott G. Paull	Low-inductance decoupling capacitor for the thermal conduction modules of the IBM Enterprise System/9000 processors.	IBM J. Res. Dev.	1992	DBLP DOI BibTeX RDF
16	Mattan Kamon, Michael J. Tsuk, C. Smithhisler, Jacob K. White 0001	Efficient techniques for inductance extraction of complex 3-D geometries.	ICCAD	1992	DBLP DOI BibTeX RDF
16	H. Craig Miller	Inductance formula for a single-layer circular coil.	Proc. IEEE	1987	DBLP DOI BibTeX RDF
16	Richard Lundin	A handbook formula for the inductance of a single-layer circular coil.	Proc. IEEE	1985	DBLP DOI BibTeX RDF
10	Vinayak Honkote, Baris Taskin	PEEC based parasitic modeling for power analysis on custom rotary rings.	ISLPED	2010	DBLP DOI BibTeX RDF	resonant clocking, simulation, modeling, interconnect
10	Tarek A. El-Moselhy, Luca Daniel	Stochastic dominant singular vectors method for variation-aware extraction.	DAC	2010	DBLP DOI BibTeX RDF	intrusive algorithms, stochastic PDEs, stochastic dominant singular vectors, variation-aware extraction, stochastic simulation, integral equations, surface roughness, parasitic extraction
10	Yoonjung Yang, Gilsoo Cho	Novel Stretchable Textile-Based Transmission Bands: Electrical Performance and Appearance after Abrasion/Laundering, and Wearability.	HCI (3)	2009	DBLP DOI BibTeX RDF	stretchable textile-based transmission band, silicon-coated stainless steel multifilament yarn, abrasion, laundering, electrical resistance, MP3 player jacket, wear sensation, image analysis
10	Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shayan Arani, A. Ege Engin, Chung-Kuan Cheng	Predicting the worst-case voltage violation in a 3D power network.	SLIP	2009	DBLP DOI BibTeX RDF	worst case violation prediction, integer linear programming, leakage, clock gating, power networks
10	Nima Hosseini, Hooman Nabovati	New geometry for improving Q-factor of spiral integrated inductor on low cost integrated circuit process.	CCECE	2009	DBLP DOI BibTeX RDF
10	Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester	Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny	On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Sampo Tuuna, Li-Rong Zheng 0001, Jouni Isoaho, Hannu Tenhunen	Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
10	Amit Goel, Sarma B. K. Vrudhula	Current source based standard cell model for accurate signal integrity and timing analysis.	DATE	2008	DBLP DOI BibTeX RDF
10	Tuck Boon Chan, Hsinchia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen	LTCC spiral inductor modeling, synthesis, and optimization.	ASP-DAC	2008	DBLP DOI BibTeX RDF
10	Massimo Alioto, Massimo Poli, Gaetano Palumbo	Explicit energy evaluation in RLC tree circuits with ramp inputs.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Wen-Chieh Wang, Chang-Ping Liao, Yi-Kai Lo, Zue-Der Huang, Fadi Riad Shahroury, Chung-Yu Wu	The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Hailin Jiang, Malgorzata Marek-Sadowska	Power gating scheduling for power/ground noise reduction.	DAC	2008	DBLP DOI BibTeX RDF	scheduling, power gating, power supply noise
10	James D. Ma, Rob A. Rutenbar	Interval-Valued Reduced-Order Statistical Interconnect Modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Martin Saint-Laurent	A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh	Two-Stage Newton-Raphson Method for Transistor-Level Simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Sanjay Pant, Eli Chiprout, David T. Blaauw	Power Grid Physics and Implications for CAD.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	R, L(di/dt), decap, locality, resonance, power supply networks
10	Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud	Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect.	ASP-DAC	2007	DBLP DOI BibTeX RDF
10	Mehmet Zeki Bilgin	A Sensorless Initial Rotor Position Sensing Using Neural Network for Direct Torque Controlled Permanent Magnet Synchronous Motor Drive.	ICANNGA (2)	2007	DBLP DOI BibTeX RDF
10	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).	ISCAS	2007	DBLP DOI BibTeX RDF
10	Philippe Artillan, Bruno Estibals, Alain Salles, Jean Abboud, Pierre Aloisi, Corinne Alonso	A PEEC approach for circular spiral inductive components modeling.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Jeffrey S. Walling, David J. Allstot	Monolithic Spiral Transformers: A Design Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Jonathan Rosenfeld, Eby G. Friedman	Quasi-Resonant Interconnects: A Low Power Design Methodology.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Fan Yang 0001, Xuan Zeng 0001, Yangfeng Su, Dian Zhou	RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Burak Kelleci, Edgar Sánchez-Sinencio, Aydin I. Karsilayan	THD+Noise Estimation in Class-D Amplifiers.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Arthur Nieuwoudt, Yehia Massoud	Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions.	ISQED	2007	DBLP DOI BibTeX RDF
10	Jae-sun Seo, Prashant Singh, Dennis Sylvester, David T. Blaauw	Self-Time Regenerators for High-Speed and Low-Power Interconnect.	ISQED	2007	DBLP DOI BibTeX RDF
10	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Weiping Shi	An Efficient Algorithm for RLC Buffer Insertion.	ISQED	2007	DBLP DOI BibTeX RDF
10	Zhenyu Qi, Hao Yu 0001, Pu Liu, Sheldon X.-D. Tan, Lei He 0001	Wideband passive multiport model order reduction and realization of RLCM circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Modeling and analysis of crosstalk noise in coupled RLC interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	James D. Ma, Rob A. Rutenbar	Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Soroush Abbaspour, Hanif Fatemi, Massoud Pedram	Non-gaussian statistical interconnect timing analysis.	DATE	2006	DBLP DOI BibTeX RDF
10	Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera	Interconnect RL extraction at a single representative frequency.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri	Controlling inductive cross-talk and power in off-chip buses using CODECs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan	Adaptive admittance-based conductor meshing for interconnect analysis.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Trong-Yen Lee, Yang-Hsin Fan, Chia-Chun Tsai	Reduction of RLC Tree Delay Using Bidirectional Buffer Repeater Insertion.	ICICIC (2)	2006	DBLP DOI BibTeX RDF
10	Nicola Diolaiti, Günter Niemeyer	Wave Haptics: Providing Stiff Coupling to Virtual Environments.	HAPTICS	2006	DBLP DOI BibTeX RDF	Motor Dynamics, Wave Variables, Current
10	Kenneth A. Townsend, James W. Haslett	Low-power Q-enhancement for parallel LC tanks.	ISCAS	2006	DBLP DOI BibTeX RDF
10	S. Vatti, Christos Papavassiliou	New LC oscillator topology in CMOS 0.18µm technology.	ISCAS	2006	DBLP DOI BibTeX RDF
10	H. J. Kadim, Lacina M. Coulibaly	EM-based analytical model for estimation of worst-case crosstalk noise.	ISCAS	2006	DBLP DOI BibTeX RDF
10	H. J. Kadim, Lacina M. Coulibaly	Wave propagation based analytical model for distributed on-chip RLC interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Magnus G. J. Lind, Guy Albert Dumont, William G. Dunford	Analysis of a circuit exhibiting ferroresonance.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Behzad Mesgarzadeh, Atila Alvandpour	A wide-tuning range 1.8 GHz quadrature VCO utilizing coupled ring oscillators.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao	Coupling aware RLC-based clock routings for crosstalk minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Tadashi Suetsugu, Marian K. Kazimierczuk	Integration of class DE inverter for on-chip DC-DC power supplies.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Xu Zhang, Xiaohong Jiang 0001, Susumu Horiguchi	A non-orthogonal clock distribution network and its performance evaluation in presence of process variations and inductive effects.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	H-Tree, X Architecture, performance evluation, variant X-Tree, clock distribution network
10	Krishnamoorthy Natarajan, S. J. Nagalakshmi	Repeater Sizing and Insertion Length of Interconnect to Minimize the Overall Time Delay using a Truncated Fourier Series Approach.	CCECE	2006	DBLP DOI BibTeX RDF
10	N. Hassaïne, L. Villeneuve, Y. Shen, F. Concilio	Modeling of Tape Automated Bonding (TAB) for High Performance Integrated Circuits.	CCECE	2006	DBLP DOI BibTeX RDF
10	Atef Shamim, Peter H. R. Popplewell, Victor Karam, Langis Roy, John W. M. Rogers, Calvin Plett	Silicon Differential Antenna/Inductor for Short Range Wireless Communication Applications.	CCECE	2006	DBLP DOI BibTeX RDF
10	Bassel Soudan	Reducing Inductive Coupling Skew in Wide Global Signal Busses.	DELTA	2006	DBLP DOI BibTeX RDF
10	Chia-Chieh Tu, Ching-Yuan Yang	A 6.5-GHz LC VCO with Integrated-Transformer Tuning.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Shao-Hua Lee, Yun-Hsueh Chuang, Li-Ren Chi, Sheng-Lyang Jang, Jian-Feng Lee	A Low-Voltage 2.4GHz VCO with 3D Helical Inductors.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Sanjay Pant, Eli Chiprout	Power grid physics and implications for CAD.	DAC	2006	DBLP DOI BibTeX RDF	Ldi/dt, decap, locality, IR, resonance, power supply networks
10	Monica Gentili, Pitu B. Mirchandani	Locating Active Sensors on Traffic Networks.	Ann. Oper. Res.	2005	DBLP DOI BibTeX RDF	network covering problems, linearly independent equations, sensors, location theory, traffic networks
10	Yu Cao 0001, Xuejue Huang, Dennis Sylvester, Tsu-Jae King 0001, Chenming Hu	Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Amin Q. Safarian, Ahmad Yazdi, Payam Heydari	Design and analysis of an ultrawide-band distributed CMOS mixer.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Guoqing Chen, Eby G. Friedman	An RLC interconnect model based on fourier analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Kai Wang 0011, Malgorzata Marek-Sadowska	On-chip power-supply network optimization using multigrid-based technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Sheldon X.-D. Tan	A general hierarchical circuit modeling and simulation algorithm.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Hao Yu 0001, Lei He 0001, Zhenyu Qi, Sheldon X.-D. Tan	A wideband hierarchical circuit reduction for massively coupled interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Hongyu Chen, Chung-Kuan Cheng	A multi-level transmission line network approach for multi-giga hertz clock distribution.	ASP-DAC	2005	DBLP DOI BibTeX RDF
10	Kai-Sheng Lu, Xiao-Yu Feng, Guo-Zhang Gao	The separability, reducibility and controllability of RLCM networks over F(z).	ISCAS (1)	2005	DBLP DOI BibTeX RDF