Search results for "interconnects"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner	A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Jun Tao 0001, Xuan Zeng 0001, Fan Yang 0001, Yangfeng Su, Lihong Feng, Wei Cai 0003, Dian Zhou, Charles C. Chiang	A one-shot projection method for interconnects with process variations.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Cristian Grecu, André Ivanov, Res Saleh, Egor S. Sogomonyan, Partha Pratim Pande	On-line Fault Detection and Location for NoC Interconnects.	IOLTS	2006	DBLP DOI BibTeX RDF
19	Ki-Young Kim, Seung-Yong Kim, Seok-Yoon Kim	An Efficient Delay Metric on RC Interconnects Under Saturated Ramp Inputs.	ICCSA (4)	2006	DBLP DOI BibTeX RDF
19	Xiangyuan Liu, Shuming Chen	Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	low-swing interconnect, delay, power, estimation model
19	Iñigo Artundo, Daniel Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont	Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior.	ISPA Workshops	2006	DBLP DOI BibTeX RDF	interconnection network, multiprocessors, Reconfiguration, distributed shared memory, context switch
19	Yuxin Wang, D. Makadia, Martin Margala	On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects.	CCECE	2006	DBLP DOI BibTeX RDF
19	Michael Kagan	InfiniBand interconnects - Application acceleration through MPI overlap.	SC	2006	DBLP DOI BibTeX RDF
19	Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Dian Zhou	A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.	APCCAS	2006	DBLP DOI BibTeX RDF
19	Vinita V. Deodhar, Jeffrey A. Davis	Optimization of throughput performance for low-power VLSI interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
19	Peter Benkart, Alexander Kaiser 0002, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher	3D Chip Stack Technology Using Through-Chip Interconnects.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Integrated Circuits General, General
19	Simon Schneider, Ulrich Mueller, Dirk Tiegelbekkers	A Reactive Workload Generation Framework for Simulation-based Performance Engineering of System Interconnects.	MASCOTS	2005	DBLP DOI BibTeX RDF
19	Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis	Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David T. Blaauw	Statistical modeling of cross-coupling effects in VLSI interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
19	Ranjit Noronha, Dhabaleswar K. Panda 0001	Performance Evaluation of MM5 on Clusters with Modern Interconnects: Scalability and Impact.	Euro-Par	2005	DBLP DOI BibTeX RDF	MM5, Clusters, InfiniBand, Myrinet, System Area Networks, Quadrics
19	Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu	Prediction of delay time for future LSI using on-chip transmission line interconnects.	SLIP	2005	DBLP DOI BibTeX RDF
19	Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner	A linear model for high-level delay estimation in VDSM on-chip interconnects.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
19	Guoqing Chen, Eby G. Friedman	Low power repeaters driving RLC interconnects with delay and bandwidth constraints.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
19	Arkadiy Morgenshtein, Israel Cidon, Ran Ginosar, Avinoam Kolodny	Low-leakage repeaters for NoC interconnects.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
19	Hao Yu 0001, Lei He 0001	A sparsified vector potential equivalent circuit model for massively coupled interconnects.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
19	B. Afkal, Ali Afzali-Kusha, Mahmoud El Nokali	Efficient power model for crossbar interconnects.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
19	Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi	Electrical and optical on-chip interconnects in scaled microprocessors.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
19	Haixia Gao, Yintang Yang, Xiaohua Ma, Gang Dong	Testing for Resistive Shorts in FPGA Interconnects.	ISQED	2005	DBLP DOI BibTeX RDF
19	Muzhou Shao, Youxin Gao, Li-Pen Yuan, Hung-Ming Chen, Martin D. F. Wong	Current Calculation on VLSI Signal Interconnects.	ISQED	2005	DBLP DOI BibTeX RDF
19	Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das	A low latency router supporting adaptivity for on-chip interconnects.	DAC	2005	DBLP DOI BibTeX RDF	networks, networks-on-chip, interconnection, adaptive routing
19	Jiuxing Liu, B. Chandrasekaran 0001, Weikuan Yu, Jiesheng Wu, Darius Buntinas, Sushmitha P. Kini, Dhabaleswar K. Panda 0001, Pete Wyckoff	Microbenchmark Performance Comparison of High-Speed Cluster Interconnects.	IEEE Micro	2004	DBLP DOI BibTeX RDF
19	Yi Zhao, Sujit Dey, Li Chen	Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
19	Atul Maheshwari, Wayne P. Burleson	Differential current-sensing for on-chip interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
19	Tom Chen 0001, Amjad Hajjar	Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors	On Skin Effect in On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
19	Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects.	PATMOS	2004	DBLP DOI BibTeX RDF
19	Lei Wang, Sandeep K. Gupta 0001, Melvin A. Breuer	Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
19	Davide Pandini, Cristiano Forzan, Livio Baldi	Design Methodologies and Architecture Solutions for High-Performance Interconnects.	ICCD	2004	DBLP DOI BibTeX RDF
19	Yuantao Peng, Xun Liu	Power macromodeling of global interconnects considering practical repeater insertion.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, interconnect, macromodeling, repeater insertion
19	Medha Kulkarni, Tom Chen 0001	A Sensitivity Based Approach to Analyzing Signal Delay Uncertainty of Coupled Interconnects.	ISQED	2004	DBLP DOI BibTeX RDF
19	Zhenghao Zhang, Yuanyuan Yang	Optimal Parallel Scheduling Algorithm for WDM Optical Interconnects with Recirculating Buffering.	ICPP	2004	DBLP DOI BibTeX RDF
19	Yariv Aridor, Tamar Domany, Oleg Goldshmidt, Edi Shmueli, José E. Moreira, Larry Stockmeier	Multi-toroidal Interconnects: Using Additional Communication Links to Improve Utilization of Parallel Computers.	JSSPP	2004	DBLP DOI BibTeX RDF
19	Mehdi Baradaran Tahoori	A high resolution diagnosis technique for open and short defects in FPGA interconnects.	FPGA	2003	DBLP DOI BibTeX RDF
19	Dinesh Pamunuwa, Shauki Elassaad, Hannu Tenhunen	Analytic Modeling of Interconnects for Deep Sub-Micron Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
19	Eun Jung Kim 0001, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das	Energy optimization techniques in cluster interconnects.	ISLPED	2003	DBLP DOI BibTeX RDF	buffer design, cluster interconnect, dynamic link shutdown, link design, dynamic voltage scaling, energy optimization, switch design
19	Krishna Kant 0001, Ravishankar K. Iyer	Design and Performance of Compressed Interconnects for High Performance Servers.	ICCD	2003	DBLP DOI BibTeX RDF
19	Takayuki Watanabe, Hideki Asai	Analysis of PCB interconnects using electromagnetic reduction technique.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
19	Atul Maheshwari, Wayne P. Burleson	Repeater and current-sensing hybrid circuits for on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	interconnect circuits, delay, power, area
19	Mehdi Baradaran Tahoori	Application-Dependent Testing of FPGA Interconnects.	DFT	2003	DBLP DOI BibTeX RDF
19	Chanhee Oh, David T. Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta	Static Electromigration Analysis for Signal Interconnects.	ISQED	2003	DBLP DOI BibTeX RDF
19	Tom Chen 0001, Amjad Hajjar	Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics.	ISQED	2003	DBLP DOI BibTeX RDF
19	Mehdi Baradaran Tahoori	Using satisfiability in application-dependent testing of FPGA interconnects.	DAC	2003	DBLP DOI BibTeX RDF	field-programmable gate array, interconnect
19	Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, Barry J. Rubin, Howard H. Smith	A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
19	Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria	A practical approach to model long MIS interconnects in VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
19	Yu-Shun Guo	Transient simulation of high-speed interconnects based on thesemidiscretization of Telegrapher's equations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
19	Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson	Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
19	Qinwei Xu, Pinaki Mazumder	Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects.	DATE	2002	DBLP DOI BibTeX RDF
19	Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj	Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model .	DATE	2002	DBLP DOI BibTeX RDF
19	Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy 0001, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond	Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).	MTDT	2002	DBLP DOI BibTeX RDF
19	Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave
19	Wendemagegnehu T. Beyene, Chuck Yuan	On the Use of Windows for Accurate Analysis of Package Interconnects.	ISQED	2002	DBLP DOI BibTeX RDF
19	Gaofeng Wang, Xiaoning Qi, Zhiping Yu, Robert W. Dutton	Accurate Model of Metal-Insulator-Semiconductor Interconnects.	ISQED	2002	DBLP DOI BibTeX RDF
19	Amir Attarha, Mehrdad Nourani	Test Pattern Generation for Signal Integrity Faults on Long Interconnects.	VTS	2002	DBLP DOI BibTeX RDF
19	Yi Zhao, Li Chen, Sujit Dey	On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips.	ITC	2002	DBLP DOI BibTeX RDF
19	Woojin Jin, Yungseon Eo, William R. Eisenstadt, Jongin Shim	Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
19	Prashant Saxena, C. L. Liu 0001	Optimization of the maximum delay of global interconnects duringlayer assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
19	Hüseyin Özkaramanli	A comparison of strong and weak distributed transverse couplingbetween VLSI interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
19	Wenjian Yu, Zeyi Wang	An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects.	ASP-DAC	2001	DBLP DOI BibTeX RDF
19	Ankireddy Nalamalpu, Wayne P. Burleson	Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters.	ISPD	2001	DBLP DOI BibTeX RDF	methodology, timing, interconnect, buffering
19	Dinesh Pamunuwa, Hannu Tenhunen	Repeater Insertion To Minimise Delay In Coupled Interconnects.	VLSI Design	2001	DBLP DOI BibTeX RDF
19	Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya	Modeling of Nonuniform Interconnects by Using Differential Quadrature Method.	VLSI Design	2001	DBLP DOI BibTeX RDF
19	Zheng-Yu Yuan, Zheng-Fan Li, Min-Liu Zou	Computer-aided analysis of on-chip interconnects near semiconductorsubstrate for high-speed VLSI.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Dennis W. Prather	Three Dimensional VLSI-Scale Interconnects.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
19	Chauchin Su, Shyh-Jye Jou	Decentralized BIST Methodology for System Level Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, BIST, DFT, boundary scan
19	Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi	Adaptive Fault Detection and Diagnosis of RAM Interconnects.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	interconnect, memory, diagnosis, detection, wiring
19	Chi-Feng Wu, Cheng-Wen Wu	Testing Interconnects of Dynamic Reconfigurable FPGAs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
19	Takayuki Watanabe, Hideki Asai	Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
19	Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	Structural diagnosis of interconnects by coloring.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	interconnect, diagnosis, graph coloring, syndrome, balanced code
19	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Bridging Fault Detection in FPGA Interconnects Using IDDQ.	FPGA	1998	DBLP DOI BibTeX RDF
19	Chunming Qiao, Yousong Mei	On the Multiplexing Degree Required to Embed Permutations in a Class of Networks with Direct Interconnects.	HPCA	1996	DBLP DOI BibTeX RDF	permutation embedding, multiplexing degree, rearrangeably nonblocking, all-optical networksThis research is supported in part by a grant from NSF under contract MIP-9409854, routing
19	Po-Ching Hsu, Sying-Jyan Wang	Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
19	Xiao-Tao Chen, Fabrizio Lombardi	A coloring approach to the structural diagnosis of interconnects.	ICCAD	1996	DBLP DOI BibTeX RDF	interconnect, Diagnosis, graph coloring, syndrome
19	Rohini Gupta, Byron Krauter, Lawrence T. Pileggi	On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects.	VLSI Design	1996	DBLP DOI BibTeX RDF
19	Dong H. Xie, Michel S. Nakhla	Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	N. de Beaucoudrey, A. Bellemain, D. Phalippou, P. Chavel, D. Fortin, Iaakov Exman, Larry Rudolph, J. P. Schnell, J. P. Pocholle	Optical Interconnects for Parallel Systems: Demonstration on an Optical Link with Multiple-Quantum-Well Opto-Electronic Arrays.	PARLE	1992	DBLP DOI BibTeX RDF
15	Angela C. Sodan, Jacob Machina, Arash Deshmeh, Kevin Macnaughton, Bryan Esbaugh	Parallelism via Multithreaded and Multicore CPUs.	Computer	2010	DBLP DOI BibTeX RDF	Multithreaded cores, Heterogeneous cores, Application-level parallelism, Chip interconnects, GPUs, Multicore processors, Power efficiency
15	Randy Wayne Morris Jr., Avinash Karanth Kodi	Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores.	NOCS	2010	DBLP DOI BibTeX RDF	Network-on-Chip, Interconnects, Low-Power architecture, Optoelectronic
15	Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun	Power-efficient variation-aware photonic on-chip network management.	ISLPED	2010	DBLP DOI BibTeX RDF	networks on chip, optical interconnects, nanophotonics
15	Valeriu Beiu, Walid Ibrahim, Rafic Z. Makki	On Wires Holding a Handful of Electrons.	NanoNet	2009	DBLP DOI BibTeX RDF	Nano-electronics, interconnects (wires), noise (intrinsic), reliability, communication
15	Yitzhak Birk, Vladimir Zdornov	Improving communication-phase completion times in HPC clusters through congestion mitigation.	SYSTOR	2009	DBLP DOI BibTeX RDF	congestion control, interconnects, adaptive routing, congestion, InfiniBand, computer clusters
15	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	An interconnect-aware delay model for dynamic voltage scaling in NM technologies.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dynamic voltage scaling (dvs), interconnects, delay model
15	Renatas Jakushokas, Eby G. Friedman	Simultaneous shield and repeater insertion.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	delay, interconnects, noise, power, area
15	Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi	Phastlane: a rapid transit optical routing network.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, multicore, optical interconnects, nanophotonics
15	Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha	Toward Ideal On-Chip Communication Using Express Virtual Channels.	IEEE Micro	2008	DBLP DOI BibTeX RDF	packet switching, flow control, on-chip interconnects, router design
15	Sarita V. Adve, David M. Brooks, Craig B. Zilles	Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007.	IEEE Micro	2008	DBLP DOI BibTeX RDF	Top Picks, reliability, computer architecture, transactional memory, variability, on-chip interconnects, compiler-architecture interactions, memory system design
15	Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles 0001, José Flich, José Duato	FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing.	HiPC	2008	DBLP DOI BibTeX RDF	Congestion Control, Distributed Routing, High-Performance Interconnects
15	David H. Albonesi	Standing on Solid Ground.	IEEE Micro	2007	DBLP DOI BibTeX RDF	interconnects for multicore chips, special-purpose chips, debugging, human-computer interface, microarchitecture, programmability
15	Pradip Bose	Robust On-Chip Communication.	IEEE Micro	2006	DBLP DOI BibTeX RDF	high-performance computing, on-chip interconnects
15	Nian-Feng Tzeng	Routing Table Partitioning for Speedy Packet Lookups in Scalable Routers.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	line cards, prefix matching search, routing table lookups, Caches, interconnects, routers, tries, forwarding engines
15	Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano	A Simple Data Transfer Technique Using Local Address for Networks-on-Chips.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	table-lookup routing, interconnection networks, Networks-on-chips, streaming processing, reconfigurable systems, on-chip interconnects
15	Tobias Bjerregaard, Shankar Mahadevan	A survey of research and practices of Network-on-chip.	ACM Comput. Surv.	2006	DBLP DOI BibTeX RDF	Chip-area networks, GSI design, OCP, ULSI design, communication-centric design, SoC, system-on-chip, network-on-chip, interconnects, NoC, GALS, sockets, on-chip communication, communication abstractions
15	Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, Mahmoud Shahram, Kishore Singhal	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	measurement, process variations, extraction, VLSI interconnects
15	Hyong-youb Kim, Scott Rixner, Vijay S. Pai	Network Interface Data Caching.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	local interconnects, operating systems, Web servers, network interfaces
15	Rajesh K. Gupta 0001	On-chip networks.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	integration, SoCs, networks on chips, on-chip interconnects