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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 18662 occurrences of 5027 keywords
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Results
Found 21661 publication records. Showing 21661 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | William S. Song |
High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Andrew Stone, Elias S. Manolakos |
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 92-102, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity |
17 | Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor |
Performance and Reliability Verification of C6201/C6701 Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 521-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
17 | Jeffry T. Russell, Margarida F. Jacome |
Software power estimation and optimization for high performance, 32-bit embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 328-333, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | David Li, Andrew Pua, Pranjal Srivastava, Uming Ko |
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 726-731, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Jude A. Rivers, Edward S. Tam, Edward S. Davidson |
On Effective Data Supply For Multi-Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '97, Austin, Texas, USA, October 12-15, 1997, pp. 519-528, 1997, IEEE Computer Society, 0-8186-8206-X. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Jean-Paul Theis, Lothar Thiele |
VLIW-Processors under Periodic Real Time Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 191-199, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Risc architecture, frontend compilers, embedded systems |
17 | Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes |
Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 468-477, 1996, IEEE Computer Society, 0-8186-7554-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen |
Architectural Verification of Processors Using Symbolic Instruction Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 454-459, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | S. Surya, Pradip Bose, Jacob A. Abraham |
Architectural Performance Verification: PowerPCTM Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '94, Cambridge, MA, USA, October 10-12, 1994, pp. 344-347, 1994, IEEE Computer Society, 0-8186-6565-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | W. H. Chou, Sun-Yuan Kung |
Register transfer modeling and simulation for array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application Specific Array Processors, ASAP 1994, Proceedings, San Francisco, CA, USA, 22-24 August, 1994, pp. 111-122, 1994, IEEE, 0-8186-6517-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Miodrag Potkonjak, Mani B. Srivastava |
Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application Specific Array Processors, ASAP 1994, Proceedings, San Francisco, CA, USA, 22-24 August, 1994, pp. 45-56, 1994, IEEE, 0-8186-6517-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Yusuke Mishina, Keiji Kojima |
String Matching on IDP: A String Matching Algorithm for Vector Processors and Its Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 394-401, 1993, IEEE Computer Society, 0-8186-4230-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe |
A Split Data Cache for Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 32-39, 1993, IEEE Computer Society, 0-8186-4230-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Chia-Jiu Wang, Frank Emnett |
Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 102-105, 1993, IEEE Computer Society, 0-8186-4230-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Michel Auguin, Fernand Boéri, C. Carrière, G. Menez |
Synthesis of dedicated SIMD processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993, pp. 416-427, 1993, IEEE, 0-8186-3492-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Chie Dou |
A highly-parallel match architecture for AI production systems using application-specific associative matching processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993, pp. 180-183, 1993, IEEE, 0-8186-3492-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Zheng Zhou, Wayne P. Burleson |
Formal descriptions, semantics and verification of VLSI array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993, pp. 321-332, 1993, IEEE, 0-8186-3492-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Alfred Strey |
Implementation of large neural associative memories by massively parallel array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993, pp. 357-368, 1993, IEEE, 0-8186-3492-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Dong-wan Tcha, Bum-il Lee, Toung-duck Lee |
Processors Selection and Traffic Splitting in a Parallel Processors System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Acta Informatica ![In: Acta Informatica 29(5), pp. 415-423, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | George A. Sai-Halasz |
Directions in Futrue High End Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 230-233, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Amar Mukherjee |
Determining longest common subsequences of two sequences on a linear array of processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1992, Proceedings of the International Conference on, Berkeley, CA, USA, 4-7 August, 1992, pp. 526-537, 1992, IEEE, 0-8186-2967-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Brion L. Keller, David A. Haynes |
Design Automation of Test for the EX/9000TM Series Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 550-553, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, K. Yano, M. Hiraki, S. Shukuri, T. Nishida |
On-Chip Multiple Superscalar Processors with Secondary Cache Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '91, Cambridge, MA, USA, October 14-16, 1991, pp. 128-131, 1991, IEEE Computer Society, 0-8186-2270-9. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Jens Franzen |
A design method for on-line reconfigurable array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, 1991. Proceedings of the International Conference on, Barcelona, Spain, 2-4 Sept., 1991, pp. 387-401, 1991, IEEE, 0-8186-9237-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Glen G. Langdon Jr. |
Book review: Solving Problems on Concurrent Processors, Vol II: Software for Concurrent Processors by I. Angus, G. Fox, J. Kim, and D. Walker (Prentice-Hall, 1990). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 18(4), pp. 90-91, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | David J. Lilja, Pen-Chung Yew |
Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP (1) ![In: Proceedings of the 1990 International Conference on Parallel Processing, Urbana-Champaign, IL, USA, August 1990. Volume 1: Architecture., pp. 563-564, 1990, Pennsylvania State University Press, 0-271-00728-1. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
|
17 | Jack S. N. Jean |
Fault-tolerant array processors using N-and-half-track switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990, pp. 426-437, 1990, IEEE, 0-8186-9089-5. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Zicheng Guo, Rami G. Melhem |
Embedding pyramids in array processors with pipelined busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990, pp. 665-676, 1990, IEEE, 0-8186-9089-5. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | A. P. Marriott, Andrew W. G. Duller, Richard H. Storer, Andrew R. Thomson, Mike R. Pout |
Towards the automated design of application specific array processors (ASAPs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990, pp. 414-425, 1990, IEEE, 0-8186-9089-5. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | R. M. Lea |
ASP modules: building-blocks for application-specific massively parallel processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990, pp. 493-504, 1990, IEEE, 0-8186-9089-5. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
17 | Yi-Chieh Chang, Kang G. Shin |
A module-sliced approach for high yield VLSI/WSI processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989, pp. 500-503, 1989, IEEE, 0-8186-1971-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago |
High performance I/O processors for real-time pulse handling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989, pp. 415-418, 1989, IEEE, 0-8186-1971-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Yervant Zorian, Najmi Jarwala |
Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1989. Proceedings., 1989 IEEE International Conference on, Cambridge, MA, USA, October 2-4, 1989, pp. 580-584, 1989, IEEE, 0-8186-1971-6. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
17 | Shannon Shen 0002, Surendar Magar, Raul Aguilar, Gerry Luikuo, Mike Fleming, K. Rishavy, K. Murphy, C. Furman |
A high performance CMOS chipset for FFT processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 578-581, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | H. V. Jagadish |
Sorting on an array of processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 36-39, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Vincenzo Piuri, Renato Stefanelli |
Use of redundant binary representation for fault-tolerant arithmetic array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 496-501, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Fausto Distante, Vincenzo Piuri |
APES: an integrated system for behavioral design, simulation and evaluation of array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 568-572, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Glenn Hinton, Konrad Lai, Randy Steck |
Microarchitecture of the 80960 high-integration processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 362-365, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Masood Namjoo |
First 32-bit SPARC-based processors implemented in high-speed CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 374-376, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | S. H. Hosseini |
On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 554-559, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
17 | Chang-Biau Yang, Richard C. T. Lee |
The mapping of 2-D array processors to 1-D array processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Parallel Comput. ![In: Parallel Comput. 3(3), pp. 217-229, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
17 | W. J. Van Gils |
How to Cope with Faulty Processors in a Completely Connected Network of Communicating Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 20(4), pp. 207-213, 1985. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
15 | John Sartori, Rakesh Kumar 0002 |
Overscaling-friendly timing speculation architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 209-214, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
stochastic processors, timing speculation, adaptability |
15 | Vahid Kazempour, Ali Kamali, Alexandra Fedorova |
AASH: an asymmetry-aware scheduler for hypervisors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VEE ![In: Proceedings of the 6th International Conference on Virtual Execution Environments, VEE 2010, Pittsburgh, Pennsylvania, USA, March 17-19, 2010, pp. 85-96, 2010, ACM, 978-1-60558-910-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
heterogeneous, scheduling algorithms, multicore processors, virtual machine monitor, hypervisor, asymmetric |
15 | Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik |
On approximating the ideal random access machine by physical machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 56(5), pp. 27:1-27:57, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Physical constraints on machines, pipelined hierarchical memory, speculative processors |
15 | Minwook Ahn, Yunheung Paek |
Register coalescing techniques for heterogeneous register architecture with copy sifting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 8(2), pp. 16:1-16:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, compiler, Register allocation, embedded processors, register coalescing |
15 | Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor |
Playing the trade-off game: Architecture exploration using Coffeee. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(3), pp. 36:1-36:37, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction |
15 | Nikolaos Kavvadias, Spiridon Nikolaidis 0001 |
Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(2), pp. 200-214, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design |
15 | Jeffrey R. Diamond, Behnam Robatmili, Stephen W. Keckler, Robert A. van de Geijn, Kazushige Goto, Doug Burger |
High performance dense linear algebra on a spatially distributed processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2008, Salt Lake City, UT, USA, February 20-23, 2008, pp. 63-72, 2008, ACM, 978-1-59593-795-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
gotoblas, grid processors, hybrid dataflow, matrix multiply, tile based architecture, instruction level parallelism, on-chip networks, dense linear algebra |
15 | Peter James Leadbitter, Dan Page, Nigel P. Smart |
Nondeterministic Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(7), pp. 992-998, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Side-channel analysis, multithreaded processors |
15 | Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham |
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 83-92, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
source-level transformations, compilers, design space exploration, ASIPs, instruction set extension, customizable processors |
15 | Minwook Ahn, Jooyeon Lee, Yunheung Paek |
Optimistic coalescing for heterogeneous register architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 93-102, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
heterogeneous register architecture, register coalesing, compiler, register allocation, embedded processors |
15 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001 |
A Retargetable Software Timing Analyzer Using Architecture Description Language. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 396-401, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis |
15 | Tomás Hrubý, Kees van Reeuwijk, Herbert Bos |
Ruler: high-speed packet matching and rewriting on NPUs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2007, Orlando, Florida, USA, December 3-4, 2007, pp. 1-10, 2007, ACM, 978-1-59593-945-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
TDFA, regular expressions, network processors, deep packet inspection |
15 | Björn Franke, Michael F. P. O'Boyle |
A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(3), pp. 234-245, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
conversion from sequential to parallel forms, modeling, evaluation, compilers, measurement, performance measures, interprocessor communications, arrays, real-time and embedded systems, restructuring, Parallel processors, simulation of multiple-processor systems, reverse engineering and reengineering, signal processing systems |
15 | Zhen Chen 0001, Chuang Lin 0002, Jia Ni, Dong-Hua Ruan, Bo Zheng, Yixin Jiang |
AntiWorm NPU-based Parallel Bloom Filters for TCP/IP Content Processing in Giga-Ethernet LAN. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCN ![In: 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 15-17 November 2005, Sydney, Australia, Proceedings, pp. 748-755, 2005, IEEE Computer Society, 0-7695-2421-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
TCP/IP Protocol suite, Parallel Bloom Filter, Stateful TCP inspection, Network Security, Network Processors, Worms, Deep Packet Inspection |
15 | Ada Gavrilovska, Karsten Schwan |
Addressing data compatibility on programmable network platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2005, Princeton, New Jersey, USA, October 16-18, 2005, pp. 125-134, 2005, ACM, 1-59593-082-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data morphing, network processors, streaming applications |
15 | Rashmi Bajaj, Dharma P. Agrawal |
Improving Scheduling of Tasks in a Heterogeneous Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 15(2), pp. 107-118, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
network of processors, directed acyclic graph, Communication cost, heterogeneous environment, optimal scheduling, computational cost, task duplication |
15 | Enrico Angelelli, Á. B. Nagy, Maria Grazia Speranza, Zsolt Tuza |
The On-Line Multiprocessor Scheduling Problem with Known Sum of the Tasks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Sched. ![In: J. Sched. 7(6), pp. 421-428, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
competitive analysis, parallel processors, on-line scheduling |
15 | Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero |
Evaluating kilo-instruction multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WMPI ![In: Proceedings of the 3rd Workshop on Memory Performance Issues, in conjunction with the 31st International Symposium on Computer Architecture 2004, Munich, Germany, June 20, 2004, pp. 72-79, 2004, ACM, 1-59593-040-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ROB, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, kilo-instruction processors |
15 | Pepijn J. de Langen, Ben H. H. Juurlink |
Reducing traffic generated by conflict misses in caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 235-239, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
caches, embedded processors, power reduction, conflict misses |
15 | Daniel Kästner, Stephan Wilhelm |
Generic control flow reconstruction from assembly code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 46-55, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
control flow reconstruction, embedded processors, call graph, retargetable compilers, assembly code, postpass optimization |
15 | Olivier Beaumont, Vincent Boudet, Antoine Petitet, Fabrice Rastello, Yves Robert |
A Proposal for a Heterogeneous Cluster ScaLAPACK (Dense Linear Solvers). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(10), pp. 1052-1070, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
heterogeneous grid, different-speed processors, load-balancing, cluster computing, Heterogeneous network, data distribution, numerical linear algebra, data allocation, heterogeneous platforms, numerical libraries |
15 | David López 0001, Josep Llosa, Mateo Valero, Eduard Ayguadé |
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(10), pp. 1033-1051, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
numerical applications, performance/cost trade-off, instruction level parallelism, software pipelining, VLIW processors |
15 | Marco Ferretti |
Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing? ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 249-, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing |
15 | Vincent Boudet, Fabrice Rastello, Yves Robert |
PVM Implementation of Heterogeneous ScaLAPACK Dense Linear Solvers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PVM/MPI ![In: Recent Advances in Parallel Virtual Machine and Message Passing Interface, 6th European PVM/MPI Users' Group Meeting, Barcelona, Spain, September 26-29, 1999, Proceedings, pp. 333-340, 1999, Springer, 3-540-66549-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
different- speed processors, scheduling and mapping, Heterogeneous networks, distributed-memory, numerical libraries |
15 | João Carreira, Henrique Madeira, João Gabriel Silva |
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 24(2), pp. 125-136, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
real time, Fault injection, dependability evaluation, RISC processors |
15 | A. Lodeczi |
Model-integrated parallel application synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 1997 Workshop on Engineering of Computer-Based Systems (ECBS '97), March 24-28, 1997, Monterey, CA, USA, pp. 38-45, 1997, IEEE Computer Society, 0-8186-7889-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
model-integrated parallel application synthesis, Texas Instruments TMS320C40, Analog Devices ADSP21060, flexible topology, embedded parallel signal processing, hardware topology, model-integrated programming environment, Multigraph Architecture, high-level system models, network of processors, software engineering, software engineering, complexity, parallel computer architectures, I/O bandwidth |
15 | Jing-Chiou Liou, Michael A. Palis |
A Comparison of General Approaches to Multiprocessor Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 152-156, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
two phase method, task clustering, near optimal number of processors, task clustering algorithm, cluster merging, communication traffic minimizing, CTM, distributed memory parallel architectures, load balancing, multiprocessing systems, multiprocessor scheduling, task graphs, task graph scheduling |
15 | Chin-Wen Ho, Sun-Yuan Hsieh, Gen-Huey Chen |
An Efficient Parallel Strategy for Computing K-terminal Reliability and Finding Most Vital Edge in 2-trees and Partial 2-trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 603-607, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
efficient parallel strategy, K-terminal reliability computation, most vital edge finding, 2-trees, partial 2-trees, connected graph components, logarithmic time, reliability, processors, edges, computation time, vertices, CRCW PRAM |
15 | Michael J. Flynn |
What's ahead in computer design? ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 4-, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size |
15 | Zhaofang Wen |
Multiway Merging in Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(1), pp. 11-17, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
information retrieval, databases, parallel computation, sorting, merging, Analysis of algorithms, processors assignment |
15 | Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai, Yu-Hua Lee |
Some Image Processing Algorithms on a RAP with Wider Bus Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '96, The 10th International Parallel Processing Symposium, April 15-19, 1996, Honolulu, Hawaii, USA, pp. 708-715, 1996, IEEE Computer Society, 0-8186-7255-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
wider bus networks, reconfigurable array of processors, base-m number system, parallel algorithms, parallel algorithms, image processing, image segmentation, image segmentation, parallel architectures, multiprocessor interconnection networks, reconfigurable architectures, histogram, system buses, computation power, image processing algorithms, image labeling, constant time, RAP |
15 | Chung-Sei Rhee, Heok-Jung Kwon, Young-Tak Kwon, Byung-Whan Choi |
On the real time diagnosability of multiprocessor systems by comparison approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: Third International Workshop on Real-Time Computing Systems Application (RTCSA '96), October 30 - November 01, 1996, Seoul, Korea, pp. 154-161, 1996, IEEE Computer Society, 0-8186-7626-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
real time diagnosability, comparison approach, multiprocessing systems, multiprocessor systems, polynomial time algorithm, faulty processors |
15 | Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe |
Load Balancing in Superscalar Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic, pp. 651-, 1996, IEEE Computer Society, 0-8186-7487-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources |
15 | Yong-Kim Chong, Kai Hwang 0001 |
Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 6(10), pp. 1085-1099, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
latency hiding techniques, performance evaluation, Distributed shared memory, stochastic Petri nets, multithreaded processors, memory consistency models, context switching, scalable multiprocessors |
15 | Larry Carter, Jeanne Ferrante, Susan Flynn Hummel |
Hierarchical tiling for improved superscalar performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 239-245, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage |
15 | Orly Kremien |
Buying and selling computational power over the network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCN ![In: Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), September 20-23, 1995, Las Vegas, Nevada, USA, pp. 616, 1995, IEEE Computer Society, 0-8186-7180-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
computational power selling, computational power buying, supercomputer speeds, high data rate applications, high-bandwidth communications, extended adaptive partitioning algorithm, mutual interest, client selection, scalability, network, multiprocessing systems, processors, workstations, data-intensive applications, server selection |
15 | Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst |
Silicon VLSI processing architectures incorporating integrated optoelectronic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 17-27, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si |
15 | Ernst W. Mayr |
Scheduling interval orders in parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (2) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 20-28, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
interval order scheduling, interval representations, transitively oriented digraph, undirected chordal complement, identical parallel processors, minimal length schedule, scheduling distance computation subroutine, incremental version, empty slots, interval order precedence constraints, scheduling, parallel algorithms, parallel algorithm, computational complexity, concurrency control, directed graphs, partial orders, NP-complete problems, deadlines, execution time, minimisation, interval graphs, optimal schedule, release times, NC-algorithm, CREW-PRAM, task systems |
15 | Chien-Min Wang, Sheng-De Wang |
Efficient Processor Assignment Algorithms and Loop Transformations for Executing Nested Parallel Loops on Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 3(1), pp. 71-82, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
processor assignment algorithms, nested parallel loops, performance, parallel algorithms, parallel programming, multiprocessors, program compilers, loop transformations, parallel processors, parallel execution |
15 | Lee A. Hollaar |
Specialized Merge Processor Networks for Combined Sorted Lists. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Database Syst. ![In: ACM Trans. Database Syst. 3(3), pp. 272-284, 1978. The full citation details ...](Pics/full.jpeg) |
1978 |
DBLP DOI BibTeX RDF |
backend processors, binary tree networks, computer system architecture, full text retrieval systems, inverted file databases, nonnumeric processing, pipelined networks, sorted list merging |
14 | Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001 |
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 286, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design |
14 | Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero |
Thread to strand binding of parallel network applications in massive multi-threaded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2010, Bangalore, India, January 9-14, 2010, pp. 191-202, 2010, ACM, 978-1-60558-877-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ultrasparc t2, simultaneous multithreading, process scheduling, cmt |
14 | Sunpyo Hong, Hyesoon Kim |
An integrated GPU power and performance model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 280-289, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
GPU architecture, performance, energy, analytical model, CUDA, power estimation |
14 | Pangfeng Liu, May-Chen Kuo, Da-Wei Wang 0004 |
An Approximation Algorithm and Dynamic Programming for Reduction in Heterogeneous Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 53(3), pp. 425-453, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Heterogeneous workstation cluster, Reduction protocol, Slowest-node-first heuristic, Dynamic programming, Scheduling optimization, Branch-and-bound search |
14 | Valerie King, Jared Saia |
From Almost Everywhere to Everywhere: Byzantine Agreement with Õ(n3/2) Bits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 23rd International Symposium, DISC 2009, Elche, Spain, September 23-25, 2009. Proceedings, pp. 464-478, 2009, Springer, 978-3-642-04354-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Lars Bauer, Muhammad Shafique 0001, Jörg Henkel |
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 335-342, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation |
14 | Valerie King, Jared Saia |
Brief announcement: fast scalable Byzantine agreement in the full information model with a nonadaptive adversary. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PODC ![In: Proceedings of the 28th Annual ACM Symposium on Principles of Distributed Computing, PODC 2009, Calgary, Alberta, Canada, August 10-12, 2009, pp. 304-305, 2009, ACM, 978-1-60558-396-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
asychrony, communication complexity, gossiping, leader election, byzantine agreement, message complexity, synchrony |
14 | Brian Dougherty, Jules White, Jaiganesh Balasubramanian, Chris Thompson, Douglas C. Schmidt |
Deployment automation with BLITZ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE Companion ![In: 31st International Conference on Software Engineering, ICSE 2009, May 16-24, 2009, Vancouver, Canada, Companion Volume, pp. 271-274, 2009, IEEE, 978-1-4244-3494-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
14 | Jingnan Yao, Jiani Guo, Laxmi N. Bhuyan |
Ordered Round-Robin: An Efficient Sequence Preserving Packet Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1690-1703, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Yefim Dinitz, Shlomo Moran, Sergio Rajsbaum |
Bit complexity of breaking and achieving symmetry in chains and rings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 55(1), pp. 3:1-3:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
bit complexity, processor chain, processor ring, symmetric synchronous execution, Distributed computing, lower bounds, consensus, communication complexity, leader election, communication cost, message complexity, tight bound |
14 | Chadi Kari, Alexander Russell, Narasimha K. Shashidhar |
Randomized Work-Competitive Scheduling for Cooperative Computing on k-partite Task Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: Proceedings of The Seventh IEEE International Symposium on Networking Computing and Applications, NCA 2008, July 10-12, 2008, Cambridge, Massachusetts, USA, pp. 267-270, 2008, IEEE Computer Society, 978-0-7695-3192-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
partitionable networks, distributed computing, randomized algorithms, competitive analysis, On-line algorithms |
14 | Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus |
The Synchronization Power of Coalesced Memory Accesses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 22nd International Symposium, DISC 2008, Arcachon, France, September 22-24, 2008. Proceedings, pp. 320-334, 2008, Springer, 978-3-540-87778-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Anne Benoit, Veronika Rehn-Sonigo, Yves Robert |
Optimizing latency and reliability of pipeline workflow applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-10, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan |
Scaling Soft Processor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, pp. 195-205, 2008, IEEE Computer Society, 978-0-7695-3307-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Suriayati Chuprat, Sanjoy K. Baruah |
Scheduling Divisible Real-Time Loads on Clusters with Varying Processor Start Times. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: The Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2008, Kaohisung, Taiwan, 25-27 August 2008, Proceedings, pp. 15-24, 2008, IEEE Computer Society, 978-0-7695-3349-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Gaurav Singh 0002, René Weiskircher |
Collaborative Resource Constraint Scheduling with a Fractional Shared Resource. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IAT ![In: Proceedings of the 2008 IEEE/WIC/ACM International Conference on Intelligent Agent Technology, Sydney, NSW, Australia, December 9-12, 2008, pp. 359-365, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
14 | Hongfeng Yu 0001, Chaoli Wang 0001, Kwan-Liu Ma |
Massively parallel volume rendering using 2-3 swap image compositing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2008, November 15-21, 2008, Austin, Texas, USA, pp. 48, 2008, IEEE/ACM, 978-1-4244-2835-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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