Search results for "processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	William S. Song	High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays.	ASAP	2000	DBLP DOI BibTeX RDF
17	Andrew Stone, Elias S. Manolakos	Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis.	ASAP	2000	DBLP DOI BibTeX RDF	Optimal VHDL, DG2VHDL, Hierarchical CDFG, High Level Synthesis, Dependence Graph, Signal Flow Graph, Design Complexity
17	Nagaraj Ns, Frank Cano, Sudha Thiruvengadam, Deepak Kapoor	Performance and Reliability Verification of C6201/C6701 Digital Signal Processors.	ICCD	1999	DBLP DOI BibTeX RDF
17	Jeffry T. Russell, Margarida F. Jacome	Software power estimation and optimization for high performance, 32-bit embedded processors.	ICCD	1998	DBLP DOI BibTeX RDF
17	David Li, Andrew Pua, Pranjal Srivastava, Uming Ko	A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors.	ICCD	1997	DBLP DOI BibTeX RDF
17	Jude A. Rivers, Edward S. Tam, Edward S. Davidson	On Effective Data Supply For Multi-Issue Processors.	ICCD	1997	DBLP DOI BibTeX RDF
17	Jean-Paul Theis, Lothar Thiele	VLIW-Processors under Periodic Real Time Constraints.	ICCD	1996	DBLP DOI BibTeX RDF	Risc architecture, frontend compilers, embedded systems
17	Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes	Reducing State Loss For Effective Trace Sampling of Superscalar Processors.	ICCD	1996	DBLP DOI BibTeX RDF
17	Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen	Architectural Verification of Processors Using Symbolic Instruction Graphs.	ICCD	1994	DBLP DOI BibTeX RDF
17	S. Surya, Pradip Bose, Jacob A. Abraham	Architectural Performance Verification: PowerPCTM Processors.	ICCD	1994	DBLP DOI BibTeX RDF
17	W. H. Chou, Sun-Yuan Kung	Register transfer modeling and simulation for array processors.	ASAP	1994	DBLP DOI BibTeX RDF
17	Miodrag Potkonjak, Mani B. Srivastava	Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations.	ASAP	1994	DBLP DOI BibTeX RDF
17	Yusuke Mishina, Keiji Kojima	String Matching on IDP: A String Matching Algorithm for Vector Processors and Its Implementation.	ICCD	1993	DBLP DOI BibTeX RDF
17	Rodney Boleyn, James Debardelaben, Vivek Tiwari, Andrew Wolfe	A Split Data Cache for Superscalar Processors.	ICCD	1993	DBLP DOI BibTeX RDF
17	Chia-Jiu Wang, Frank Emnett	Area and Performance Comparison of Pipelined RISC Processors Implementing Different Precise Interrupt Methods.	ICCD	1993	DBLP DOI BibTeX RDF
17	Michel Auguin, Fernand Boéri, C. Carrière, G. Menez	Synthesis of dedicated SIMD processors.	ASAP	1993	DBLP DOI BibTeX RDF
17	Chie Dou	A highly-parallel match architecture for AI production systems using application-specific associative matching processors.	ASAP	1993	DBLP DOI BibTeX RDF
17	Zheng Zhou, Wayne P. Burleson	Formal descriptions, semantics and verification of VLSI array processors.	ASAP	1993	DBLP DOI BibTeX RDF
17	Alfred Strey	Implementation of large neural associative memories by massively parallel array processors.	ASAP	1993	DBLP DOI BibTeX RDF
17	Dong-wan Tcha, Bum-il Lee, Toung-duck Lee	Processors Selection and Traffic Splitting in a Parallel Processors System.	Acta Informatica	1992	DBLP DOI BibTeX RDF
17	George A. Sai-Halasz	Directions in Futrue High End Processors.	ICCD	1992	DBLP DOI BibTeX RDF
17	Amar Mukherjee	Determining longest common subsequences of two sequences on a linear array of processors.	ASAP	1992	DBLP DOI BibTeX RDF
17	Brion L. Keller, David A. Haynes	Design Automation of Test for the EX/9000TM Series Processors.	ICCD	1991	DBLP DOI BibTeX RDF
17	M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, K. Yano, M. Hiraki, S. Shukuri, T. Nishida	On-Chip Multiple Superscalar Processors with Secondary Cache Memories.	ICCD	1991	DBLP DOI BibTeX RDF
17	Jens Franzen	A design method for on-line reconfigurable array processors.	ASAP	1991	DBLP DOI BibTeX RDF
17	Glen G. Langdon Jr.	Book review: Solving Problems on Concurrent Processors, Vol II: Software for Concurrent Processors by I. Angus, G. Fox, J. Kim, and D. Walker (Prentice-Hall, 1990).	SIGARCH Comput. Archit. News	1990	DBLP DOI BibTeX RDF
17	David J. Lilja, Pen-Chung Yew	Comparing Parallelism Extraction Techniques: Superscalar Processors, Pipelined Processors, and Multiprocessors.	ICPP (1)	1990	DBLP BibTeX RDF
17	Jack S. N. Jean	Fault-tolerant array processors using N-and-half-track switches.	ASAP	1990	DBLP DOI BibTeX RDF
17	Zicheng Guo, Rami G. Melhem	Embedding pyramids in array processors with pipelined busses.	ASAP	1990	DBLP DOI BibTeX RDF
17	A. P. Marriott, Andrew W. G. Duller, Richard H. Storer, Andrew R. Thomson, Mike R. Pout	Towards the automated design of application specific array processors (ASAPs).	ASAP	1990	DBLP DOI BibTeX RDF
17	R. M. Lea	ASP modules: building-blocks for application-specific massively parallel processors.	ASAP	1990	DBLP DOI BibTeX RDF
17	Yi-Chieh Chang, Kang G. Shin	A module-sliced approach for high yield VLSI/WSI processors.	ICCD	1989	DBLP DOI BibTeX RDF
17	Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago	High performance I/O processors for real-time pulse handling.	ICCD	1989	DBLP DOI BibTeX RDF
17	Yervant Zorian, Najmi Jarwala	Designing fault-tolerant, testable, VLSI processors using the IEEE P1149.1 boundary-scan architecture.	ICCD	1989	DBLP DOI BibTeX RDF
17	Shannon Shen 0002, Surendar Magar, Raul Aguilar, Gerry Luikuo, Mike Fleming, K. Rishavy, K. Murphy, C. Furman	A high performance CMOS chipset for FFT processors.	ICCD	1988	DBLP DOI BibTeX RDF
17	H. V. Jagadish	Sorting on an array of processors.	ICCD	1988	DBLP DOI BibTeX RDF
17	Vincenzo Piuri, Renato Stefanelli	Use of redundant binary representation for fault-tolerant arithmetic array processors.	ICCD	1988	DBLP DOI BibTeX RDF
17	Fausto Distante, Vincenzo Piuri	APES: an integrated system for behavioral design, simulation and evaluation of array processors.	ICCD	1988	DBLP DOI BibTeX RDF
17	Glenn Hinton, Konrad Lai, Randy Steck	Microarchitecture of the 80960 high-integration processors.	ICCD	1988	DBLP DOI BibTeX RDF
17	Masood Namjoo	First 32-bit SPARC-based processors implemented in high-speed CMOS.	ICCD	1988	DBLP DOI BibTeX RDF
17	S. H. Hosseini	On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processors.	ICCD	1988	DBLP DOI BibTeX RDF
17	Chang-Biau Yang, Richard C. T. Lee	The mapping of 2-D array processors to 1-D array processors.	Parallel Comput.	1986	DBLP DOI BibTeX RDF
17	W. J. Van Gils	How to Cope with Faulty Processors in a Completely Connected Network of Communicating Processors.	Inf. Process. Lett.	1985	DBLP DOI BibTeX RDF
15	John Sartori, Rakesh Kumar 0002	Overscaling-friendly timing speculation architectures.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	stochastic processors, timing speculation, adaptability
15	Vahid Kazempour, Ali Kamali, Alexandra Fedorova	AASH: an asymmetry-aware scheduler for hypervisors.	VEE	2010	DBLP DOI BibTeX RDF	heterogeneous, scheduling algorithms, multicore processors, virtual machine monitor, hypervisor, asymmetric
15	Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik	On approximating the ideal random access machine by physical machines.	J. ACM	2009	DBLP DOI BibTeX RDF	Physical constraints on machines, pipelined hierarchical memory, speculative processors
15	Minwook Ahn, Yunheung Paek	Register coalescing techniques for heterogeneous register architecture with copy sifting.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	heterogeneous register architecture, compiler, Register allocation, embedded processors, register coalescing
15	Praveen Raghavan, Murali Jayapala, Andy Lambrechts, Javed Absar, Francky Catthoor	Playing the trade-off game: Architecture exploration using Coffeee.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	design, embedded systems, Energy, VLIW, processors, power estimation, loop transformations, architecture exploration, area, power-performance trade-off, compiler-architecture interaction
15	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
15	Jeffrey R. Diamond, Behnam Robatmili, Stephen W. Keckler, Robert A. van de Geijn, Kazushige Goto, Doug Burger	High performance dense linear algebra on a spatially distributed processor.	PPoPP	2008	DBLP DOI BibTeX RDF	gotoblas, grid processors, hybrid dataflow, matrix multiply, tile based architecture, instruction level parallelism, on-chip networks, dense linear algebra
15	Peter James Leadbitter, Dan Page, Nigel P. Smart	Nondeterministic Multithreading.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Side-channel analysis, multithreaded processors
15	Richard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham	Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems.	LCTES	2007	DBLP DOI BibTeX RDF	source-level transformations, compilers, design space exploration, ASIPs, instruction set extension, customizable processors
15	Minwook Ahn, Jooyeon Lee, Yunheung Paek	Optimistic coalescing for heterogeneous register architectures.	LCTES	2007	DBLP DOI BibTeX RDF	heterogeneous register architecture, register coalesing, compiler, register allocation, embedded processors
15	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra 0001, Xu Cheng 0001	A Retargetable Software Timing Analyzer Using Architecture Description Language.	ASP-DAC	2007	DBLP DOI BibTeX RDF	retargetable software timing analyzer, static WCET analysis, program path analysis, microarchitecture modeling, graph-based execution models, pipeline model, real-time systems, architecture description language, worst case execution time, embedded processors, branch prediction, schedulability analysis
15	Tomás Hrubý, Kees van Reeuwijk, Herbert Bos	Ruler: high-speed packet matching and rewriting on NPUs.	ANCS	2007	DBLP DOI BibTeX RDF	TDFA, regular expressions, network processors, deep packet inspection
15	Björn Franke, Michael F. P. O'Boyle	A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	conversion from sequential to parallel forms, modeling, evaluation, compilers, measurement, performance measures, interprocessor communications, arrays, real-time and embedded systems, restructuring, Parallel processors, simulation of multiple-processor systems, reverse engineering and reengineering, signal processing systems
15	Zhen Chen 0001, Chuang Lin 0002, Jia Ni, Dong-Hua Ruan, Bo Zheng, Yixin Jiang	AntiWorm NPU-based Parallel Bloom Filters for TCP/IP Content Processing in Giga-Ethernet LAN.	LCN	2005	DBLP DOI BibTeX RDF	TCP/IP Protocol suite, Parallel Bloom Filter, Stateful TCP inspection, Network Security, Network Processors, Worms, Deep Packet Inspection
15	Ada Gavrilovska, Karsten Schwan	Addressing data compatibility on programmable network platforms.	ANCS	2005	DBLP DOI BibTeX RDF	data morphing, network processors, streaming applications
15	Rashmi Bajaj, Dharma P. Agrawal	Improving Scheduling of Tasks in a Heterogeneous Environment.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	network of processors, directed acyclic graph, Communication cost, heterogeneous environment, optimal scheduling, computational cost, task duplication
15	Enrico Angelelli, Á. B. Nagy, Maria Grazia Speranza, Zsolt Tuza	The On-Line Multiprocessor Scheduling Problem with Known Sum of the Tasks.	J. Sched.	2004	DBLP DOI BibTeX RDF	competitive analysis, parallel processors, on-line scheduling
15	Marco Galluzzi, Ramón Beivide, Valentin Puente, José-Ángel Gregorio, Adrián Cristal, Mateo Valero	Evaluating kilo-instruction multiprocessors.	WMPI	2004	DBLP DOI BibTeX RDF	ROB, shared-memory multiprocessors, CC-NUMA, memory wall, instruction window, kilo-instruction processors
15	Pepijn J. de Langen, Ben H. H. Juurlink	Reducing traffic generated by conflict misses in caches.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	caches, embedded processors, power reduction, conflict misses
15	Daniel Kästner, Stephan Wilhelm	Generic control flow reconstruction from assembly code.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	control flow reconstruction, embedded processors, call graph, retargetable compilers, assembly code, postpass optimization
15	Olivier Beaumont, Vincent Boudet, Antoine Petitet, Fabrice Rastello, Yves Robert	A Proposal for a Heterogeneous Cluster ScaLAPACK (Dense Linear Solvers).	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	heterogeneous grid, different-speed processors, load-balancing, cluster computing, Heterogeneous network, data distribution, numerical linear algebra, data allocation, heterogeneous platforms, numerical libraries
15	David López 0001, Josep Llosa, Mateo Valero, Eduard Ayguadé	Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	numerical applications, performance/cost trade-off, instruction level parallelism, software pipelining, VLIW processors
15	Marco Ferretti	Multi-Media Extensions in Super-Pipelined Micro-Architectures. A New Case for SIMD Processing?	CAMP	2000	DBLP DOI BibTeX RDF	super-pipelined microarchitectures, general purpose microprocessors, Von-Neumann paradigm, image processing, parallel architectures, associated memory, instruction set architectures, massively parallel processors, multimedia extensions, SIMD processing
15	Vincent Boudet, Fabrice Rastello, Yves Robert	PVM Implementation of Heterogeneous ScaLAPACK Dense Linear Solvers.	PVM/MPI	1999	DBLP DOI BibTeX RDF	different- speed processors, scheduling and mapping, Heterogeneous networks, distributed-memory, numerical libraries
15	João Carreira, Henrique Madeira, João Gabriel Silva	Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers.	IEEE Trans. Software Eng.	1998	DBLP DOI BibTeX RDF	real time, Fault injection, dependability evaluation, RISC processors
15	A. Lodeczi	Model-integrated parallel application synthesis.	ECBS	1997	DBLP DOI BibTeX RDF	model-integrated parallel application synthesis, Texas Instruments TMS320C40, Analog Devices ADSP21060, flexible topology, embedded parallel signal processing, hardware topology, model-integrated programming environment, Multigraph Architecture, high-level system models, network of processors, software engineering, software engineering, complexity, parallel computer architectures, I/O bandwidth
15	Jing-Chiou Liou, Michael A. Palis	A Comparison of General Approaches to Multiprocessor Scheduling.	IPPS	1997	DBLP DOI BibTeX RDF	two phase method, task clustering, near optimal number of processors, task clustering algorithm, cluster merging, communication traffic minimizing, CTM, distributed memory parallel architectures, load balancing, multiprocessing systems, multiprocessor scheduling, task graphs, task graph scheduling
15	Chin-Wen Ho, Sun-Yuan Hsieh, Gen-Huey Chen	An Efficient Parallel Strategy for Computing K-terminal Reliability and Finding Most Vital Edge in 2-trees and Partial 2-trees.	IPPS	1997	DBLP DOI BibTeX RDF	efficient parallel strategy, K-terminal reliability computation, most vital edge finding, 2-trees, partial 2-trees, connected graph components, logarithmic time, reliability, processors, edges, computation time, vertices, CRCW PRAM
15	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
15	Zhaofang Wen	Multiway Merging in Parallel.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	information retrieval, databases, parallel computation, sorting, merging, Analysis of algorithms, processors assignment
15	Shung-Shing Lee, Shi-Jinn Horng, Horng-Ren Tsai, Yu-Hua Lee	Some Image Processing Algorithms on a RAP with Wider Bus Networks.	IPPS	1996	DBLP DOI BibTeX RDF	wider bus networks, reconfigurable array of processors, base-m number system, parallel algorithms, parallel algorithms, image processing, image segmentation, image segmentation, parallel architectures, multiprocessor interconnection networks, reconfigurable architectures, histogram, system buses, computation power, image processing algorithms, image labeling, constant time, RAP
15	Chung-Sei Rhee, Heok-Jung Kwon, Young-Tak Kwon, Byung-Whan Choi	On the real time diagnosability of multiprocessor systems by comparison approach.	RTCSA	1996	DBLP DOI BibTeX RDF	real time diagnosability, comparison approach, multiprocessing systems, multiprocessor systems, polynomial time algorithm, faulty processors
15	Eliseu M. Chaves Filho, Edil S. T. Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
15	Yong-Kim Chong, Kai Hwang 0001	Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	latency hiding techniques, performance evaluation, Distributed shared memory, stochastic Petri nets, multithreaded processors, memory consistency models, context switching, scalable multiprocessors
15	Larry Carter, Jeanne Ferrante, Susan Flynn Hummel	Hierarchical tiling for improved superscalar performance.	IPPS	1995	DBLP DOI BibTeX RDF	hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage
15	Orly Kremien	Buying and selling computational power over the network.	ICCCN	1995	DBLP DOI BibTeX RDF	computational power selling, computational power buying, supercomputer speeds, high data rate applications, high-bandwidth communications, extended adaptive partitioning algorithm, mutual interest, client selection, scalability, network, multiprocessing systems, processors, workstations, data-intensive applications, server selection
15	Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst	Silicon VLSI processing architectures incorporating integrated optoelectronic devices.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si
15	Ernst W. Mayr	Scheduling interval orders in parallel.	HICSS (2)	1995	DBLP DOI BibTeX RDF	interval order scheduling, interval representations, transitively oriented digraph, undirected chordal complement, identical parallel processors, minimal length schedule, scheduling distance computation subroutine, incremental version, empty slots, interval order precedence constraints, scheduling, parallel algorithms, parallel algorithm, computational complexity, concurrency control, directed graphs, partial orders, NP-complete problems, deadlines, execution time, minimisation, interval graphs, optimal schedule, release times, NC-algorithm, CREW-PRAM, task systems
15	Chien-Min Wang, Sheng-De Wang	Efficient Processor Assignment Algorithms and Loop Transformations for Executing Nested Parallel Loops on Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	processor assignment algorithms, nested parallel loops, performance, parallel algorithms, parallel programming, multiprocessors, program compilers, loop transformations, parallel processors, parallel execution
15	Lee A. Hollaar	Specialized Merge Processor Networks for Combined Sorted Lists.	ACM Trans. Database Syst.	1978	DBLP DOI BibTeX RDF	backend processors, binary tree networks, computer system architecture, full text retrieval systems, inverted file databases, nonnumeric processing, pipelined networks, sorted list merging
14	Diana Göhringer, Michael Hübner 0001, Michael Benz, Jürgen Becker 0001	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
14	Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Thread to strand binding of parallel network applications in massive multi-threaded systems.	PPoPP	2010	DBLP DOI BibTeX RDF	ultrasparc t2, simultaneous multithreading, process scheduling, cmt
14	Sunpyo Hong, Hyesoon Kim	An integrated GPU power and performance model.	ISCA	2010	DBLP DOI BibTeX RDF	GPU architecture, performance, energy, analytical model, CUDA, power estimation
14	Pangfeng Liu, May-Chen Kuo, Da-Wei Wang 0004	An Approximation Algorithm and Dynamic Programming for Reduction in Heterogeneous Environments.	Algorithmica	2009	DBLP DOI BibTeX RDF	Heterogeneous workstation cluster, Reduction protocol, Slowest-node-first heuristic, Dynamic programming, Scheduling optimization, Branch-and-bound search
14	Valerie King, Jared Saia	From Almost Everywhere to Everywhere: Byzantine Agreement with Õ(n3/2) Bits.	DISC	2009	DBLP DOI BibTeX RDF
14	Lars Bauer, Muhammad Shafique 0001, Jörg Henkel	MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	extensible embedded processor, reconfigurable computing, kernel, accelerator, replacement, run-time adaptation
14	Valerie King, Jared Saia	Brief announcement: fast scalable Byzantine agreement in the full information model with a nonadaptive adversary.	PODC	2009	DBLP DOI BibTeX RDF	asychrony, communication complexity, gossiping, leader election, byzantine agreement, message complexity, synchrony
14	Brian Dougherty, Jules White, Jaiganesh Balasubramanian, Chris Thompson, Douglas C. Schmidt	Deployment automation with BLITZ.	ICSE Companion	2009	DBLP DOI BibTeX RDF
14	Jingnan Yao, Jiani Guo, Laxmi N. Bhuyan	Ordered Round-Robin: An Efficient Sequence Preserving Packet Scheduler.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
14	Yefim Dinitz, Shlomo Moran, Sergio Rajsbaum	Bit complexity of breaking and achieving symmetry in chains and rings.	J. ACM	2008	DBLP DOI BibTeX RDF	bit complexity, processor chain, processor ring, symmetric synchronous execution, Distributed computing, lower bounds, consensus, communication complexity, leader election, communication cost, message complexity, tight bound
14	Chadi Kari, Alexander Russell, Narasimha K. Shashidhar	Randomized Work-Competitive Scheduling for Cooperative Computing on k-partite Task Graphs.	NCA	2008	DBLP DOI BibTeX RDF	partitionable networks, distributed computing, randomized algorithms, competitive analysis, On-line algorithms
14	Phuong Hoai Ha, Philippas Tsigas, Otto J. Anshus	The Synchronization Power of Coalesced Memory Accesses.	DISC	2008	DBLP DOI BibTeX RDF
14	Anne Benoit, Veronika Rehn-Sonigo, Yves Robert	Optimizing latency and reliability of pipeline workflow applications.	IPDPS	2008	DBLP DOI BibTeX RDF
14	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Scaling Soft Processor Systems.	FCCM	2008	DBLP DOI BibTeX RDF
14	Suriayati Chuprat, Sanjoy K. Baruah	Scheduling Divisible Real-Time Loads on Clusters with Varying Processor Start Times.	RTCSA	2008	DBLP DOI BibTeX RDF
14	Gaurav Singh 0002, René Weiskircher	Collaborative Resource Constraint Scheduling with a Fractional Shared Resource.	IAT	2008	DBLP DOI BibTeX RDF
14	Hongfeng Yu 0001, Chaoli Wang 0001, Kwan-Liu Ma	Massively parallel volume rendering using 2-3 swap image compositing.	SC	2008	DBLP DOI BibTeX RDF