Search results for "time-to-market"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Paul K. Rodman	Forest vs. trees: where's the slack?	DAC	2004	DBLP DOI BibTeX RDF
4	Mark Hopkins	Nomadic platform approach for wireless mobile multimedia.	DAC	2004	DBLP DOI BibTeX RDF
4	Mahmut T. Kandemir	LODS: locality-oriented dynamic scheduling for on-chip multiprocessors.	DAC	2004	DBLP DOI BibTeX RDF	embedded system, parallelization, data locality, loop scheduling
4	Philip Brisk, Adam Kaplan, Majid Sarrafzadeh	Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.	DAC	2004	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP)
4	Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete	Fine-grain design space exploration for a cartographic SoC multiprocessor.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF	SoC Multiprocessors, performance evaluation, embedded systems, trace-driven simulation, multiprocessor architecture
4	Nasib Singh Gill, P. S. Grover	Component-based measurement: few useful guidelines.	ACM SIGSOFT Softw. Eng. Notes	2003	DBLP DOI BibTeX RDF
4	Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj	Early probabilistic noise estimation for capacitively coupled interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
4	Ross Buhrdorf, Dale Churchett, Charles W. Krueger	Salion's Experience with a Reactive Software Product Line Approach.	PFE	2003	DBLP DOI BibTeX RDF
4	Jason Xabier Mansell, David Sellier	Decision Model and Flexible Component Definition Based on XML Technology.	PFE	2003	DBLP DOI BibTeX RDF
4	Claudio Riva, Christian Del Rosso	Experiences with Software Product Family Evolution.	IWPSE	2003	DBLP DOI BibTeX RDF
4	Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni	From Specification to Hardware Device: A Synthesis Algorithm.	ICFEM	2003	DBLP DOI BibTeX RDF	Rapid System Prototyping, Synthesis, Hardware Design
4	Orest Pilskalns, Anneliese Amschler Andrews, Sudipto Ghosh, Robert B. France	Rigorous Testing by Merging Structural and Behavioral UML Representations.	UML	2003	DBLP DOI BibTeX RDF
4	Jan Jürjens	Developing Safety-Critical Systems with UML.	UML	2003	DBLP DOI BibTeX RDF
4	Jörn Guy Süß, Andreas Leicher, Herbert Weber, Ralf-Detlef Kutsche	Model-Centric Engineering with the Evolution and Validation Environment.	UML	2003	DBLP DOI BibTeX RDF
4	Alex K. Jones, Prithviraj Banerjee	An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
4	Jean-Pierre Talpin, Paul Le Guernic, Sandeep K. Shukla, Rajesh K. Gupta 0001, Frederic Doucet	Polychrony for Refinement-Based Design.	DATE	2003	DBLP DOI BibTeX RDF
4	Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi	Modeling and Integration of Peripheral Devices in Embedded Systems.	DATE	2003	DBLP DOI BibTeX RDF
4	Alexandre Alvaro, Daniel Lucrédio, Vinicius Cardoso Garcia, Antônio Francisco do Prado, Luís Carlos Trevelin, Eduardo Santana de Almeida	Orion-RE: A Component-Based Software Reengineering Environment .	WCRE	2003	DBLP DOI BibTeX RDF
4	Jörn Guy Süß, Andreas Leicher, Fadi Chabarek	Software Model Engineering and Reuse with the Evolution and Validation Environment.	FIDJI	2003	DBLP DOI BibTeX RDF
4	Manu Prego	Reuse Based Software Factory.	ESERNET	2003	DBLP DOI BibTeX RDF
4	Mário P. Véstias, Horácio C. Neto	DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures.	SBCCI	2003	DBLP DOI BibTeX RDF
4	Visvanathan Subramanian, Joseph G. Tront, Charles W. Bostian, Scott F. Midkiff	Design and Implementation of a Configurable Platform for Embedded Communication Systems.	IPDPS	2003	DBLP DOI BibTeX RDF
4	Vicente Luque Centeno, Peter T. Breuer, Luis Sánchez Fernández 0001, Carlos Delgado Kloos, Juan Antonio Herráiz Pérez	MSC-based Language for Specifying Automated Web Clients.	ISCC	2003	DBLP DOI BibTeX RDF
4	Bozena Kaminska, Karim Arabi	Mixed Signal DFT: A Concise Overview.	ICCAD	2003	DBLP DOI BibTeX RDF
4	David Goodwin, Darin Petkov	Automatic generation of application specific processors.	CASES	2003	DBLP DOI BibTeX RDF	automatic instruction-set generation, ASIPs, configurable processors, extensible processors
4	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
4	Ryan J. Fong, Scott J. Harper, Peter M. Athanas	A Versatile Framework for FPGA Field Updates: An Application of Partial Self-Reconfiguation.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
4	Patrick Tessier, Sébastien Gérard, Chokri Mraidha, Jean-Marc Geib	A Component-Based Methodology for Embedded System Prototyping.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
4	Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou	Parameterized and low power DSP core for embedded systems.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
4	Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima	Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.	HICSS	2003	DBLP DOI BibTeX RDF
4	Noh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi	Regressive Testing for System-on-Chip with Unknown-Good-Yield.	DFT	2003	DBLP DOI BibTeX RDF
4	Francisco DaSilva, Yervant Zorian, Lee Whetsel, Karim Arabi, Rohit Kapur	Overview of the IEEE P1500 Standard.	ITC	2003	DBLP DOI BibTeX RDF
4	Amarjeet Singh 0001, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar	SoC Synthesis with Automatic Hardware Software Interface Generation.	VLSI Design	2003	DBLP DOI BibTeX RDF
4	Armando Armaroli, Marcello Coppola, Mario Diaz-Nava, Luca Fanucci	High Level Modeling and Simulation of a VDSL Modem in SystemC 2.0 - IPsim.	IWSOC	2003	DBLP DOI BibTeX RDF
4	Andreas Kirstädter, Axel Hof, Walter Meyer, Erwin Wolf	Implementation of Resilient Packet Ring Nodes Using Network Processors.	LCN	2003	DBLP DOI BibTeX RDF	Simulation, Quality of Service, Network processors, High-speed LAN
4	Grant Martin, Frank Schirrmeister	A Design Chain for Embedded Systems.	Computer	2002	DBLP DOI BibTeX RDF
4	Apostolos A. Kountouris, Christophe Wolinski	Efficient scheduling of conditional behaviors for high-level synthesis.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	conditional behavior, scheduling, high level synthesis (HLS), Design automation
4	Donald J. Reifer	How Good are Agile Methods?	IEEE Softw.	2002	DBLP DOI BibTeX RDF
4	Ian F. Alexander, Friedemann Kiedaisch	Towards Recyclable System Requirements.	ECBS	2002	DBLP DOI BibTeX RDF	Reuse, Requirements, Use Cases, Recycling
4	Donald J. Reifer	How to Get the Most out of Extreme Programming/Agile Methods.	XP/Agile Universe	2002	DBLP DOI BibTeX RDF
4	Christopher W. Milner, Jack W. Davidson	Quick piping: a fast, high-level model for describing processor pipelines.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	embedded systems, pipelines, modeling of computer architecture
4	Daniel Ménard, Olivier Sentieys	Automatic Evaluation of the Accuracy of Fixed-Point Algorithms.	DATE	2002	DBLP DOI BibTeX RDF
4	Julia Ahlers, Henrik Weimer	Challenges in Interactive Visualization for Knowledge Management.	IV	2002	DBLP DOI BibTeX RDF
4	Tuomas Valtonen, Jouni Isoaho, Hannu Tenhunen	The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance.	FPL	2002	DBLP DOI BibTeX RDF
4	Fayez Chayab, Lev Kirischian, Lucas Szajek	Architecture-to-Task Optimization System (ATOS) for Parallel Multi-Mode Data-Flow Architectures on a Base of a Partially Reconfigurable Computing Platform.	PARELEC	2002	DBLP DOI BibTeX RDF	data-flow applications, optimization, FPGA, Parallel architecture, DFG, partial reconfiguration, automated synthesis
4	Ulrike Becker-Kornstaedt, Daniela Boggio, Jürgen Münch, Alexis Ocampo, Gino Palladino	Empirically Driven Design of Software Development Processes for Wireless Internet Services.	PROFES	2002	DBLP DOI BibTeX RDF
4	Teade Punter, Adam Trendowicz, Peter Kaiser	Evaluating Evolutionary Software Systems.	PROFES	2002	DBLP DOI BibTeX RDF
4	Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda	Early probabilistic noise estimation for capacitively coupled interconnects.	SLIP	2002	DBLP DOI BibTeX RDF	early noise analysis, congestion, global routing
4	Krzysztof Czarnecki 0001	Generative Programming: Methods, Techniques, and Applications.	ICSR	2002	DBLP DOI BibTeX RDF
4	Fritz Stallinger, Alec Dorling, Terence P. Rout, Brian Henderson-Sellers, Bruno Lefever	Software Process Improvement for Component-Based Software Engineering: An Introduction to the OOSPICE Project.	EUROMICRO	2002	DBLP DOI BibTeX RDF	software process improvement, component-based software engineering, object-oriented development, software process assessment
4	Kurt Keutzer, Sharad Malik, A. Richard Newton	From ASIC to ASIP: The Next Design Discontinuity.	ICCD	2002	DBLP DOI BibTeX RDF	Programmable platforms, Design methodology, Application Specific Integrated Circuits, ASIC, Application Specific Instruction Set Processors, ASIP
4	Cesare Alippi, Andrea Galbusera, Marco Stellini	An application level synthesis methodology for embedded systems.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
4	Edith Kussener, Hervé Barthélemy, Alexandre Malherbe, Andreas Kaiser	Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
4	Petros Oikonomakos, Mark Zwolinski	Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment.	IOLTW	2002	DBLP DOI BibTeX RDF
4	Sébastien Pillement, Daniel Chillet, Olivier Sentieys	Behavioral IP Specification and Integration Framework for High-Level Design Reuse.	ISQED	2002	DBLP DOI BibTeX RDF
4	Terry Blanchard, Rick Ferreri, Jim Wilmore	The OpenAccess Coalition - The Drive to an Open Industry Standard Information Model, API, and Reference Implementation for IC Design Data (invited).	ISQED	2002	DBLP DOI BibTeX RDF
4	Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj	Pre-route Noise Estimation in Deep Submicron Integrated Circuits.	ISQED	2002	DBLP DOI BibTeX RDF	Crosstalk noise estimation, pre-route, congestion
4	Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger	Silicon Symptoms to Solutions: Applying Design for Debug Techniques.	ITC	2002	DBLP DOI BibTeX RDF
4	Yunjian Jiang, Robert K. Brayton	Software synthesis from synchronous specifications using logic simulation techniques.	DAC	2002	DBLP DOI BibTeX RDF
4	Alexander Chatzigeorgiou, George Stephanides	Evaluating Performance and Power of Object-Oriented Vs. Procedural Programming in Embedded Processors.	Ada-Europe	2002	DBLP DOI BibTeX RDF
4	Stanislaw Deniziak, Krzysztof Sapiecha	Developing a High-Level Fault Simulation Standard.	Computer	2001	DBLP DOI BibTeX RDF
4	Martin L. Griss, Gilda Pour	Accelerating Development with Agent Components.	Computer	2001	DBLP DOI BibTeX RDF
4	Peter Knauber, Jesús Bermejo Muñoz, Günter Böckle, Julio César Sampaio do Prado Leite, Frank van der Linden 0001, Linda M. Northrop, Michael E. Stark, David M. Weiss 0001	Quantifying Product Line Benefits.	PFE	2001	DBLP DOI BibTeX RDF
4	Steffen Thiel	On the Definition of a Framework for an Architecting Process Supporting Product Family Development.	PFE	2001	DBLP DOI BibTeX RDF
4	Juha Savolainen, Juha Kuusela	Consistency Management of Product Line Requirements.	RE	2001	DBLP DOI BibTeX RDF
4	Jim Harkin, T. Martin McGinnity, Liam P. Maguire	Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach.	FPL	2001	DBLP DOI BibTeX RDF
4	Jacky Estublier	Objects Control for Software Configuration Management.	CAiSE	2001	DBLP DOI BibTeX RDF	architecture, distribution, Version control, concurrent engineering, Software configuration management
4	Kenneth S. Norton	Applying Cross-Functional Evolutionary Methodologies to Web Development.	Web Engineering	2001	DBLP DOI BibTeX RDF
4	Dimitris Lioupis, Apostolos Papagiannis, Dionysia Psihogiou	A systematic approach to software peripherals for embedded systems.	CODES	2001	DBLP DOI BibTeX RDF	software peripherals, reconfigurable architectures, embedded processors
4	Johan Cockx	Whole program compilation for embedded software: the ADSL experiment.	CODES	2001	DBLP DOI BibTeX RDF	interprocedural optimization, whole program compilation, C++, embedded software
4	José Pineda de Gyvez	Yield modeling and BEOL fundamentals.	SLIP	2001	DBLP DOI BibTeX RDF
4	Dietmar Loy, Atsushi Murase, Andreas Doederlein	System Level Prototyping for Embedded Networking Applications.	IEEE International Workshop on Rapid System Prototyping	2001	DBLP DOI BibTeX RDF
4	Tae-Jin Kwon, Sang-Hoon Lee, Tae-Seon Kim, Hoe-Jin Lee, Young-Kwan Park, Taek-Soo Kim, Seok-Jin Kim, Jeong-Taek Kong	Performance Improvement for High Speed Devices Using E-tests and the SPICE Model.	ISQED	2001	DBLP DOI BibTeX RDF
4	Frank Huebner, Kathleen S. Meier-Hellstern, Paul Reeser	Performance Testing for IP Services and Systems.	Performance Engineering	2001	DBLP DOI BibTeX RDF
4	Magdy S. Abadir, Juhong Zhu, Li-C. Wang	Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor.	VTS	2001	DBLP DOI BibTeX RDF
4	Ioana Singureanu	Clinical Trial Automation: New, Revolutionary Therapies and Fewer Side-Effects using Mobile Internet Technologies.	WETICE	2001	DBLP DOI BibTeX RDF	Pharmaceutical, Food and Drug Administration, Internet, WAP, Clinical Trial, Therapy
4	Ali Arsanjani	Grammar-Oriented Object Design: Creating Adaptive Collaborations and Dynamic Configurations with Self-Describing Components and Services.	TOOLS (39)	2001	DBLP DOI BibTeX RDF	grammar-oriented object design, self-descriptive systems, components, dynamic reconfiguration, meta-data, adaptive object models, manners
4	Krzysztof Czarnecki 0001	Generative Programming and Software System Families.	SAIG	2001	DBLP DOI BibTeX RDF
4	Charles J. Poole, Tim Murphy, Jan Willem Huisman, Allen Higgins	Extreme Maintenance.	ICSM	2001	DBLP DOI BibTeX RDF	Software engineering, Software maintenance, Programming, Software
4	Daniel Häggander, Lars Lundberg, Jonas Matton	Quality Attribute Conflicts - Experiences from a Large Telecommunication Application.	ICECCS	2001	DBLP DOI BibTeX RDF
4	Kurt Keutzer, A. Richard Newton, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli	System-level design: orthogonalization of concerns andplatform-based design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
4	S. Ramanathan, S. K. Nandy 0001, V. Visvanathan	Reconfigurable Filter Coprocessor Architecture for DSP Applications.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures
4	Joerg Abke, Erich Barke	CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
4	André Brinkmann, Dominik Langen, Ulrich Rückert 0001	A Rapid Prototyping Environment for Microprocessor Based System-on-Chips and Its Application to the Development of a Network Processor.	FPL	2000	DBLP DOI BibTeX RDF
4	Li Gong	Developing Security Systems in the Real World.	ECOOP	2000	DBLP DOI BibTeX RDF
4	Stan Y. Liao	Towards a new standard for system-level design.	CODES	2000	DBLP DOI BibTeX RDF
4	Maya B. Gokhale, Janice M. Stone, Jeffrey M. Arnold, Mirek Kalinowski	Stream-Oriented FPGA Computing in the Streams-C High Level Language.	FCCM	2000	DBLP DOI BibTeX RDF	FPGA design tools, FPGA, high-level synthesis, configurable computing, hardware-software co-design, silicon compiler
4	Gaëtan Vanet, Motohiro Suzuki, Tôru Egashira, Yoshiaki Kiriha	Platform Architecture for Internet Service Delivery and Management.	DSOM	2000	DBLP DOI BibTeX RDF	Basic Service Component, Composite Internet Service, TINA Business Model, Building Block
4	Robert N. Blair, Jacques Benkoski	How Do You Select A High Quality EDA Tool Flow?.	ISQED	2000	DBLP DOI BibTeX RDF
4	Alberto L. Sangiovanni-Vincentelli	Platform-Based Design: A Path to Efficient Design Re-Use.	ISQED	2000	DBLP DOI BibTeX RDF
4	Thomas W. Williams, Rohit Kapur	Design for Testability in Nanometer Technologies; Searching for Quality.	ISQED	2000	DBLP DOI BibTeX RDF
4	Cesare Alippi, Stefano Ferrari, Vincenzo Piuri	A Methodology for Example-Based Specification and Design.	IJCNN (3)	2000	DBLP DOI BibTeX RDF
4	Brian Dipert, Danesh Tavana, Barry K. Britton, Bill Harris, Bob Boderson, Chris Rowen	Future systems-on-chip: software of hardware design? (panel session).	DAC	2000	DBLP DOI BibTeX RDF
4	N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang	When bad things happen to good chips (panel session).	DAC	2000	DBLP DOI BibTeX RDF
4	Jing Dong	Model checking the composition of hypermedia design components.	CASCON	2000	DBLP BibTeX RDF
4	Indradeep Ghosh, Niraj K. Jha, Sujit Dey	A low overhead design for testability and test generation technique for core-based systems-on-a-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
4	Nur Engin, Hans G. Kerkhoff, Ronald J. W. T. Tangelder, Han Speek	Integrated Design and Test of Mixed-Signal Circuits.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	design and test integration, test plan generation, specification-based testing, mixed-signal test
4	Chris Feige, Jan Ten Pierick, Clemens Wouters, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	bus-transfer, core reuse, test protocol, TIC, TTM, vector transfer, design-for-testability, ATPG, scan-test, AMBA
4	Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee	Synthesis of Embedded Software from Synchronous Dataflow Specifications.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
4	Bertram Weber	Automating PBX System Testing.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF