Search results for "FSM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Ying Huang, Santhosh Kumaran, Jen-Yao Chung	A Service Management Framework for Service-Oriented Enterprises.	CEC	2004	DBLP DOI BibTeX RDF
9	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
9	Victor V. Kuliamin, Alexander K. Petrenko, Nick V. Pakoulin, Alexander S. Kossatchev, Igor B. Bourdonov	Integration of Functional and Timed Testing of Real-Time and Concurrent Systems.	Ershov Memorial Conference	2003	DBLP DOI BibTeX RDF
9	Jianping Wu, Zhongjie Li, Xia Yin	Towards Modeling and Testing of IP Routing Protocols.	TestCom	2003	DBLP DOI BibTeX RDF
9	MingHung Lee, TingTing Hwang, Shi-Yu Huang	Decomposition of Extended Finite State Machine for Low Power Design.	DATE	2003	DBLP DOI BibTeX RDF
9	Jianqiang Jia, Weidong Chen 0001, Yugeng Xi	A Rule-Driven Autonomous Robotic System Operating in a Time-Varying Environment.	RoboCup	2003	DBLP DOI BibTeX RDF
9	Tatsuo Yotsukura, Shigeo Morishima, Satoshi Nakamura 0001	Model-based talking face synthesis for anthropomorphic spoken dialog agent system.	ACM Multimedia	2003	DBLP DOI BibTeX RDF	anthropomorphic dialog agent, face image synthesis, facial animation, lip synchronization
9	Piotr Dziurzanski	Modelling of Complex Systems Given as a Mealy Machine with Linear Decision Diagrams.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
9	Sobeeh Almukhaizim, Thomas Verdel, Yiorgos Makris	Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case.	ICCD	2003	DBLP DOI BibTeX RDF
9	Ravishankar K. Iyer, Shuo Chen 0001, Jun Xu 0003, Zbigniew Kalbarczyk	Security Vulnerabilities - From Data Analysis to Protection Mechanisms.	WORDS Fall	2003	DBLP DOI BibTeX RDF
9	Amit K. Chopra, Munindar P. Singh	Nonmonotonic Commitment Machines.	Workshop on Agent Communication Languages	2003	DBLP DOI BibTeX RDF
9	K. Satya Sai Prakash, S. V. Raghavan	User Relevancy Improvisation Protocol.	IWDC	2003	DBLP DOI BibTeX RDF
9	Emil Dumitrescu, Dominique Borrione	Symbolic Simulation as a Simplifying Strategy for SoC Verification.	IWSOC	2003	DBLP DOI BibTeX RDF
9	Jessica Chen, Suganthan Subramaniam	Specification-based Testing for Gui-based Applications.	Softw. Qual. J.	2002	DBLP DOI BibTeX RDF	java AWT and swing, finite state machines, specification-based testing, capture/replay
9	Fabrizio Ferrandi, Michele Rendine, Donatella Sciuto	Functional Verification for SystemC Descriptions Using Constraint Solving.	DATE	2002	DBLP DOI BibTeX RDF
9	Prabhat Mishra 0001, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama	Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units.	DATE	2002	DBLP DOI BibTeX RDF
9	Paul Amblard, Fabienne Lagnier, Michel Lévy	Using Formal Tools to Study Complex Circuits Behaviour.	DSD	2002	DBLP DOI BibTeX RDF
9	Xiaoming Chen, Geok-Soon Hong	A Simulation Study of the Predictive p-Persistent CSMA Protocol.	Annual Simulation Symposium	2002	DBLP DOI BibTeX RDF
9	Grégory Lestiennes, Marie-Claude Gaudel	Testing Processes from Formal Specifications with Inputs, Outputs and Data Types.	ISSRE	2002	DBLP DOI BibTeX RDF
9	Wilson Rosa de Oliveira, Marcílio Carlos Pereira de Souto, Teresa Bernarda Ludermir	Turing Machines with Finite Memory.	SBRN	2002	DBLP DOI BibTeX RDF
9	Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai	A bipartition-codec architecture to reduce power in pipelinedcircuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
9	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
9	Rajeev Alur, Mihalis Yannakakis	Model checking of hierarchical state machines.	ACM Trans. Program. Lang. Syst.	2001	DBLP DOI BibTeX RDF	model checking, temporal logic, statecharts, Hierarchical state machines
9	Igor B. Bourdonov, Alexey V. Demakov, Andrew A. Jarov, Alexander S. Kossatchev, Victor V. Kuliamin, Alexander K. Petrenko, Sergey V. Zelenov	Java Specification Extension for Automated Test Development.	Ershov Memorial Conference	2001	DBLP DOI BibTeX RDF
9	Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai	An entropy-based algorithm to reduce area overhead for bipartition-codec architecture.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
9	Cristiana Bolchini, R. Montandon, Fabio Salice, Donatella Sciuto	Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
9	Hideo Fujiwara	A New Class of Sequential Circuits with Combinational Test Generation Complexity.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	complexity, test generation, design for testability, sequential circuits, reducibility, partial scan, Balanced structure
9	Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer	AQUILA: An Equivalence Checking System for Large Sequential Designs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	state exploration, formal verification, Design verification, equivalence checking
9	Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara	A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	non-scan design for testability, complete fault efficiency, controllers, at-speed test
9	William M. Spears, Diana F. Gordon	Evolving Finite-State Machine Strategies for Protecting Resources.	ISMIS	2000	DBLP DOI BibTeX RDF
9	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero	Evolving Cellular Automata for Self-Testing Hardware.	ICES	2000	DBLP DOI BibTeX RDF
9	Wander O. Cesário, Zoltan Sugar, Imed Moussa, Ahmed Amine Jerraya	Efficient Integration of Behavioral Synthesis with Existing Design Flows.	ISSS	2000	DBLP DOI BibTeX RDF
9	Wander O. Cesário, Ahmed Amine Jerraya, Zoltan Sugar, Imed Moussa	Rethinking Behavioral Synthesis for a Better Integration within Existing Design Flows.	ICCD	2000	DBLP DOI BibTeX RDF
9	Yang Xia, Pranav Ashar	Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture.	VLSI Design	2000	DBLP DOI BibTeX RDF	Combinational Loop, Model Checking, Formal Verification, Temporal Logic, Time Division Multiplexing, Token Ring, Computational Tree Logic, Bus Protocol
9	Gianpiero Cabodi, Stefano Quer, Fabio Somenzi	Optimizing sequential verification by retiming transformations.	DAC	2000	DBLP DOI BibTeX RDF
9	Loe M. G. Feijs	Generating FSMs from Interworkings.	Distributed Comput.	1999	DBLP DOI BibTeX RDF	Sequence chart, Synthesis, Finite state machine, Process algebra
9	Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey	An output encoding problem and a solution technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
9	Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita	Model Checking Based on Sequential ATPG.	CAV	1999	DBLP DOI BibTeX RDF
9	Winfried Nöth, Reiner Kolla	Spanning Tree-based State Encoding for Low Power Dissipation.	DATE	1999	DBLP DOI BibTeX RDF
9	Marine Tabourier, Ana R. Cavalli, Melania Ionescu	A GSM-MAP Protocol Experiment Using Passive Testing.	World Congress on Formal Methods	1999	DBLP DOI BibTeX RDF
9	Chung-Shyan Liu	A Program Generator for Object-based Implementation of Communication Protocol Software.	ISADS	1999	DBLP DOI BibTeX RDF
9	François Pêcheux, Yannick Hervé	DIPS for MIPS: An Instrumented VHDL/Corba Kernel for Distributed Learning in EECS.	MSE	1999	DBLP DOI BibTeX RDF
9	In-Ho Moon, James H. Kukula, Thomas R. Shiple, Fabio Somenzi	Least fixpoint approximations for reachability analysis.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang	A bipartition-codec architecture to reduce power in pipelined circuits.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Jens Schönherr, Ingo Schreiber, Eva Fordran, Bernd Straube	Hazard Checking in Pipelined Processor Designs Using Symbolic Model Checking.	EUROMICRO	1999	DBLP DOI BibTeX RDF
9	Young Moo Lee, Kyu Ho Park	Unified Modeling Graph for Specifying and Synthesizing Chip-Level Interfaces.	EUROMICRO	1999	DBLP DOI BibTeX RDF
9	Pranav Ashar, Anand Raghunathan, Aarti Gupta, Subhrajit Bhattacharya	Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.	ICCD	1999	DBLP DOI BibTeX RDF
9	Peter Bodorik, Dawn N. Jutla, A. Agarwal	Recoverable Virtual Memory through the Multi-View Memory Computer System.	HICSS	1999	DBLP DOI BibTeX RDF	Recoverable Virtual Memory, Multi-view Virtual Memory, Protection Architecture, Architectural Support for Operating Systems, Access Control
9	Prabhas Chongstitvatana, Chatchawit Aporntewan	Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences.	Evolvable Hardware	1999	DBLP DOI BibTeX RDF
9	Rashmi Goswami, V. Srinivasan, M. Balakrishnan	MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign.	VLSI Design	1999	DBLP DOI BibTeX RDF
9	Cesare Alippi, Franco Fummi, Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto	Testability analysis and behavioral testing of the Hopfield neural paradigm.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
9	Rajeev Alur, Mihalis Yannakakis	Model Checking of Hierarchical State Machines.	SIGSOFT FSE	1998	DBLP DOI BibTeX RDF
9	Dawn N. Jutla, Peter Bodorik	Architectural Support for Synchronization of Threads Accessing Variable-Sized Units of Virtual Memory.	HICSS (3)	1998	DBLP DOI BibTeX RDF
9	Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha	An Exact Input Encoding Algorithm for BDDs Representing FSMs.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	input encoding, finite state machines, binary decision diagrams, multi-valued decision diagrams
9	Youpyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen Sentovich	Don't Care-Based BDD Minimization for Embedded Software.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
9	Pai H. Chou, Gaetano Borriello	Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems.	DAC	1998	DBLP DOI BibTeX RDF
9	Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz	Approximate Reachability with BDDs Using Overlapping Projections.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
9	Timothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Theory and algorithms for state minimization of nondeterministic FSMs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
9	Wayne H. Wolf	Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	scheduling dont-care, high-level synthesis, redundancy
9	Hiroaki Iwashita, Tsuneo Nakata	Forward model checking techniques oriented to buggy designs.	ICCAD	1997	DBLP DOI BibTeX RDF	symbolic state traversal, forward model checking, formal verification, symbolic model checking
9	Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello	Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
9	Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal	Functional test generation for synchronous sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
9	Enrique Alba 0001, José M. Troya	Genetic Algorithms for Protocol Validation.	PPSN	1996	DBLP DOI BibTeX RDF
9	Uwe Wildner	Compiler Assisted Self-checking of Structural Integrity Using Return Address Hashing.	EDCC	1996	DBLP DOI BibTeX RDF
9	Ellen Sentovich, Horia Toma, Gérard Berry	Latch optimization in circuits generated from high-level descriptions.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential optimisation, high-level synthesis, state assignment
9	K. Vijayananda	Distributed fault detection in communication protocols using extended finite state machines.	ICPADS	1996	DBLP DOI BibTeX RDF	distributed fault detection, run-time fault detection, coding defects, memory problems, protocol faults, vocabulary faults, sequencing faults, parallel decomposition method, multiple observers, distributed fault detection mechanism, fault tolerant computing, finite state machines, transport protocols, encoding, communication protocols, fault coverage, extended finite state machines
9	Jun Bi, Jianping Wu	A STREAMS based high performance IP/X.25 router.	ISPAN	1996	DBLP DOI BibTeX RDF	IP/X.25, TCP/IP networks, connection oriented subnetwork, performance evaluation, STREAMS, finite state machine, interconnection, Unix, transport protocols, high performance, internetworking, internetworking, interoperability testing, communication software
9	Murali M. R. Gala, Don E. Ross, Karan L. Watson, Beena Vasudevan, Peter Utama	Built-in self test for C-testable ILA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Luis Entrena-Arrontes, Kwang-Ting Cheng	Combinational and sequential logic optimization by redundancy addition and removal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	Sukumar Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
9	Heikki Saastamoinen, George M. White	On handling exceptions.	COOCS	1995	DBLP DOI BibTeX RDF
9	Tan-Li Chou, Kaushik Roy 0001	Estimation of sequential circuit activity considering spatial and temporal correlations.	ICCD	1995	DBLP DOI BibTeX RDF	sequential circuit activity estimation, signal activity, internal nodes, sequential logic circuits, logic signals, ESTG, extended state transition graph, exact signal probabilities, large circuits, state logic, logic simulation results, graph theory, finite state machines, finite state machine, sequential circuits, spatial correlations, circuit switching, switching activities, approximate method, temporal correlations
9	Said Amellal, Bozena Kaminska	Functional synthesis of digital systems with TASS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
9	Luca Benini, Polly Siegel, Giovanni De Micheli	Saving Power by Synthesizing Gated Clocks for Sequential Circuits.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
9	Adnan Aziz, Thomas R. Shiple, Vigyan Singhal	Formula-Dependent Equivalence for Compositional CTL Model Checking.	CAV	1994	DBLP DOI BibTeX RDF
9	Chuan-Jin Shi, Janusz A. Brzozswski	An efficient algorithm for constrained encoding and its applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer	Delay-fault test generation and synthesis for testability under a standard scan design methodology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi	Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Irith Pomeranz, Kwang-Ting Cheng	STOIC: state assignment based on output/input functions.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
9	Margot Karam, Gabriele Saucier	Functional versus random test generation for sequential circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	simulation, Finite state machine, functional testing, graph traversal
9	Toshimasa Watanabe, Toshiya Mashima, Satoshi Taoka	The k-Edge-Connectivity Augmentation Problem of Weighted Graphs.	ISAAC	1992	DBLP DOI BibTeX RDF
9	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Test generation and verification for highly sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
9	Fabrizio Lombardi, Yinan N. Shen, Hannu H. Kari	On a new approach for enhancing the fault coverage of conformance testing of protocols.	SPDP	1991	DBLP DOI BibTeX RDF
9	Tiziano Villa, Alberto L. Sangiovanni-Vincentelli	NOVA: state assignment of finite state machines for optimal two-level logic implementation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
9	David Binger, David Knapp	Automatic synthesis of a dual-PLA controller with a counter.	MICRO	1990	DBLP BibTeX RDF
9	Vishwani D. Agrawal, Kwang-Ting Cheng	An architecture for synthesis of testable finite state machines.	EURO-DAC	1990	DBLP DOI BibTeX RDF
9	Siegfried I. Mensch, Hans Martin Lipp	Fuzzy specification of finite state machines.	EURO-DAC	1990	DBLP DOI BibTeX RDF
9	Kassem Saleh, Robert L. Probert	Synthesis of Error-Recoverable Protocol Specifications from Service Specifications.	ICCI	1990	DBLP DOI BibTeX RDF	syntactic correctness, synthesis, error-recovery, protocol design, semantic correctness, Communication software
9	Pranav Ashar, Srinivas Devadas, A. Richard Newton	A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.	DAC	1990	DBLP DOI BibTeX RDF
9	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Verification of Interacting Sequential Circuits.	DAC	1990	DBLP DOI BibTeX RDF
9	Dwight D. Hill, Bryan Preas	Benchmarks for Cell Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
9	Doron Drusinsky, David Harel	Using statecharts for hardware description and synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
9	Alexandre Bronstein, Carolyn L. Talcott	Formal Verification of Synchronous Circuits based on String-Functional Semantics: The 7 Paillet Circuits in Boyer-Moore.	Automatic Verification Methods for Finite State Systems	1989	DBLP DOI BibTeX RDF
9	Tiziano Villa, Alberto L. Sangiovanni-Vincentelli	NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations.	DAC	1989	DBLP DOI BibTeX RDF
9	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	MUSTANG: state assignment of finite state machines targeting multilevel logic implementations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
9	Franz Pichler	Finite State Machine Modelling of Cryptographic Systems in Loops.	EUROCRYPT	1987	DBLP DOI BibTeX RDF
9	Rainer Brück 0001, Bernd Kleinjohann, Thomas Kathöfer, Franz J. Rammig	Synthesis of concurrent modular controllers from algorithmic descriptions.	DAC	1986	DBLP DOI BibTeX RDF
9	Krishan K. Sabnani, Anton T. Dahbura	A new technique for generating protocol test.	SIGCOMM	1985	DBLP DOI BibTeX RDF