Search results for "circuit"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Lutz Finger	The Josephson junction circuit family: network theory.	Int. J. Circuit Theory Appl.	2000	DBLP DOI BibTeX RDF
17	Sami Barmada, Marco Raugi	A general tool for circuit analysis based on wavelet transform.	Int. J. Circuit Theory Appl.	2000	DBLP DOI BibTeX RDF
17	Matthew Worsman, Mike W. T. Wong	Non‐linear analog circuit fault diagnosis with large change sensitivity.	Int. J. Circuit Theory Appl.	2000	DBLP DOI BibTeX RDF
17	Marco Storace, Mauro Parodi, Dario Robatto	A hysteresis‐based chaotic circuit: dynamics and applications.	Int. J. Circuit Theory Appl.	1999	DBLP DOI BibTeX RDF
17	Péter Szolgay, Katalin Tömördi	Analogic algorithms for optical detection of breaks and short circuits on the layouts of printed circuit boards using CNN.	Int. J. Circuit Theory Appl.	1999	DBLP DOI BibTeX RDF
17	Spiridon Nikolaidis 0001, Alexander Chatzigeorgiou	Analytical estimation of propagation delay and short‐circuit power dissipation in CMOS gates.	Int. J. Circuit Theory Appl.	1999	DBLP DOI BibTeX RDF
17		Sandberg IW, 'Multidimensional linear systems: the extra term'. International Journal of Circuit Theory and Applications 1999; 27(4): 415-420.	Int. J. Circuit Theory Appl.	1999	DBLP DOI BibTeX RDF
17	Mauro Parodi, Marco Storace, Carlo S. Regazzoni	Circuit realization of Markov random fields for analog image processing.	Int. J. Circuit Theory Appl.	1998	DBLP DOI BibTeX RDF
17	Marco Storace, Mauro Parodi	On the representation of static hysteresis curves by a PWL ladder circuit.	Int. J. Circuit Theory Appl.	1998	DBLP DOI BibTeX RDF
17	Udo Jörges, G. Jummel	A macromodel of the transfer characteristics of chopper-stabilized operational amplifiers oriented by the circuit structure.	Int. J. Circuit Theory Appl.	1997	DBLP DOI BibTeX RDF
17	Lubomir V. Kolev, Valeri M. Mladenov	Use of interval slopes in implementing an interval method for global non-linear DC circuit analysis.	Int. J. Circuit Theory Appl.	1997	DBLP DOI BibTeX RDF
17	Mauro Parodi, Marco Storace	On a circuit representation of the Hodgkin and Huxley nerve axon membrane equations.	Int. J. Circuit Theory Appl.	1997	DBLP DOI BibTeX RDF
17	Feng Lin, Zheng-Hui Lin, T. William Lin	A uniform approach to mixed-signal circuit test.	Int. J. Circuit Theory Appl.	1997	DBLP DOI BibTeX RDF
17	Qicheng Yu, Carl Sechen	Generation of colour-constrained spanning trees with application in symbolic circuit analysis.	Int. J. Circuit Theory Appl.	1996	DBLP DOI BibTeX RDF
17	Mauro Parodi, Marco Storace, Silvano Cincotti	Static and dynamic hysteretic features in a PWL circuit.	Int. J. Circuit Theory Appl.	1996	DBLP DOI BibTeX RDF
17	Hans Georg Brachtendorf, Günther Welsch, Rainer Laur	A simulation tool for the analysis and verification of the steady state of circuit designs.	Int. J. Circuit Theory Appl.	1995	DBLP DOI BibTeX RDF
17	Guntram E. Müller-Liebler	PastA - the characterization of the inherent fluctuations in the fabrication process for circuit simulation.	Int. J. Circuit Theory Appl.	1995	DBLP DOI BibTeX RDF
17	Theodore Karoubalis, Kostas Adaos, George Alexiou, Nick Kanopoulos	A new efficient dcvs circuit synthesis technique used for an improved implementation of a serial/parallel multiplier.	Int. J. Circuit Theory Appl.	1995	DBLP DOI BibTeX RDF
17	Samuil L. Farchy, Elisaveta D. Gadzheva, Lyudmila H. Raykovska, Todor G. Kouyoumdjiev	Nullator-norator approach to analogue circuit diagnosis using general-purpose analysis programmes.	Int. J. Circuit Theory Appl.	1995	DBLP DOI BibTeX RDF
17	Wim Kruiskamp, Domine Leenaerts	Darwin: Analogue circuit synthesis based on genetic algorithms.	Int. J. Circuit Theory Appl.	1995	DBLP DOI BibTeX RDF
17	Leon O. Chua	Chua's circuit 10 years later.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Renzo Perfetti	On the OP-amp based circuit design of cellular neural networks.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Hervé Dedieu, Catherine Dehollain, Jacques Neirynck, Graham Rhodes	New broadband-matching circuit.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Lubomir V. Kolev, Valeri M. Mladenov	An interval method for global non-linear dc circuit analysis.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Tadej Tuma, Franc Bratkovic	A general approach to circuit equations.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Giuseppe Martinelli, Renzo Perfetti	Circuit theoretic approach to the tank-hopfield A/D converter.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Mauro Parodi, Marco Storace, Silvano Cincotti	A PWL ladder circuit which exhibits hysteresis.	Int. J. Circuit Theory Appl.	1994	DBLP DOI BibTeX RDF
17	Dario D'Amore, William Fornaciari	A spice-based approach to steady state circuit analysis.	Int. J. Circuit Theory Appl.	1993	DBLP DOI BibTeX RDF
17	Shoba Krishnan, Chin-Long Wey	An accurate reference-generating circuit for successive approximation current mode A/D converters.	Int. J. Circuit Theory Appl.	1993	DBLP DOI BibTeX RDF
17	Martin Hasler	The backpropagation learning algorithm realized by an analogue circuit.	Int. J. Circuit Theory Appl.	1993	DBLP DOI BibTeX RDF
17	Michael Peter Kennedy	Synthesis of continuous three-segment voltage-controlled piecewise-linear resistors for Chua's circuit family using operational amplifiers, diodes and linear resistors.	Int. J. Circuit Theory Appl.	1993	DBLP DOI BibTeX RDF
17	José M. Cruz, Leon O. Chua	An IC diode for Chua's circuit.	Int. J. Circuit Theory Appl.	1993	DBLP DOI BibTeX RDF
17	Cüneyt Güzelis	Chaotic Cellular Neural Networks Made of Chua's Circuits.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Michal Misiurewicz	Unimodal interval Maps obtained from the modified Chua equations.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Ljupco Kocarev, K. Sean Halle, Kevin Eckert, Leon O. Chua, Ulrich Parlitz	Experimental Demonstration of Secure Communications via Chaotic Synchronization.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	K. Sean Halle, Leon O. Chua, Vadim S. Anishchenko, M. A. Safonova	Signal Amplification via Chaos: Experimental Evidence.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Vladimir N. Belykh, N. N. Verichev, Ljupco Kocarev, Leon O. Chua	On Chaotic Synchronization in a linear array of Chua's Circuits.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Maciej J. Ogorzalek, Zbigniew Galias	Characterisation of Chaos in Chua's oscillator in Terms of unstable periodic orbits.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Philippe Deregel	Chua's oscillator: a Zoo of attractors.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	L. P. Shil'nikov	Strange attractors and dynamical Models.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Gennady A. Leonov, D. V. Ponomarenko, Vera B. Smirnova, Leon O. Chua	Global stability and instability of Canonical Chua's Circuits.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Vicente Pérez-Muñuzuri, V. Pérez-Villar, Leon O. Chua	Traveling wave front and its Failure in a One-dimensional array of Chua's Circuits.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Ulrich Parlitz, Leon O. Chua, Ljupco Kocarev, K. Sean Halle, Alain Shang	Transmission of Digital signals by Chaotic Synchronization.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Vladimir I. Nekorkin, Leon O. Chua	Spatial Disorder and wave Fronts in a Chain of coupled Chua's Circuits.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Valentin S. Afraimovich, Leon O. Chua	Enigma of the double-scroll Chua's Attractor.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Ljupco Kocarev, Tamás Roska	Dynamics of the Lorenz equation and Chua's equation: a Tutorial.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Ljupco Kocarev, Alain Shang, Leon O. Chua	A Unified method of control and Synchronization of Chaos.	Chua's Circuit	1993	DBLP DOI BibTeX RDF
17	Josef A. Nossek, Gerhard Seiler, Tamás Roska, Leon O. Chua	Cellular neural networks: Theory and circuit design.	Int. J. Circuit Theory Appl.	1992	DBLP DOI BibTeX RDF
17	Christopher Michael, Christopher J. Abel, Mohammed Ismail 0001	SMOS: A CAD-compatible statistical model for analogue mos integrated circuit simulation.	Int. J. Circuit Theory Appl.	1992	DBLP DOI BibTeX RDF
17	D. Golzio, S. Graffi, Zsolt Miklós Kovács-Vajna, G. Masetti	Circuit macromodels and large-signal behaviour of fet-input operational amplifiers.	Int. J. Circuit Theory Appl.	1992	DBLP DOI BibTeX RDF
17	Xiangming Xiao, Robert Spence	Trade-off prediction and circuit performance optimization using a second-order model.	Int. J. Circuit Theory Appl.	1992	DBLP DOI BibTeX RDF
17	Magatte Diouf, Charles-Henri Carlin	Relaxation-based computation of a synchronous sequential circuit stable state.	Int. J. Circuit Theory Appl.	1992	DBLP DOI BibTeX RDF
17	Domine M. W. Leenaerts, Johannes A. Hegt	Finding all solutions of piecewise linear functions and application to circuit design.	Int. J. Circuit Theory Appl.	1991	DBLP DOI BibTeX RDF
17	Tat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch	Parametric yield optimization of CMOS analogue circuits by quadratic statistical circuit performance models.	Int. J. Circuit Theory Appl.	1991	DBLP DOI BibTeX RDF
17	A. H. M. Saleh, Donard de Cogan	An equivalent circuit for the analysis of transmission line matrix (tlm) scattering algorithms.	Int. J. Circuit Theory Appl.	1991	DBLP DOI BibTeX RDF
17	R. M. Biernacki, M. A. Styblinski	Efficient performance function interpolation scheme and its application to statistical circuit design.	Int. J. Circuit Theory Appl.	1991	DBLP DOI BibTeX RDF
17	Michael Peter Kennedy, Leon O. Chua	Hysteresis in electronic circuits: A circuit theorist's perspective.	Int. J. Circuit Theory Appl.	1991	DBLP DOI BibTeX RDF
17	Claus Kahlert	Dynamics of the inclusions appearing in the return maps of chua's circuit. Part II: The annihilation mechanism.	Int. J. Circuit Theory Appl.	1990	DBLP DOI BibTeX RDF
17	Marc Fosseprez, Martin Hasler	Resistive circuit topologies that admit several solutions.	Int. J. Circuit Theory Appl.	1990	DBLP DOI BibTeX RDF
17	Tamás Roska	Limitations and complexity of digital hardware simulators used for large-scale analogue circuit and system dynamics.	Int. J. Circuit Theory Appl.	1990	DBLP DOI BibTeX RDF
17	Basab Datta, Wayne P. Burleson	Circuit-level NBTI macro-models for collaborative reliability monitoring.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	macro-models, on-chip sensors, calibration, NBTI
17	Yalei Cui, Zibin Dai	The Research of NULL Convention Logic Circuit Computing Model Targeted at Block Cipher Processing.	IAS	2009	DBLP DOI BibTeX RDF
17	He Peng, Chung-Kuan Cheng	Parallel transistor level circuit simulation using domain decomposition methods.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Ming-Chien Tsai, Ching-Hwa Cheng	A full-synthesizable high-precision built-in delay time measurement circuit.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
17	Takushi Tanaka	Deriving Electrical Dependencies from Circuit Topologies Using Logic Grammar.	KES (2)	2009	DBLP DOI BibTeX RDF
17	Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Erect of regularity-enhanced layout on printability and circuit performance of standard cells.	ISQED	2009	DBLP DOI BibTeX RDF
17	Xin He, Syed Al-Kadry, Afshin Abdollahi	Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit.	ISQED	2009	DBLP DOI BibTeX RDF
17	Cheng Jia, Linda S. Milor	A BIST Circuit for DLL Fault Detection.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
17	Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann	The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Dimitrios K. Konstantinou, Michael G. Dimopoulos, Dimitris K. Papakostas, Alkis A. Hatzopoulos, Alexios Spyronasios	Testing an Emergency Luminaire Circuit Using a Fault Dictionary Approach.	DDECS	2008	DBLP DOI BibTeX RDF
17	Xin Fu, Tao Li, José A. B. Fortes	Combined circuit and microarchitecture techniques for effective soft error robustness in SMT processors.	DSN	2008	DBLP DOI BibTeX RDF
17	Zhusong Liu, Simin Yu, Guobo Xie, Yijun Liu	A Novel Fourth-Order Chaotic Circuit and Its Implementation.	ICYCS	2008	DBLP DOI BibTeX RDF
17	Ranko Sredojevic, Vladimir Stojanovic	Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example.	ICCAD	2008	DBLP DOI BibTeX RDF
17	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
17	John Oliver, Mark Lehne, Krishna Vummidi, Amy Bell, Sanjay Raman	A low power CMOS sigma-delta readout circuit for heterogeneously integrated chemoresistive micro-/nano- sensor arrays.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Jayawan H. B. Wijekoon, Piotr Dudek	Integrated circuit implementation of a cortical neuron.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Daisuke Atuti, Kazuki Nakada, Takashi Morie	CMOS pulse-modulation circuit implementation of phase-locked loop neural networks.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Nader Safavian, G. Reza Chaji, Karim S. Karim, John A. Rowlands	A novel hybrid active-passive pixel with correlated double sampling CMOS readout circuit for medical x-ray imaging.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Peng Xu, Timothy K. Horiuchi, Pamela Abshire	Stochastic model and simulation of a random number generator circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Toru Tanzawa	A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage.	ISCAS	2008	DBLP DOI BibTeX RDF
17	Yue Chi, Zhushi Xie, Kewen Xia, Xin Liu	Static Power Optimization for CMOS Combinational Circuit Based on Bacterial Colony Chemotaxis Algorithm.	CSSE (5)	2008	DBLP DOI BibTeX RDF
17	Minglang Lin, Ahmet T. Erdogan, Tughrul Arslan, Adrian Stoica	A novel CMOS exponential approximation circuit.	SoCC	2008	DBLP DOI BibTeX RDF
17	Farhad Alibeygi Parsan, Ahmad Ayatollahi	A comparator-based switched-capacitor integrator using a new charge control circuit.	SoCC	2008	DBLP DOI BibTeX RDF
17	Suganth Paul, Rajesh Garg, Sunil P. Khatri	Pipelined network of PLA based circuit design.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	synchronous, pipelining, PLA
17	Wenping Wang, Shengqi Yang, Yu Cao 0001	Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect.	ISQED	2008	DBLP DOI BibTeX RDF
17	Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang	An All-Digital High-Precision Built-In Delay Time Measurement Circuit.	VTS	2008	DBLP DOI BibTeX RDF
17	Zhihua Wang 0001, Songping Mai, Chun Zhang	Power Issues on Circuit Design for Cochlear Implants.	DELTA	2008	DBLP DOI BibTeX RDF	low power, power efficiency, cochlear implant
17	Natalie D. Enright Jerger, Mikko H. Lipasti, Li-Shiuan Peh	Circuit-Switched Coherence.	IEEE Comput. Archit. Lett.	2007	DBLP DOI BibTeX RDF
17	Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester	Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
17	Yokesh Kumar, Prosenjit Gupta	An External Memory Circuit Validation Algorithm for Large VLSI Layouts.	ISVLSI	2007	DBLP DOI BibTeX RDF
17	Almitra Pradhan, Ranga Vemuri	Regression based circuit matrix models for accurate performance estimation of analog circuits.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
17	Wenqian Li, Hanwu Chen, Zhiqiang Li 0001	Application of Semi-Template in Reversible Logic Circuit.	CSCWD	2007	DBLP DOI BibTeX RDF
17	Gilles Audemard, Lakhdar Sais	Circuit Based Encoding of CNF Formula.	SAT	2007	DBLP DOI BibTeX RDF
17	Frank Liu 0001	An efficient method for statistical circuit simulation.	ICCAD	2007	DBLP DOI BibTeX RDF
17	Mingjing Chen, Alex Orailoglu	Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.	ICCD	2007	DBLP DOI BibTeX RDF
17	Nader Safavian, G. Reza Chaji, Shahin Jafarabadi-Ashtiani, Arokia Nathan, John A. Rowlands	A novel current scaling active pixel sensor with correlated double sampling readout circuit for real time medical x-ray imaging.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Martin Di Federico, Pedro Julián, Tomaso Poggi, Marco Storace	A Simplicial PWL Integrated Circuit Realization.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Jayawan H. B. Wijekoon, Piotr Dudek	Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit.	IJCNN	2007	DBLP DOI BibTeX RDF
17	Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy 0001	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.	DAC	2007	DBLP DOI BibTeX RDF