Search results for "layout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Antonio Adán, Pilar Merchán, Santiago Salamanca, Andrés S. Vázquez, Miguel Adán, Carlos Cerrada	Objects layout graph for 3D complex scenes.	ICIP (3)	2005	DBLP DOI BibTeX RDF
17	Guilin Chen, Mahmut T. Kandemir, Mustafa Karaköy	A Constraint Network Based Approach to Memory Layout Optimization.	DATE	2005	DBLP DOI BibTeX RDF
17	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.	DSD	2005	DBLP DOI BibTeX RDF
17	Satoshi Hashimoto, Kazunori Haruyama, Taro Nakamura, Toyohisa Nakajima, Yuko Osana	Office layout support system using island model genetic algorithm.	Congress on Evolutionary Computation	2005	DBLP DOI BibTeX RDF
17	Ke Cao, Puneet Dhawan, Jiang Hu	Library cell layout with Alt-PSM compliance and composability.	ASP-DAC	2005	DBLP DOI BibTeX RDF
17	Peter Sobe	Distributed Storage Layout Schemes.	IPDPS	2005	DBLP DOI BibTeX RDF
17	Koenraad Mertens, Tom Holvoet, Yolande Berbers	An Adaptive Distributed Layout for Multi-agent Applications.	SELMAS (LNCS)	2005	DBLP DOI BibTeX RDF
17	Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS.	ICCD	2005	DBLP DOI BibTeX RDF
17	Gagan Aggarwal, Tomás Feder, Rajeev Motwani 0001, Rina Panigrahy, An Zhu	Algorithms for the Database Layout Problem.	ICDT	2005	DBLP DOI BibTeX RDF
17	Jeyarajan Thiyagalingam, Olav Beckmann, Paul H. J. Kelly	Minimizing Associativity Conflicts in Morton Layout.	PPAM	2005	DBLP DOI BibTeX RDF
17	Xin Dai, Chengming He, Hanqing Xing, Degang Chen 0001, Randall L. Geiger	An Nth order central symmetrical layout pattern for nonlinear gradients cancellation.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
17	Qianying Tang, Jianwen Zhu	Two-Dimensional Layout Migration by Soft Constraint Satisfaction.	ISQED	2005	DBLP DOI BibTeX RDF
17	Manish Garg, Laurent Le Cam, Matthieu Gonzalez	Lithography Driven Layout Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
17	John William Lumley, Roger Gimson, Owen Rees	A framework for structure, layout & function in documents.	ACM Symposium on Document Engineering	2005	DBLP DOI BibTeX RDF	XML, functional programming, XSLT, SVG, document construction
17	Margherita Berardi, Oronzo Altamura, Michelangelo Ceci, Donato Malerba	A color-based layout analysis to process censorship cards of film archives.	ICDAR	2005	DBLP DOI BibTeX RDF
17	Nattawut Thepayasuwan, Alex Doboli	Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip.	DATE	2004	DBLP DOI BibTeX RDF
17	Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich	Impact of Test Point Insertion on Silicon Area and Timing during Layout.	DATE	2004	DBLP DOI BibTeX RDF
17	Sriram Krishnamoorthy, Gerald Baumgartner, Chi-Chung Lam, Jarek Nieplocha, P. Sadayappan	Efficient Layout Transformation for Disk-Based Multidimensional Arrays.	HiPC	2004	DBLP DOI BibTeX RDF
17	Feihui Li, Pyush Agrawal, Grace Eberhardt, Eren Manavoglu, Secil Ugurel, Mahmut T. Kandemir	Improving Memory Performance of Embedded Java Applications by Dynamic Layout Modifications.	IPDPS	2004	DBLP DOI BibTeX RDF
17	Lubomir Torok, Imrich Vrto	Layout Volumes of the Hypercube.	GD	2004	DBLP DOI BibTeX RDF
17	Kuang-Kuo Lin, Sudhakar Kale, Aditi Nigam	Methodology for Automated Layout Migration for 90 nm Itanium®2 Processor Design.	ISQED	2004	DBLP DOI BibTeX RDF
17	Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada	Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.	ISQED	2004	DBLP DOI BibTeX RDF
17	Sébastien Choplin, Lata Narayanan, Jaroslav Opatrny	Two-Hop Virtual Path Layout in Tori.	SIROCCO	2004	DBLP DOI BibTeX RDF
17	Junhyung Um, Taewhan Kim	Synthesis of arithmetic circuits considering layout effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
17	Rakesh Agrawal 0001, Surajit Chaudhuri, Abhinandan Das, Vivek R. Narasayya	Automating Layout of Relational Databases.	ICDE	2003	DBLP DOI BibTeX RDF
17	Márta Rencz, Vladimír Székely, András Poppe	A Fast Algorithm for the Layout Based Electro-Thermal Simulation.	DATE	2003	DBLP DOI BibTeX RDF
17	Quang Vinh Nguyen, Mao Lin Huang	A Fast Focus + Context Viewing Technique for the Navigation of Classical Hierarchical Layout.	IV	2003	DBLP DOI BibTeX RDF
17	Sriram Padmanabhan, Bishwaranjan Bhattacharjee, Timothy Malkemus, Leslie Cranston, Matthew Huras	Multi-Dimensional Clustering: A New Data Layout Scheme in DB2.	SIGMOD Conference	2003	DBLP DOI BibTeX RDF
17	Lars Liebmann	Layout impact of resolution enhancement techniques: impediment or opportunity?	ISPD	2003	DBLP DOI BibTeX RDF	radically restricted designs, resolution enhancement techniques, design for manufacturability, lithography
17	Roland Sturm, Joachim Seidelmann, Johann Dorner, Kevin Reddig	Automated material handling systems: an approach to robust layout planning of AMHS.	WSC	2003	DBLP DOI BibTeX RDF
17	Georg Sander	Layout of Directed Hypergraphs with Orthogonal Hyperedges.	GD	2003	DBLP DOI BibTeX RDF
17	Sarat C. Maruvada, Karthik Krishnamoorthy, Subodh Annojvala, Florin Balasa	Placement with symmetry constraints for analog layout using red-black trees.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
17	Sophon Vorasitchai, Suthep Madarasmi	Improvements on layout of garment patterns for efficient fabric consumption.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
17	Véronique Eglin, Stéphane Bres	Document page similarity based on layout visual saliency: Application to query by example and document classification.	ICDAR	2003	DBLP DOI BibTeX RDF
17	Thomas M. Breuel	An Algorithm for Finding Maximal Whitespace Rectangles at Arbitrary Orientations for Document Layout Analysis.	ICDAR	2003	DBLP DOI BibTeX RDF
17	Alexandre César Muniz de Oliveira, Luiz Antonio Nogueira Lorena	A constructive genetic algorithm for gate matrix layout problems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
17	Thomas M. Breuel	Two Geometric Algorithms for Layout Analysis.	Document Analysis Systems	2002	DBLP DOI BibTeX RDF
17	Apostolos Antonacopoulos, Hong Meng	A Ground-Truthing Tool for Layout Analysis Performance Evaluation.	Document Analysis Systems	2002	DBLP DOI BibTeX RDF
17	Binyamin Rosenfeld, Ronen Feldman, Yonatan Aumann	Structural extraction from visual layout of documents.	CIKM	2002	DBLP DOI BibTeX RDF
17	Shimon Even, Roni Kupershtok	Layout area of the hypercube (extended abstract).	SODA	2002	DBLP BibTeX RDF
17	Adrish Ray Chaudhuri, A. K. Mandal, B. B. Chaudhuri 0001	Page Layout Analyser for Multilingual Indian Documents.	Language Engineering Conference	2002	DBLP DOI BibTeX RDF
17	Heikki Keränen, Johan Plomp	Adaptive runtime layout of hierarchical UI components.	NordiCHI	2002	DBLP DOI BibTeX RDF	constant information density, elastic windows, adaptive user interfaces, zoomable user interfaces, treemaps
17	Alistair Morrison, Greg Ross, Matthew Chalmers	A Hybrid Layout Algorithm for Sub-Quadratic Multidimensional Scaling.	INFOVIS	2002	DBLP DOI BibTeX RDF
17	Markus Kowarschik, Ulrich Rüde, Christian Weiß 0001	Data Layout Optimizations for Variable Coefficient Multigrid.	International Conference on Computational Science (3)	2002	DBLP DOI BibTeX RDF
17	Kwok-Wing Chau, M. Anson	A Knowledge-Based System for Construction Site Level Facilities Layout.	IEA/AIE	2002	DBLP DOI BibTeX RDF
17	Florin Balasa	Device-level placement for analog layout: an opportunity for non-slicing topological representations.	ASP-DAC	2001	DBLP DOI BibTeX RDF
17	Wei Lai	Layout Adjustment and Boundary Detection for a Diagram.	Computer Graphics International	2001	DBLP DOI BibTeX RDF
17	Roland Wiese, Markus Eiglsperger, Michael Kaufmann 0001	yFiles: Visualization and Automatic Layout of Graphs.	GD	2001	DBLP DOI BibTeX RDF
17	Ka-Ping Yee, Danyel Fisher, Rachna Dhamija, Marti A. Hearst	Animated Exploration of Dynamic Graphs with Radial Layout.	INFOVIS	2001	DBLP DOI BibTeX RDF
17	Juan A. Montiel-Nelson, De de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi	A compact layout technique to minimize high frequency switching effects in high speed circuits.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
17	Susan L. Epstein, Bernard Moulin, Walid Chaker, Janice I. Glasgow, Jeremi Gancet	Pragmatism and Spatial Layout Design.	COSIT	2001	DBLP DOI BibTeX RDF	spatial design, cognitive structure of spatial knowledge, social and cultural organization of space, structure of geographic information, constraint-based reasoning
17	Helen C. Purchase, David A. Carrington, Jo-Anne Allder	Experimenting with Aesthetics-Based Graph Layout.	Diagrams	2000	DBLP DOI BibTeX RDF
17	Youcef Bourai, C.-J. Richard Shi	Layout Compaction for Yield Optimization via Critical Area Minimization.	DATE	2000	DBLP DOI BibTeX RDF
17	Natalie Eckel, Joseph Gil	Empirical Study of Object-Layout Strategies and Optimization Techniques.	ECOOP	2000	DBLP DOI BibTeX RDF
17	Vance E. Waddle	Graph Layout for Displaying Data Structures.	GD	2000	DBLP DOI BibTeX RDF
17	Ulrik Brandes, Galina Shubina, Roberto Tamassia, Dorothea Wagner	Fast Layout Methods for Timetable Graphs.	GD	2000	DBLP DOI BibTeX RDF
17	Carl De Ranter, Bram De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen	CYCLONE: automated design and layout of RF LC-oscillators.	DAC	2000	DBLP DOI BibTeX RDF
17	Tong Liu 0007, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi	Test generation and scheduling for layout-based detection of bridge faults in interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
17	Jeffrey P. Bradford, Russell W. Quong	An empirical study on how program layout affects cache miss rates.	SIGMETRICS Perform. Evaluation Rev.	1999	DBLP DOI BibTeX RDF
17	Piotr Berman, Andrew B. Kahng, Devendra Vidhani, Alexander Zelikovsky	The T-join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout.	WADS	1999	DBLP DOI BibTeX RDF
17	Guo-Hui Lin, Guoliang Xue, Defang Zhou	Approximating Hexagonal Steiner Minimal Trees by Fast Optimal Layout of Minimum Spanning Trees.	ICCD	1999	DBLP DOI BibTeX RDF	VLSI physical design, hexagonal routing, approximation algorithms
17	Stefano Rovetta, Rodolfo Zunino	VLSI circuits with fractal layout for spatial image decorrelation.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
17	Chi-Keung Luk, Todd C. Mowry	Memory Forwarding: Enabling Aggressive Layout Optimizations by Guaranteeing the Safety of Data Relocation.	ISCA	1999	DBLP DOI BibTeX RDF
17	John D. Hobby	Page Decomposition and Signature Finding via Shape Classification and Geometric Layout.	ICDAR	1999	DBLP DOI BibTeX RDF
17	Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani	Module packing based on the BSG-structure and IC layout applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
17	Aythan Avior, Tiziana Calamoneri, Shimon Even, Ami Litman, Arnold L. Rosenberg	A Tight Layout of the Butterfly Network.	Theory Comput. Syst.	1998	DBLP DOI BibTeX RDF
17	Evanthia Papadopoulou	Linfinity Voronoi Diagrams and Applications to VLSI Layout and Manufacturing.	ISAAC	1998	DBLP DOI BibTeX RDF
17	Min Xu, Fadi J. Kurdahi	Layout-Driven High Level Synthesis for FPGA Based Architectures.	DATE	1998	DBLP DOI BibTeX RDF
17	Sumito Nakano, Naotake Kamiura, Yutaka Hata	Fault Tolerance of a Tree-Connected Multiprocessor System and its Arraylike Layout.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
17	Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, U. Nagaraj Shenoy, Prithviraj Banerjee	Enhancing Spatial Locality via Data Layout Optimizations.	Euro-Par	1998	DBLP DOI BibTeX RDF
17	Hamdy Elwany, Mohamed G. Abou-Ali, Nermeen A. Harraz	The Layout Problem: Investigation and Aggregation of Artificial Intelligence and Optimization Techniques.	PRICAI	1998	DBLP DOI BibTeX RDF
17	Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara	A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order.	GD	1998	DBLP DOI BibTeX RDF
17	Min Xu, Fadi J. Kurdahi	Layout-driven RTL binding techniques for high-level synthesis using accurate estimators.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	FPGAs, high-level synthesis, floorplan, binding
17	Les T. Walczowski, D. Nalbantis, W. A. J. Waller, Keng-Hua Shi	Analogue layout generation by World Wide Web server-based agents.	ED&TC	1997	DBLP DOI BibTeX RDF
17	Avaneendra Gupta, John P. Hayes	CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells.	DAC	1997	DBLP DOI BibTeX RDF
17	Enrico Malavasi, Edoardo Charbon, Eric Felt, Alberto L. Sangiovanni-Vincentelli	Automation of IC layout with analog constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
17	Yannis E. Ioannidis, Miron Livny, Jian Bao, Eben M. Haber	User-oriented visual layout at multiple granularities.	AVI	1996	DBLP DOI BibTeX RDF
17	Fadi J. Kurdahi, Champaka Ramachandran	Evaluating layout area tradeoffs for high level applications.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
17	Terence B. Hook	Automatic extraction of circuit models from layout artwork for a BiCMOS technology.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
17	Tetsuto Yoshikawa	A visual knowledge representation language for layout problem.	ICCL	1992	DBLP DOI BibTeX RDF
17	Martin D. F. Wong, Mohankumar Guruswamy	Channel ordering for VLSI layout with rectilinear modules.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
17	Wayne Bower, Carl Seaquist, Wayne H. Wolf	A framework for industrial layout generators.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
17	Kurt Mehlhorn, Wolfgang Rülling	Compaction on the torus [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
17	Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu	A fast transistor-chaining algorithm for CMOS cell layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
17	Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli, Carlo H. Séquin	'Zone-refining' techniques for IC layout compaction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
17	David Marple, Michiel Smulders, Henk Hegen	Tailor: a layout system based on trapezoidal corner stitching.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
17	João Paulo Teixeira 0001, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo	A strategy for testability enhancement at layout level.	EURO-DAC	1990	DBLP DOI BibTeX RDF
17	Shao-Jun Wei, Jacques Leroy, Raymond Crappe	An efficient two-dimensional compaction algorithm for VLSI symbolic layout.	EURO-DAC	1990	DBLP DOI BibTeX RDF
17	H. Cai, Stefaan Note, Paul Six, Hugo De Man	A Data Path Layout Assembler for High Performance DSP Circuits.	DAC	1990	DBLP DOI BibTeX RDF
17	Akira Onozawa	Layout Compaction with Attractive and Repulsive Constraints.	DAC	1990	DBLP DOI BibTeX RDF
17	Ramin Hojati	Layout Optimization by Pattern Modification.	DAC	1990	DBLP DOI BibTeX RDF
17	Uminder Singh, C. Y. Roger Chen	A Transistor Reordering Technique for Gate Matrix Layout.	DAC	1990	DBLP DOI BibTeX RDF
17	Masayuki Terai, Kazuhiro Takahashi, Koji Sato	A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint.	DAC	1990	DBLP DOI BibTeX RDF
17	Shuo Huang, Omar Wing	Improved gate matrix layout.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
17	A. McBrien, J. Madden, Nigel Shadbolt	Artificial intelligence methods in process plant layout.	IEA/AIE (1)	1989	DBLP DOI BibTeX RDF
17	Bryan Preas, Massoud Pedram, Don Curry	Automatic Layout of Silicon-on-Silicon Hybrid Packages.	DAC	1989	DBLP DOI BibTeX RDF
17	R. F. Milsom, K. J. Scott, S. G. Clark, J. C. McEntegart, S. Ahmed, F. N. Soper	FACET: A CAE System for RF Analogue Simulation Including Layout.	DAC	1989	DBLP DOI BibTeX RDF
17	K. Lee, Andrew R. Neureuther	SIMPL-2: (SIMulated Profiles from the Layout-Version 2).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
17	Edmund M. Clarke, Yulin Feng	Escher-a geometrical layout system for recursively defined circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
17	Richard Barth, Louis Monier, Bertrand Serlet	Patchwork: Layout from Schematic Annotations.	DAC	1988	DBLP BibTeX RDF