Search results for "memories"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Chanik Park, Jeong-Uk Kang, Seon-Yeong Park, Jinsoo Kim 0001	Energy-aware demand paging on NAND flash-based embedded storages.	ISLPED	2004	DBLP DOI BibTeX RDF	embedded storages, page replacemen, embedded systems, virtual memory, NAND flash memory, demand paging
12	Humberto Sossa, Ricardo Barrón, José Luis Oropeza Rodríguez, Cortes Cortes	Associative Memory Based Real-Valued Pattern Recall.	ENC	2004	DBLP DOI BibTeX RDF
12	Mika Laiho, Ari Paasio, Kari Halonen	Improved cell core for a mixed-mode polynomial CNN.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
12	Marcelo Trierveiler Pereira, Antônio Augusto Fröhlich, Hugo Marcondes	RIFFS: Reverse Indirect Flash File System.	EUC	2004	DBLP DOI BibTeX RDF	embedded systems, Operating systems, file systems, flash memory
12	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri	March iC-: An Improved Version of March C- for ADOFs Detection.	VTS	2004	DBLP DOI BibTeX RDF
12	Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk	Memory BIST Using ESP.	VTS	2004	DBLP DOI BibTeX RDF
12	Jitendra Khare	Memory Yield Improvement - SoC Design Perspective.	ITC	2004	DBLP DOI BibTeX RDF
12	Mikael Olausson, Anders Edman, Dake Liu	Bit Memory Instructions for a General CPU.	IWSOC	2004	DBLP DOI BibTeX RDF
12	Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.	DAC	2004	DBLP DOI BibTeX RDF	data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC
12	Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias	An integrated hardware/software approach for run-time scratchpad management.	DAC	2004	DBLP DOI BibTeX RDF	AMBA AHB, scratchpad, DMA, dynamic allocation
12	Zygmunt Vetulani	Dialogue Processing Memory for Incident Solving in Man-Machine Dialogue.	IMTCI	2004	DBLP DOI BibTeX RDF
12	Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li 0001, Cheng-Wen Wu	Built-in redundancy analysis for memory yield improvement.	IEEE Trans. Reliab.	2003	DBLP DOI BibTeX RDF
12	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	fault injection, single event upsets, dependability evaluation
12	Enoch Peserico	Online paging with arbitrary associativity.	SODA	2003	DBLP BibTeX RDF
12	James Bergin, Dan Bernhardt	Learning from Average Experience.	IDEAL	2003	DBLP DOI BibTeX RDF
12	Cédric Bastoul, Paul Feautrier	Improving Data Locality by Chunking.	CC	2003	DBLP DOI BibTeX RDF
12	Manish Verma, Lars Wehmeyer, Peter Marwedel	Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems.	PACS	2003	DBLP DOI BibTeX RDF
12	Anton Selikhov, Cécile Germain	CMDE: A Channel Memory Based Dynamic Environment for Fault-Tolerant Message Passing Based on MPICH-V Architecture.	PaCT	2003	DBLP DOI BibTeX RDF
12	Michael Nicolaidis, Nadir Achouri, Slimane Boutobza	Dynamic Data-bit Memory Built-In Self- Repair.	ICCAD	2003	DBLP DOI BibTeX RDF
12	Timothy P. McNamara	How Are the Locations of Objects in the Environment Represented in Memory?	Spatial Cognition	2003	DBLP DOI BibTeX RDF
12	Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta 0001, Alexandru Nicolau	Interface Synthesis using Memory Mapping for an FPGA Platform.	ICCD	2003	DBLP DOI BibTeX RDF
12	Michael Nicolaidis, Nadir Achouri, Lorena Anghel	A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.	DFT	2003	DBLP DOI BibTeX RDF
12	Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott	An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.	DFT	2003	DBLP DOI BibTeX RDF
12	Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang	An Access Timing Measurement Unit of Embedded Memory.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
12	Preeti Ranjan Panda, Lakshmikantam Chitturi	An energy-conscious algorithm for memory port allocation.	ICCAD	2002	DBLP DOI BibTeX RDF
12	Isabelle Puaut, David Decotigny	Low-Complexity Algorithms for Static Cache Locking in Multitasking Hard Real-Time Systems.	RTSS	2002	DBLP DOI BibTeX RDF
12	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Analysis of SEU Effects in a Pipelined Processor.	IOLTW	2002	DBLP DOI BibTeX RDF
12	A. T. Sivaram, Daniel Fan, A. Yiin	Efficient Embedded Memory Testing with APG.	ITC	2002	DBLP DOI BibTeX RDF
12	George Bosilca, Aurélien Bouteiller, Franck Cappello, Samir Djilali, Gilles Fedak, Cécile Germain, Thomas Hérault, Pierre Lemarinier, Oleg Lodygensky, Frédéric Magniette, Vincent Néri, Anton Selikhov	MPICH-V: toward a scalable fault tolerant MPI for volatile nodes.	SC	2002	DBLP DOI BibTeX RDF
12	Eisaku Ohbuchi, Hiroshi Unno 0004	A Real-Time Configurable Shader Based on Lookup Tables.	CW	2002	DBLP DOI BibTeX RDF
12	Chih-Hsien Hsu, Shyue-Kung Lu	Fault-tolerance design of memory systems based on DBL structures.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
12	Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap	Fault Models and Test Procedures for Flash Memory Disturbances.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	program disturbance, fault model, flash memory, test algorithms
12	Kuo-Liang Cheng, Chia-Ming Hsueh, Jing-Reng Huang, Jen-Chieh Yeh, Chih-Tsun Huang, Cheng-Wen Wu	Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
12	Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho	BIST-Based Bitfail Mapping of an Embedded DRAM.	MTDT	2001	DBLP DOI BibTeX RDF
12	Jean-Philippe Kotowicz, Xavier Briffault	Cooperation as a Communication process.	CSCWD	2001	DBLP DOI BibTeX RDF
12	Lubomir Ivanov, Ramakrishna Nunna	Modeling and verification of cache coherence protocols.	ISCAS (5)	2001	DBLP DOI BibTeX RDF
12	John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare	Enabling Embedded Memory Diagnosis via Test Response Compression.	VTS	2001	DBLP DOI BibTeX RDF	diagnosis, BIST, process monitoring, bitmap, RAM testing, memory repair
12	Sang Seok Lim, Yunheung Paek, Kyu Ho Park, Jay P. Hoeflinger	A Parallel Programming Environment for a V-Busbased PC-cluste.	CLUSTER	2001	DBLP DOI BibTeX RDF	Automatic ParallelizingCompiler, LMAD(Linear Memory Access Descriptor), parallel, MPI, PC-cluster, SPMD
12	David G. Schwartz, Dov Te'eni	Tying Knowledge to Action with kMail.	IEEE Intell. Syst.	2000	DBLP DOI BibTeX RDF
12	Joohee Kim, Marios C. Papaefthymiou	Dynamic Memory Design for Low Data-Retention Power.	PATMOS	2000	DBLP DOI BibTeX RDF
12	Cheng-Fa Tsai	Fuzzy Data Recognition by Polynomial Bidirectional Heteroassociator.	COMPSAC	2000	DBLP DOI BibTeX RDF
12	Bruce Schulman, Gerald G. Pechanek	A 90k Gate "CLB" for Parallel Distributed Computing.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
12	Krassimir Georgiev, Jerzy Wasniewski	Recursive Version of LU Decomposition.	NAA	2000	DBLP DOI BibTeX RDF	LU factorization AMS Subject Classifications: 65F05, FORTRAN 90, recursive algorithms, numerical linear algebra, 65Y10
12	Chua-Chin Wang, Cheng-Fa Tsai	A Novel Neural Architecture with High Storage Capacity.	IJCNN (5)	2000	DBLP DOI BibTeX RDF	associative memory, fuzzy neural networks
12	Melvin A. Breuer	High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability.	VTS	2000	DBLP DOI BibTeX RDF
12	Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, David A. Wood 0001	Timestamp snooping: an approach for extending SMPs.	ASPLOS	2000	DBLP DOI BibTeX RDF
12	Preeti Ranjan Panda, Nikil D. Dutt	Low-power memory mapping through reducing address bus activity.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
12	Von-Kyoung Kim, Tom Chen 0001	On comparing functional fault coverage and defect coverage for memory testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
12	Koichiro Yamauchi 0001, Nobuhiko Yamaguchi, Naohiro Ishii	Incremental learning methods with retrieving of interfered patterns.	IEEE Trans. Neural Networks	1999	DBLP DOI BibTeX RDF
12	Alfonso Renart, Néstor Parga, Edmund T. Rolls	Connected Cortial Recurrent Networks.	IWANN (1)	1999	DBLP DOI BibTeX RDF
12	Michael Nicolaidis, Yervant Zorian	Scaling Deeper to Submicron: On-Line Testing to the Rescue.	DATE	1999	DBLP DOI BibTeX RDF
12	Lilia Yerosheva, Peter M. Kogge	Prototyping Execution Models for HTMT Petaflop Machine in Java.	CANPC	1999	DBLP DOI BibTeX RDF
12	Daniel P. Van der Velde, Ad J. van de Goor	Designing a Memory Module Tester.	MTDT	1999	DBLP DOI BibTeX RDF
12	Martin Margala	Low Power SRAMs for Battery Operation.	MTDT	1999	DBLP DOI BibTeX RDF
12	Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew I. Frank, Rajeev Barua, Saman P. Amarasinghe	Parallelizing Applications into Silicon.	FCCM	1999	DBLP DOI BibTeX RDF
12	Uming Ko, Poras T. Balsara, Ashwini K. Nanda	Energy optimization of multilevel cache architectures for RISC and CISC processors.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
12	Miroslav N. Velev, Randal E. Bryant	Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation.	ACSD	1998	DBLP DOI BibTeX RDF	pipelined microprocessor verification, memory shadowing, Efficient Memory Model (EMM), circuit correspondence checking, symbolic simulation
12	Motonobu Hattori, Masafumi Hagiwara	Neural associative memory for intelligent information processing.	KES (2)	1998	DBLP DOI BibTeX RDF
12	Per Larsson-Edefors	A Miniature Serial-Data SIMD Architecture.	EUROMICRO	1998	DBLP DOI BibTeX RDF
12	Jürgen Teich, Lothar Thiele, Lee Z. Zhang	Partitioning Processor Arrays under Resource Constraints.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
12	Liuxi Yang, Josep Torrellas	Speeding up the Memory Hierarchy in Flat COMA Multiprocessors.	HPCA	1997	DBLP DOI BibTeX RDF	cache-only memory architectures, cache coherence protocols, cache hierarchies, scalable shared-memory multiprocessors
12	Fredrik Dahlgren, Anders Landin	Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors.	HPCA	1997	DBLP DOI BibTeX RDF	broken inclusion, memory pressure, replacement traffic, loose inclusion, no inclusion, shared memory, COMA
12	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Exploiting off-chip memory access modes in high-level synthesis.	ICCAD	1997	DBLP DOI BibTeX RDF	High Level Synthesis, DRAM, Memory Synthesis
12	Christine Fricker, Olivier Temam, William Jalby	Influence of Cross-Interferences on Blocked Loops: A Case Study with Matric-Vector Multiply	ACM Trans. Program. Lang. Syst.	1995	DBLP DOI BibTeX RDF	cache conflicts (interferences), data locality optimization, blocking, cache performance, numerical codes
12	Frank Mueller 0001	Compiler Support for Software-Based Cache Partitioning.	Workshop on Languages, Compilers, & Tools for Real-Time Systems	1995	DBLP DOI BibTeX RDF
12	Ilkka Tuomi	Abstraction and history-from institutional amnesia to organizational memory.	HICSS (4)	1995	DBLP DOI BibTeX RDF	institutional memory, consensual cognitive abstractions, support system implementations, generic design processes, product concept specification, information systems, information systems, organizational learning, learning systems, organizational memory, strategic planning, strategic planning, cognitive systems
12	Bruce F. Cockburn	Tutorial on semiconductor memory testing.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Design for testability, fault models, functional test, memory testing, memory design
12	Michael Wu 0003, Willy Zwaenepoel	eNVy: A Non-Volatile, Main Memory Storage System.	ASPLOS	1994	DBLP DOI BibTeX RDF
12	Sundarar Mohan, Pinaki Mazumder	Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian	A Method for Consistent Fault Coverage Reporting.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Michihiro Inoue, Toshio Yamada, Atsushi Fujiwara	A New Testing Acceleration Chip for Low-Cost Memory Tests.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Hiroshi Miyano	A Method to Estimate the Number of Ciphertext Pairs for Differential Cryptanalysis.	ASIACRYPT	1991	DBLP DOI BibTeX RDF
12	Janusz A. Brzozowski, Bruce F. Cockburn	Detection of coupling faults in RAMs.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	toggling faults, fault modeling, coupling faults, RAM testing, optimal tests
12	Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal	Serial Interfacing for Embedded-Memory Testing.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
12	Tsang-Ling Sheu, Yuan-Bao Shieh, Woei Lin	The selection of optimal cache lines for microprocessor-based controllers.	MICRO	1990	DBLP BibTeX RDF
12	Tae Nam Ahn, Kohichi Sakaniwa, T. R. N. Rao	A Construction Method for m-ary Unidirectional Error Control Codes.	AAECC	1990	DBLP DOI BibTeX RDF
12	M. Morioka	S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP.	ISCA	1989	DBLP DOI BibTeX RDF	Prolog
12	Andrew Birrell, Michael B. Jones, Edward Wobber	A Simple and Efficient Implementation for Small Databases.	SOSP	1987	DBLP DOI BibTeX RDF
12	Linda Turpin	Motivation for and current work on copaging cache (abstract only).	ACM Conference on Computer Science	1985	DBLP DOI BibTeX RDF
12	Trevor N. Mudge, B. A. Makrucki	Probabilistic analysis of a crossbar switch.	ISCA	1982	DBLP BibTeX RDF
12	Roberto Bisiani	The Harpy Machine: A Data Structure-Oriented Architecture.	Computer Architecture for Non-Numeric Processing	1980	DBLP DOI BibTeX RDF	HARPY
12	Murray Edelberg, L. Robert Schissler	Intelligent memory.	AFIPS National Computer Conference	1976	DBLP DOI BibTeX RDF
12	I. V. Vel'bitskiy	Metalanguage for formal definition of semantics of programming languages.	Methods of Algorithmic Language Implementation	1975	DBLP DOI BibTeX RDF
12	Jack I. Raffel, Allan H. Anderson, Thomas S. Crowther, Terry O. Herndon, Charles E. Woodward	A progress report on large capacity magnetic film memory development.	AFIPS Spring Joint Computing Conference	1968	DBLP DOI BibTeX RDF
10	Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits	FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture.	IEEE Access	2024	DBLP DOI BibTeX RDF
10	Andrea Sánchez-Corzo, David M. Baum, Martín Irani, Svenja Hinrichs, Renate Reisenegger, Grace A Whitaker, Jan Born, Ranganatha Sitaram, Jens G. Klinzing	Odor cueing of declarative memories during sleep enhances coordinated spindles and slow oscillations.	NeuroImage	2024	DBLP DOI BibTeX RDF
10	Riccardo Vignali, Riccardo Zurla, Marco Pasotti, Pier Luigi Rolandi, Abhairaj Singh, Manuel Le Gallo, Abu Sebastian, Taekwang Jang, Alessio Antolini, Eleonora Franchi Scarselli, Alessandro Cabrini	Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
10	Lan Wen, Chong Kim Ong	Study of Short-Term and Long-Term Memories by Hodgkin-Huxley Memristor.	Int. J. Bifurc. Chaos	2024	DBLP DOI BibTeX RDF
10	Jim Handy, Tom Coughlin 0001	How Emerging Memories Extend Battery Life.	Computer	2024	DBLP DOI BibTeX RDF
10	Zhe Wang, Yan Liu, Jiuren Zhou, Genquan Han	Double-gated ferroelectric-gate field-effect-transistor for multi-bit content-addressable memories.	Microelectron. J.	2024	DBLP DOI BibTeX RDF
10	Taixin Li, Boran Sun, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Liang Shi, Tianyi Wang, Yao Yu, Thomas Kämpfe, Kai Ni 0004, Huazhong Yang, Xueqing Li	ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories.	ACM Trans. Design Autom. Electr. Syst.	2024	DBLP DOI BibTeX RDF
10	Michele Resta, Davide Bacciu	Self-generated Replay Memories for Continual Neural Machine Translation.	CoRR	2024	DBLP DOI BibTeX RDF
10	M. Carmen Aguilera-Morillo, Ana M. Aguilera, Francisco Jiménez-Molinos, Juan Bautista Roldán	Stochastic modeling of Random Access Memories reset transitions.	CoRR	2024	DBLP DOI BibTeX RDF
10	Zihan Qiu, Zeyu Huang, Youcheng Huang, Jie Fu	Empirical Study on Updating Key-Value Memories in Transformer Feed-forward Layers.	CoRR	2024	DBLP DOI BibTeX RDF
10	Siri Narla, Piyush Kumar, Mohammad Adnaan, Azad Naeemi	Cross-layer Modeling and Design of Content Addressable Memories in Advanced Technology Nodes for Similarity Search.	CoRR	2024	DBLP DOI BibTeX RDF
10	Jie Liu, Xuequn Shang, Xiaolin Han, Wentao Zhang, Hongzhi Yin	Spatial-temporal Memories Enhanced Graph Autoencoder for Anomaly Detection in Dynamic Graphs.	CoRR	2024	DBLP DOI BibTeX RDF
10	Tommaso Salvatori, Beren Millidge, Yuhang Song 0001, Rafal Bogacz, Thomas Lukasiewicz	Associative Memories in the Feature Space.	CoRR	2024	DBLP DOI BibTeX RDF
10	Vivien Cabannes, Berfin Simsek, Alberto Bietti	Learning Associative Memories with Gradient Descent.	CoRR	2024	DBLP DOI BibTeX RDF
10	Roy Barzel, Mustafa Gündogan, Markus Krutzik, Dennis Rätzel, Claus Lämmerzahl	Entanglement dynamics of photon pairs and quantum memories in the gravitational field of the earth.	Quantum	2024	DBLP DOI BibTeX RDF
10	Benedikt Bünz, Jessica Chen	Proofs for Deep Thought: Accumulation for large memories and deterministic computations.	IACR Cryptol. ePrint Arch.	2024	DBLP BibTeX RDF