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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1160 occurrences of 532 keywords
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Results
Found 1093 publication records. Showing 1093 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
8 | Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang |
An automated design flow for 3D microarchitecture evaluation. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | José Manuel Colmenar, Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo, Guadalupe Miñana, Sonia López |
Sim-async: An Architectural Simulator for Asynchronous Processor Modeling Using Distribution Functions. |
Euro-Par |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Jonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat |
Modeling Instruction-Level Parallelism for WCET Evaluation. |
RTCSA |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Lih Wen Koh, Oliver Diessel |
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-Heng Kang, Tien-Fu Chen, Jiun-In Guo |
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications. |
ICME |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose |
Selective writeback: exploiting transient values for energy-efficiency and performance. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
energy-efficiency, register files |
8 | Hui Zeng, Kanad Ghose |
Register file caching for energy efficiency. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
register caching, energy-efficiency, register files |
8 | Hiroshi Sasaki 0001, Masaaki Kondo, Hiroshi Nakamura |
Energy-efficient dynamic instruction scheduling logic through instruction grouping. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
instruction grouping, issue queue, dynamic instruction scheduling |
8 | Elham Safi, Andreas Moshovos, Andreas G. Veneris |
L-CBF: a low-power, fast counting bloom filter architecture. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
counting bloom filters, energy per operation, delay, processors |
8 | Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick |
The potential of the cell processor for scientific computing. |
Conf. Computing Frontiers |
2006 |
DBLP DOI BibTeX RDF |
GEMM, SpMV, three level memory, FFT, sparse matrix, cell processor, stencil |
8 | Maurício L. Pilla, Bruce R. Childers, Amarildo T. da Costa, Felipe M. G. França, Philippe Olivier Alexandre Navaux |
A Speculative Trace Reuse Architecture with Reduced Hardware Requirements. |
SBAC-PAD |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Nasreddine Hireche, J. M. Pierre Langlois, Gabriela Nicolescu |
Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research. |
CCECE |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Aneesh Aggarwal |
Address-Value Decoupling for Early Register Deallocation. |
ICPP |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Akira Nishida, Hisashi Kotakemori, Tamito Kajiyama, Akira Nukada |
Poster reception - Scalable software infrastructure project. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Christophe Lemuet, Jack Sampson, Jean-Francois Collard, Norman P. Jouppi |
Architecture - The potential energy efficiency of vector acceleration. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Alice E. Koniges, William Gropp, Ewing L. Lusk, David C. Eder |
M01 - Application supercomputing and multiscale simulation techniques. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Pieter Bellens, Josep M. Pérez, Rosa M. Badia, Jesús Labarta |
Memory - CellSs: a programming model for the cell BE architecture. |
SC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Chester Rebeiro, A. David Selvakumar, A. S. L. Devi |
Bitslice Implementation of AES. |
CANS |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Kaiyu Chen, Sharad Malik |
Dependable Multithreaded Processing Using Runtime Validation. |
PRDC |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Wei Liu 0014, James Tuck 0001, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas |
POSH: a TLS compiler that exploits program structure. |
PPoPP |
2006 |
DBLP DOI BibTeX RDF |
TLS compiler, profiling, prefetching, thread-level speculation, multi-core architecture |
8 | Stefan Tillich, Johann Großschädl |
Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. |
CHES |
2006 |
DBLP DOI BibTeX RDF |
embedded RISC processor, SPARC V8 architecture, Advanced Encryption Standard, instruction set extensions, efficient implementation |
8 | Steven Swanson, Andrew Putnam, Martha Mercaldi, Ken Michelson, Andrew Petersen 0001, Andrew Schwerin, Mark Oskin, Susan J. Eggers |
Area-Performance Trade-offs in Tiled Dataflow Architectures. |
ISCA |
2006 |
DBLP DOI BibTeX RDF |
WaveScalar, ASIC, RTL, Dataflow computing |
8 | Gihan R. Mudalige, Stephen A. Jarvis, Daniel P. Spooner, Graham R. Nudd |
Predictive Performance Analysis of a Parallel Pipelined Synchronous Wavefront Application for Commodity Processor Cluster Systems. |
CLUSTER |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Alex Pajuelo, Antonio González 0001, Mateo Valero |
Speculative execution for hiding memory latency. |
SIGARCH Comput. Archit. News |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff |
The CSI multimedia architecture. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Emil Talpes, Diana Marculescu |
Toward a multiple clock/voltage island design style for power-aware processors. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Sid Ahmed Ali Touati |
Register Saturation in Instruction Level Parallelism. |
Int. J. Parallel Program. |
2005 |
DBLP DOI BibTeX RDF |
Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure |
8 | Aneesh Aggarwal, Manoj Franklin |
Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
instruction replication, interconnection latency, load balancing, task assignment, Clustered processors |
8 | Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio González 0001, José Duato |
On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures. |
IEEE Trans. Parallel Distributed Syst. |
2005 |
DBLP DOI BibTeX RDF |
intercluster communication, instruction steering, complexity, on-chip interconnects, Clustered microarchitecture |
8 | Andrea Di Blas, David M. Dahle, Mark Diekhans, Leslie Grate, Jeffrey D. Hirschberg, Kevin Karplus, Hansjörg Keller, Mark Kendrick, Francisco J. Mesa-Martinez, David Pease, Eric Rice, Angela Schultz, Don Speck, Richard Hughey |
The UCSC Kestrel Parallel Processor. |
IEEE Trans. Parallel Distributed Syst. |
2005 |
DBLP DOI BibTeX RDF |
VLSI system design, image processing, Parallel processing, high performance computing, computer architecture, systolic array, SIMD, DNA, computational chemistry, biological sequence analysis |
8 | Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal |
Scalar Operand Networks. |
IEEE Trans. Parallel Distributed Syst. |
2005 |
DBLP DOI BibTeX RDF |
microprocessors, distributed architectures, Interconnection architectures |
8 | Victor V. Toporkov, Anna S. Toporkova |
Measuring the Execution Time of Fragmented Programs. |
Program. Comput. Softw. |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Jason T. Higgins, Mark D. Aagaard |
Simplifying the design and automating the verification of pipelines with structural hazards. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
formal design verification, design automation, Pipelined circuits |
8 | Ruby B. Lee, A. Murat Fiskiran |
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
multimedia, processor architecture, instruction set architecture, media processing, ISA |
8 | Won So, Alexander G. Dean |
Complementing software pipelining with software thread integration. |
LCTES |
2005 |
DBLP DOI BibTeX RDF |
TI C6000, DSP, software pipelining, VLIW, stream programming, coarse-grain parallelism, software thread integration |
8 | Wolfram Kahl, Christopher Kumar Anand, Jacques Carette |
Control-Flow Semantics for Assembly-Level Data-Flow Graphs. |
RelMiCS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Ben Wun, Jeremy Buhler, Patrick Crowley |
Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor. |
IEEE PACT |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Huiyang Zhou |
Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window. |
IEEE PACT |
2005 |
DBLP DOI BibTeX RDF |
|
8 | John D. Davis, James Laudon, Kunle Olukotun |
Maximizing CMP Throughput with Mediocre Cores. |
IEEE PACT |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Gokhan Memik, Masud H. Chowdhury, Arindam Mallik, Yehea I. Ismail |
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files. |
DSN |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers |
SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors. |
DSN |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Lucanus J. Simonson, Lei He 0001 |
Micro-architecture Performance Estimation by Formula. |
SAMOS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Shadi T. Khasawneh, Kanad Ghose |
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto 0001, Michael C. Huang 0001, Francisco Tirado |
A Power-Efficient and Scalable Load-Store Queue Design. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk 0001 |
Increasing Register File Immunity to Transient Errors. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Sam S. Stone, Kevin M. Woley, Matthew I. Frank |
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding. |
MICRO |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Masaaki Kondo, Hiroshi Nakamura |
A Small, Fast and Low-Power Register File by Bit-Partitioning. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Timothy M. Jones 0001, Michael F. P. O'Boyle, Jaume Abella 0001, Antonio González 0001 |
Software Directed Issue Queue Power Reduction. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Won Woo Ro, Jean-Luc Gaudiot |
A Low-Complexity Issue Queue Design with Speculative Pre-execution. |
HiPC |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Richard W. Vuduc, Hyun Jin Moon |
Fast Sparse Matrix-Vector Multiplication by Exploiting Variable Block Structure. |
HPCC |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Erich Strohmaier, Hongzhang Shan |
Apex-Map: A Synthetic Scalable Benchmark Probe to Explore Data Access Performance on Highly Parallel Systems. |
Euro-Par |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Joseph J. Sharkey, Dmitry V. Ponomarev |
Non-uniform Instruction Scheduling. |
Euro-Par |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Hongkyu Kim, D. Scott Wills, Linda M. Wills |
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Satish Narayanasamy, Hong Wang 0003, Perry H. Wang, John Paul Shen, Brad Calder |
A Dependency Chain Clustered Microarchitecture. |
IPDPS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Reza Azimi, Michael Stumm, Robert W. Wisniewski |
Online performance analysis by statistical sampling of microprocessor performance counters. |
ICS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Jose Renau, Karin Strauss, Luis Ceze, Wei Liu 0014, Smruti R. Sarangi, James Tuck 0001, Josep Torrellas |
Thread-Level Speculation on a CMP can be energy efficient. |
ICS |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Nithin Nakka, Giacinto Paolo Saggese, Zbigniew Kalbarczyk, Ravishankar K. Iyer |
An Architectural Framework for Detecting Process Hangs/Crashes. |
EDCC |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Jongmyon Kim, D. Scott Wills, Linda M. Wills |
Architectural Enhancements for Color Image and Video Processing on Embedded Systems. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Weng-Fai Wong |
Targeted Data Prefetching. |
Asia-Pacific Computer Systems Architecture Conference |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Sadaf R. Alam, Jeffrey S. Vetter |
Performance and Scalability Analysis of Cray X1 Vectorization and Multistreaming Optimization. |
International Conference on Computational Science (1) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin |
Instruction packing: reducing power and delay of the dynamic scheduling logic. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
instruction packing, low power, issue queue |
8 | William Lloyd Bircher, M. Valluri, J. Law, Lizy K. John |
Runtime identification of microprocessor energy saving opportunities. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
speculative microprocessors, modeling, energy efficiency, power |
8 | Ahmad Zmily, Christos Kozyrakis |
Energy-efficient and high-performance instruction fetch using a block-aware ISA. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
basic blocks, energy efficiency, instruction set architecture, decoupled architecture, instruction delivery |
8 | Joseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin |
Power-Efficient Wakeup Tag Broadcast. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio González 0001 |
Memory Bank Predictors. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Won-Ho Park, Andreas Moshovos, Babak Falsafi |
RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches "for Free". |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
8 | A. Murat Fiskiran, Ruby B. Lee |
On-Chip Lookup Tables for Fast Symmetric-Key Encryption. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Junwei Zhou, Andrew J. Mason |
Increasing design space of the instruction queue with tag coding. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
instruction queue, wakeup/select loop |
8 | Gokhan Memik, Mahmut T. Kandemir, Arindam Mallik |
Load elimination for low-power embedded processors. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
load elimination technique, low power design |
8 | José R. Herrero 0001, Juan J. Navarro |
Efficient Implementation of Nearest Neighbor Classification. |
CORES |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Tatiana Gadelha Serra dos Santos, Sergio Bampi, Philippe Olivier Alexandre Navaux |
Reusing Traces in a Dynamic Conditional Execution Architecture. |
SBAC-PAD |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Guilherme Dal Pizzol, Philippe Olivier Alexandre Navaux |
Branch Prediction Topologies for SMT Architectures. |
SBAC-PAD |
2005 |
DBLP DOI BibTeX RDF |
|
8 | A. Murat Fiskiran, Ruby B. Lee |
Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography. |
ITCC (1) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Julian Borrill, Jonathan Carter, Leonid Oliker, David Skinner, Rupak Biswas |
Integrated Performance Monitoring of a Cosmology Application on Leading HEC Platforms. |
ICPP |
2005 |
DBLP DOI BibTeX RDF |
Cosmic Microwave Background, MADCAP, Altix Columbia, Earth Simulator, X1 Phoenix, Power3 Seaborg, parallel performance characterization |
8 | Ethan Schuchman, T. N. Vijaykumar |
Rescue: A Microarchitecture for Testability and Defect Tolerance. |
ISCA |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Mladen Berekovic, Sören Moch, Peter Pirsch |
A scalable, clustered SMT processor for digital signal processing. |
SIGARCH Comput. Archit. News |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Faraydon Karim, Alain Mellan, Anh Nguyen, Utku Aydonat, Tarek S. Abdelrahman |
A Multilevel Computing Architecture for Embedded Multimedia Applications. |
IEEE Micro |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Yu Bai 0001, R. Iris Bahar |
A low-power in-order/out-of-order issue queue. |
ACM Trans. Archit. Code Optim. |
2004 |
DBLP DOI BibTeX RDF |
instruction issue logic, low power, High-performance |
8 | Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding 0001, David H. Albonesi |
The Energy Impact of Aggressive Loop Fusion. |
IEEE PACT |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Alex Settle, Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors |
Architectural Support for Enhanced SMT Job Scheduling. |
IEEE PACT |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Jens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider 0003, Tim Niggemeier |
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Nirav Dave |
Designing a reorder buffer in Bluespec. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Muhamed F. Mudawar |
Scalable cache memory design for large-scale SMT architectures. |
WMPI |
2004 |
DBLP DOI BibTeX RDF |
scalable multiported cache memory, simultaneous multithreaded architectures |
8 | Giovanni Agosta, Gianluca Palermo, Cristina Silvano |
Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems. |
SAC |
2004 |
DBLP DOI BibTeX RDF |
hardware/software co-exploration, embedded systems, low-power design, source code transformations |
8 | Vinod Viswanath |
Multi-log Processor - Towards Scalable Event-Driven Multiprocessors. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Soyeb Alli, Chris Bailey 0002 |
Compiler-Directed Dynamic Memory Disambiguation for Loop Structures. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Francisco J. Cazorla, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández, Alex Ramírez, Mateo Valero |
Implicit vs. Explicit Resource Allocation in SMT Processors. |
DSD |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry V. Ponomarev |
Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure. |
MICRO |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Michael Dupré, Nathalie Drach, Olivier Temam |
VHC: Quickly Building an Optimizer for Complex Embedded Architectures. |
CGO |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Jonathan Carter, Julian Borrill, Leonid Oliker |
Performance Characteristics of a Cosmology Package on Leading HPC Architectures. |
HiPC |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Miroslav N. Velev |
Using positive equality to prove liveness for pipelined microprocessors. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
8 | G. Surendra, Subhasis Banerjee, S. K. Nandy 0001 |
Power-performance trade-off using pipeline delays. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Venkata Syam P. Rapaka, Emil Talpes, Diana Marculescu |
Mixed-clock issue queue design for energy aware, high-performance cores. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose, Oguz Ergin |
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization. |
PACS |
2004 |
DBLP DOI BibTeX RDF |
|
8 | André L. Sandri, Ronaldo Augusto Lara Gonçalves, João Angelo Martini |
SMS - Tool for Development and Performance Analysis of Parallel Applications. |
Annual Simulation Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Peng-fei Chuang, Resit Sendag, David J. Lilja |
Improving Data Cache Performance via Address Correlation: An Upper Bound Study. |
Euro-Par |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Adrián Cristal, Oliverio J. Santana, Mateo Valero |
Maintaining Thousands of In-flight Instructions. |
Euro-Par |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Jamison D. Collins, Dean M. Tullsen |
Clustered Multithreaded Architectures - Pursuing both IPC and Cycle Time. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Adronis Niyonkuru, Hans Christoph Zeidler |
Designing a Runtime Reconfigurable Processor for General Purpose Applications. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Dongsoo Kang, Jean-Luc Gaudiot |
Speculation Control for Simultaneous Multithreading. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
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