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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 10061 occurrences of 3641 keywords
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Results
Found 17347 publication records. Showing 17347 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Steven E. Raasch, Nathan L. Binkert, Steven K. Reinhardt |
A Scalable Instruction Queue Design Using Dependence Chains. |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
Instruction Queue, Dependence Chains, Variable-latency, Scheduling, Scalable, Segment |
14 | Ludek Kucera |
Wait-Free Deflection Routing of Long Messages. |
IEEE Trans. Parallel Distributed Syst. |
2001 |
DBLP DOI BibTeX RDF |
throughput, latency, contention, Deflection routing, fully adaptive routing |
14 | James R. Anderson 0001, Seth Abraham |
Performance-Based Constraints for Multidimensional Networks. |
IEEE Trans. Parallel Distributed Syst. |
2000 |
DBLP DOI BibTeX RDF |
multidimensional network, $k$-ary $n$-cube, direct-connected, queue waiting time, unity queue waiting time, performance analysis, Interconnection networks, message latency, maximum throughput |
14 | Reinhard von Hanxleden, Ken Kennedy |
A balanced code placement framework. |
ACM Trans. Program. Lang. Syst. |
2000 |
DBLP DOI BibTeX RDF |
Tarjan intervals, data-flow analysis, high performance Fortran, latency hiding, partial redundancy elimination, Fortran D |
14 | Thilo Kielmann, Henri E. Bal, Sergei Gorlatch |
Bandwidth-Efficient Collective Communication for Clustered Wide Area Systems. |
IPDPS |
2000 |
DBLP DOI BibTeX RDF |
Models for Parallel Computers, Optimization, Grid Computing, Interconnection Networks, MPI, Performance Modeling, Cluster Computing, Runtime Support, Latency Tolerance |
14 | Anders Wall, Kristian Sandström, Jukka Mäki-Turja, Christer Norström, Wang Yi 0001 |
Verifying temporal constraints on data in multi-rate transactions using timed automata. |
RTCSA |
2000 |
DBLP DOI BibTeX RDF |
temporal constraint verification, multi-rate transactions, nonpreemptive execution order, scheduling, real-time systems, real-time systems, program verification, transaction processing, computational models, timed automata, data dependencies, schedulability analysis, reachability analysis, reachability analysis, automata theory, end-to-end latency |
14 | Dong-Hwan Park, Soon-Ju Kang |
IEEE1394 OHCI device driver architecture for guarantee real-time requirement. |
RTCSA |
2000 |
DBLP DOI BibTeX RDF |
IEEE1394 OHCI device driver architecture, guaranteed real time requirement, priority based packet queueing, interrupt latency time, ISR, Interrupt Service Routine, device driver level support, real time characteristics, high priority applications, digital multimedia services, hard real time instrumentation, control applications, real-time systems, queueing theory, packet switching, interrupts, client-server systems, home networks, device drivers, QoS guarantees, real time requirements, real time middleware |
14 | Steven J. Ross, Jason L. Hill, Michael Y. Chen, Anthony D. Joseph, David E. Culler, Eric A. Brewer |
A Composable Framework for Secure Multi-Modal Access to Internet Services from Post-PC Devices. |
WMCSA |
2000 |
DBLP DOI BibTeX RDF |
secure multi-modal access, post-PC devices, public kiosks, cellular telephones, voice based vehicle telematics, infrastructure-based secure proxy architecture, security transformation functions, generic content, service-specific rules, untrusted public Internet access points, proxy transformations, unoptimized Java implementation, Internet, mobile computing, mobile devices, PDAs, latency, security of data, information access, information resources, telecommunication security, Internet services, reusable components |
14 | Yuan Gao, Ye Ge, Jennifer C. Hou |
RMCM: Reliable Multicasts for Core-based Multicast Trees. |
ICNP |
2000 |
DBLP DOI BibTeX RDF |
core-based multicast trees, RMCM, multicast applications, on-tree router, core-based tree, retransmission request, optimal recovery, turning point approach, IP options, group membership changes, repliers, delayed ACK approach, repair-based reliable multicast, NAK implosion control, recovery latency, recovery isolation, FreeBSD 2.2.8, Internet, Internet, transport protocols, packet switching, network topology, digital simulation, trees (mathematics), telecommunication network routing, multicast communication, reliable multicasts, event-driven simulation, topology changes, local recovery, data packets, hosts |
14 | Suchitra Raman, Hari Balakrishnan, Murari Srinivasan |
An Image Transport Protocol for the Internet. |
ICNP |
2000 |
DBLP DOI BibTeX RDF |
image transport protocol, Web downloads, in-order byte-stream abstraction, loss-prone congested networks, user-perceived latency, application level framing, out-of-order application data unit, receiver-driven selective reliability, image formats, receiver post-processing algorithms, Internet, Internet, image processing, image processing, wireless networks, transport protocols, image quality, JPEG, JPEG2000, visual communication, UDP, error concealment, PSNR, receiver, network congestion, image transmission, image data, peak signal-to-noise ratio, image rendering, reconstructed images, congestion manager, interactive performance |
14 | Wen-Tsong Shiue |
High Level Synthesis for Peak Power Minimization Using ILP. |
ASAP |
2000 |
DBLP DOI BibTeX RDF |
Peak power minimization, latency-constrained scheduling, High-level synthesis, low power design, integer linear programming, force-directed scheduling |
14 | Douglas H. Summerville, Lynwald Edmunds |
An Analysis of Resource Scheduling with Prioritization for QoS in LANs. |
LCN |
2000 |
DBLP DOI BibTeX RDF |
switch organizations, high-speed local networks, router solutions, resource prioritization, CBR traffic, simulation, scheduling, quality of service, QoS, quality of service, local area networks, latency, bandwidth, jitter, telecommunication network routing, telecommunication traffic, resource reservation, LAN, resource scheduling, communication performance, VBR traffic |
14 | Roger Espasa, Mateo Valero |
A Simulation Study of Decoupled Vector Architectures. |
J. Supercomput. |
1999 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, decoupling, memory latency, vector architectures |
14 | Mohamed Ould-Khaoua |
A Performance Model for Duato's Fully Adaptive Routing Algorithm in k-Ary n-Cubes. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
interconnection networks, performance modeling, adaptive routing, Multicomputers, virtual channels, deterministic routing, message latency |
14 | Greg Welch, Gary Bishop, Leandra Vicci, Stephen Brumback, Kurtis Keller, D'nardo Colucci |
The HiBall Tracker: high-performance wide-area tracking for virtual and augmented environments. |
VRST |
1999 |
DBLP DOI BibTeX RDF |
virtual enviroments, tracking, delay, Kalman filter, latency, calibration, sensor fusion, autocalibration, optical sensor |
14 | Nosa Omoigui, Liwei He, Anoop Gupta, Jonathan Grudin, Elizabeth Sanocki |
Time-Compression: Systems Concerns, Usage, and Benefits. |
CHI |
1999 |
DBLP DOI BibTeX RDF |
compression granularity, compression rate, multimedia, latency, video browsing, time-compression |
14 | Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith 0001 |
Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications. |
ACM Trans. Comput. Syst. |
1998 |
DBLP DOI BibTeX RDF |
cache miss notification, processor architecture, memory latency |
14 | Gary S. Tyson, Todd M. Austin |
Improving the Accuracy and Performance of Memory Communication Through Renaming. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
data fetching, data value speculation, heap segment, instruction loading, memory access latency, memory communication, memory references, memory renaming, memory segments, processor pipeline, register access techniques, stores, performance, delays, accuracy, instruction-level parallelism, execution time, storage allocation, data dependence speculation, address calculation |
14 | Graham P. Jones, Nigel P. Topham |
A Comparison of Data Prefetching on an Access Decoupled and Superscalar Machine. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
Access Decoupling, Superscalar, out of order execution, latency hiding |
14 | James E. Bennett, Michael J. Flynn |
Prediction Caches for Superscalar Processors. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
Prediction cache, Dynamic scheduling, Memory latency, Victim cache, Stream buffer |
14 | Andreas Moshovos, Gurindar S. Sohi |
Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. |
MICRO |
1997 |
DBLP DOI BibTeX RDF |
DEF-store-load-USE chains, address disambiguation, data cache access, data cache bandwidth requirements, data dependence prediction, inter-operation memory communication, memory dependences, memory hierarchy design, transient value cache, storage management, memory architecture, communication latency, instruction window, address calculation |
14 | Beng-Hong Lim, Philip Heidelberger, Pratap Pattnaik, Marc Snir |
Message Proxies for Efficient, Protected Communication on SMP Clusters. |
HPCA |
1997 |
DBLP DOI BibTeX RDF |
message proxies, protected communication, custom hardware, IBM Model G30 SMPs, cache-miss latency, cache-update mechanism, performance model, multiprocessing systems, symmetric multiprocessor clusters |
14 | Kai Hwang 0001, Choming Wang, Cho-Li Wang |
Evaluating MPI Collective Communication on the SP2, T3D, and Paragon Multicomputers. |
HPCA |
1997 |
DBLP DOI BibTeX RDF |
startup latency, aggregated bandwidth, message passing, Collective communications, multicomputers |
14 | William Perrizo, Zhili Zhang, Stephen Krebsbach |
Strategies for implementing distributed query algorithms over high-speed, bandwidth-on-demand, wide area networks. |
COMPSAC |
1997 |
DBLP DOI BibTeX RDF |
high-speed bandwidth-on-demand wide area networks, distributed query processing algorithms, latency delay reduction, multicast issue handling, transmission delay reduction, local processing delay reduction, distributed join algorithm, time cost, near optimal performance, distributed databases, analytical model, distributed database systems |
14 | Dimiter R. Avresky, Vladimir Shurbanov, Robert W. Horst, William J. Watson, L. Young, Doug Jewett |
Maximum Delivery Time and Hot Spots in ServerNet(tm) Topologies. |
IPPS |
1997 |
DBLP DOI BibTeX RDF |
ServerNet topologies, maximum two-way delivery time, congested links, tree saturation, reliability, latency, wormhole-routed, multistage interconnection networks, hot spots, performance degradation, performance characteristics |
14 | Joseph Kee-Yin Ng, Shibin Song |
A video smoothing algorithm for transmitting MPEG video over limited bandwidth. |
RTCSA |
1997 |
DBLP DOI BibTeX RDF |
video smoothing algorithm, MPEG video transmission, future computer networks, variable bit rate compressed video, multiple time scale bit rate variability, optimal video smoothing algorithm, stored MPEG-1 video stream, user defined maximum network bandwidth, startup latency, client buffer size, predefined bandwidth, B-frames, one-time playback pause, quality of service, video coding, video quality, data transmission, bursty traffic, network utilization, limited bandwidth |
14 | Kyosun Kim, Ramesh Karri, Miodrag Potkonjak |
Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
micro-preemption, multi-task VLSI system synthesis, context switch overhead, preemption latency |
14 | W. Lynn Gallagher, Chuan-lin Wu |
Evaluation of a memory hierarchy for the MTS multithreaded processor. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
memory hierarchy evaluation, MTS multithreaded processor, hardware resource utilization, instruction throughput, multithreaded superscalar processor, multiple instruction streams, multiple functional unit architecture, parameter-driven simulator, SES/workbench, numerical benchmarks, memory system configurations, main memory latency, cache hit rates, realistic multilevel cache hierarchy, parallel processing, VLIW, superscalar processor, instruction cache |
14 | Matthew Clegg, Keith Marzullo |
A low-cost processor group membership protocol for a hard real-time distributed system. |
RTSS |
1997 |
DBLP DOI BibTeX RDF |
processor group membership protocol, hard real-time distributed system, failure detection latency, processor time, bounded tax, broadcast message traffic, protocols, schedulability analysis, message complexity, shared resources, network bandwidth |
14 | Chouki Aktouf, Ghassan Al Hayek, Chantal Robach |
Concurrent testing of VLSI digital signal processors using mutation based testing. |
DFT |
1997 |
DBLP DOI BibTeX RDF |
VLSI digital signal processor, software technique, hardware device, fault latency, computation, DSP, fault coverage, Mutation testing, digital signal processing chips, concurrent testing |
14 | Valery A. Vardanian |
Exact probabilistic analysis of error detection for parity checkers. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
circuit under check, multi-output supergate, combinational CUC, restricted observability, restricted detectability, concurrent checker, latency, error detection, combinational circuits, probabilistic analysis, single stuck-at fault, parity checker |
14 | Richard Wolski |
Forecasting Network Performance to Support Dynamic Scheduling using the Network Weather Service. |
HPDC |
1997 |
DBLP DOI BibTeX RDF |
network performance forecasting, network weather service, dynamic resource performance forecasts, metacomputing environments, TCP/IP, transport protocols, latency, dynamic scheduling, quality-of-service guarantees |
14 | Gab Joong Jeong, Kyoung Hwan Kwon, Moon Key Lee, Seung Han An |
A Scalable Memory System Design. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
scalable memory system, pipeline technique, systolic data flow, sub-memory blocks, partial binary tree structure, multidirectional data flow, chip size, 4 kbit, 0.8 micron, 5.1 ns, 3.5 mm, throughput, latency, memory architecture, memory architecture, CMOS technology, communication channel, access time, operating speed, clock speed |
14 | Masaru Takesue |
A tampering protocol for reducing the coherence transactions in regular computation. |
ISPAN |
1997 |
DBLP DOI BibTeX RDF |
tampering protocol, coherence transactions, regular computation, latency of communication, protocols, multiprocessor, cache-coherence protocol, RTL simulator |
14 | Nian-Feng Tzeng, Harish Kumar |
Traffic Analysis and Simulation Performance of Incomplete Hypercubes. |
IEEE Trans. Parallel Distributed Syst. |
1996 |
DBLP DOI BibTeX RDF |
mean latency, simulation, message routing, Incomplete hypercubes, traffic density |
14 | David A. Koufaty, Xiangfeng Chen, David K. Poulsen, Josep Torrellas |
Data Forwarding in Scalable Shared-Memory Multiprocessors. |
IEEE Trans. Parallel Distributed Syst. |
1996 |
DBLP DOI BibTeX RDF |
Memory latency hiding, forwarding and prefetching, multiprocessor caches, address trace analysis, scalable shared-memory multiprocessors |
14 | Wolfgang K. Giloi, Ulrich Brüning 0001, Wolfgang Schröder-Preikschat |
MANNA: Prototype of a Distributed Memory Architecture with Maximized Sustained Performance. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
maximized sustained performance, compiler problem, innovative architectural solutions, overlapping communication, MANNA computer, benchmark performance, performance evaluation, parallel computers, operating system, parallel machines, distributed memory systems, parallelizing compilers, operating systems (computers), programmability, virtual storage, parallelising compilers, latency hiding, distributed memory parallel computer, distributed memory architecture, virtual shared memory, global address space, superscalar microprocessors |
14 | H. Bekker, E. J. Dijkstra |
Delay-Insensitive Synchronization on a Message-Passing Architecture with an Open Collector Bus. |
PDP |
1996 |
DBLP DOI BibTeX RDF |
delay-insensitive synchronization, open collector bus, high latency, constraint algorithm, SHAKE, Constraint Molecular Dynamics simulation, ring architecture, delay insensitive algorithm, performance evaluation, performance, parallel algorithms, parallel algorithms, parallel architectures, message passing, multiprocessor interconnection networks, multiprocessor interconnection networks, synchronisation, digital simulation, physics computing, system buses, communication time, message passing architecture |
14 | David A. Dunn, Wei-Chung Hsu |
Instruction Scheduling for the HP PA-8000. |
MICRO |
1996 |
DBLP DOI BibTeX RDF |
HP PA-8000, instruction polarity cache interfaces, memory dependences, production compiler, scheduling, latency, compiler optimization, instruction scheduling, resource constraints, micro-architecture |
14 | Leonidas I. Kontothanassis, Michael L. Scott |
Using Memory-Mapped Network Interfaces to Improve the Performance of Distributed Shared Memory. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
memory-mapped network interfaces, cache fills, fine-grain access faults, parallel algorithms, protocols, message passing, latency, bandwidth, shared memory systems, distributed shared memory, distributed memory systems, network interfaces, network interfaces, memory-mapped |
14 | Brad Calder, Dirk Grunwald, Joel S. Emer |
Predictive Sequential Associative Cache. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
predictive sequential associative cache, miss rate, prediction sources, storage management, memory architecture, content-addressable storage, access time, direct-mapped cache, access latency |
14 | Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh |
The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. |
HPCA |
1996 |
DBLP DOI BibTeX RDF |
shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention |
14 | Loïc Prylli, Bernard Tourancheau |
Distributed simulation of parallel computers. |
Annual Simulation Symposium |
1996 |
DBLP DOI BibTeX RDF |
MIMD computer, code recompilation, trace file, simulation hosts, application granularity, performance evaluation, parallel computers, virtual machines, local area networks, program compilers, distributed memory systems, distributed simulation, distributed simulator, workstation cluster, distributed memory parallel computers, network latency, virtual timings |
14 | Cezary Dubnicki, Liviu Iftode, Edward W. Felten, Kai Li 0001 |
Software Support for Virtual Memory-Mapped Communication. |
IPPS |
1996 |
DBLP DOI BibTeX RDF |
virtual memory-mapped communication, virtual address space, full protection, user-level buffer management, zero-copy protocols, software communication overhead, SHRIMP project, hardware performance, Pentium personal computer, user-to-user latency, peak hardware bandwidth, 23 MB/s, performance evaluation, software architecture, operating system, application program interfaces, application program interface, client-server systems, operating systems (computers), data transfer, network interfaces, network interfaces, communication model, virtual storage, microcomputers, data handling |
14 | C. S. Yang, Y. M. Tsai, Y. L. Tsai |
Adaptive routing in k-ary n-cube multicomputers. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
k-ary n-cube multicomputers, distributed memory multiprocessor systems, virtual system, network congestion delay, performance evaluation, virtual reality, throughput, hypercube networks, wormhole routing, digital simulation, adaptive routing, distributed memory systems, simulation results, network routing, buffer size, deadlock-free routing, deadlock free routing, communication latency |
14 | Vipul Gupta, Eugen Schenfeld |
Annealed Embeddings of Communication Patterns in an Interconnection Cached Network. |
IEEE Trans. Parallel Distributed Syst. |
1995 |
DBLP DOI BibTeX RDF |
Interconnection cache, switching locality, latency reduction, reconfigurable parallel architectures, interconnection networks, simulated annealing, optical networks, process mapping |
14 | Stuart M. Fairley, Ian D. Reid 0001, David William Murray 0001 |
Transfer of Fixation for an Active Stereo Platform via Affine Structure Recovery. |
ICCV |
1995 |
DBLP DOI BibTeX RDF |
fixation transfer, active stereo platform, affine structure recovery, stereo tracking, 3D affine transfer, body-centred fixation point, active camera platform, fixed latency tracking, structure calculation, approximately Euclidean frame, structure transfer, computer vision, computational geometry, convex hull, trajectories, stereo image processing, graceful degradation, robust performance |
14 | Michael F. P. O'Boyle |
A hierarchical locality algorithm for NUMA compilation. |
PDP |
1995 |
DBLP DOI BibTeX RDF |
hierarchical locality algorithm, NUMA compilation, latency overhead, parallel hierarchical memory machines, nonlocal accesses, compound sequenc, complex array accesses, general iteration spaces, strip mining, parallel machines, program compilers, storage management, distributed memory systems, memory structure, program locality, unimodular transformations, data alignment, compiler algorithm |
14 | Oum-El-Kheir Benkahla, Chouki Aktouf, Chantal Robach |
Distributed off-line testing of parallel systems. |
Asian Test Symposium |
1995 |
DBLP DOI BibTeX RDF |
distributed off-line testing, off-line testing, distributed self-diagnosis algorithms, adaptive testing assignment strategies, static testing assignment strategies, testing latency, message load, SELF3, HOST BSCT, HOST PATH, ADAPTIVE TREES, performance evaluation, parallel algorithms, fault diagnosis, adaptive systems, parallel systems, queueing network model, computer testing, automatic test software |
14 | Arindam Saha |
A simulator for real-time parallel processing architectures. |
Annual Simulation Symposium |
1995 |
DBLP DOI BibTeX RDF |
real-time parallel processing architectures, time-driven flit-based wormhole-routed parallel processor network simulator, user-friendly graphical user interface, prioritized queues, resource allocation policies, message priorities, average latency convergence, throughput monitoring, communication characteristics, performance, real-time systems, resource allocation, parallel architectures, graphical user interfaces, virtual machines, concurrency control, convergence, deadlocks, virtual channel, overlaps, real-time networks |
14 | Guillermo A. Alvarez, Marcelo O. Fernández, Ragelio A. Alvez, Sylvia Rodriguez, Julio A. Sánchez Avalos, Jorge L. C. Sanz |
Run-time support for asynchronous parallel computations. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
asynchronous parallel computations, DREAM, asynchronous multiprocessors, global distributed arrays, dynamic communication patterns, performance evaluation, scalability, parallel computations, programming environments, multiprocessing systems, network latency, run-time support, performance results, distributed programming environment |
14 | Richard M. Karp |
Modeling parallel communication. |
IPPS |
1995 |
DBLP DOI BibTeX RDF |
cost of computation, cost of communication, Valiant's BSP model, PRAM(m) model, FFT computation, tridiagonal systems, performance evaluation, performance, framework, broadcasting, sorting, shared memory systems, distributed-memory multiprocessor, communication latency, prefix summing, summing, LogP model, communication bandwidth |
14 | Jörg Ottensmeyer, Peter Martini |
Improving the demand-priority protocol. |
ICCCN |
1995 |
DBLP DOI BibTeX RDF |
demand-priority protocol, IEEE 802.12, low latency service, high-priority traffic, normal priority traffic, high priority traffic, variable bit rate high priority loads, service strategies, standardization, network topology, network topology, simulation results, medium access control protocol, interactive multimedia applications |
14 | Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai |
A prototype router for the massively parallel computer RWC-1. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
prototype router, massively parallel computer RWC-1, multi-threaded architecture, high communication performance, direct interconnection networks, small degree, operating system support features, CMOS gate array, VLSI, parallel architectures, multiprocessor interconnection networks, CMOS integrated circuits, high throughput, low latency, hardware cost, VLSI chip |
14 | Ram K. Krishnamurthy, Ramalingam Sridhar |
A CMOS wave-pipelined image processor for real-time morphology . |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity |
14 | Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito |
SSM-MP: more scalability in shared-memory multi-processor. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
SSM-MP, shared-memory multi-processor, cache refill latency, bus bottle neck problem, MTag, scalability, shared memory systems, cache coherency, memory architecture, multi-processor system |
14 | Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto |
A 13.3ns double-precision floating-point ALU and multiplier. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit |
14 | H. Dhanesha, K. Falakshahi, Mark Horowitz |
Array-of-arrays architecture for parallel floating point multiplication. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron |
14 | Thomas Scholz, Michael Schäfers 0003 |
An improved dynamic register array concept for high-performance RISC processors. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing |
14 | Sangho Ha, Sangyong Han, Heunghwan Kim |
Partitioning a lenient parallel language into sequential threads. |
HICSS (2) |
1995 |
DBLP DOI BibTeX RDF |
lenient parallel language, language partitioning, sequential threads, multithreaded architecture performance, large-scale parallel system, split-phase memory operations, fast context switching, multithreaded code quality, enhanced thread formation scheme, Id/sup -/, long latency instructions, multiple switches, generalized switch-and-merge, thread merging, redundant arc elimination, thread precedence relations, control instructions, DAVRID multithreaded architecture, simulation, graph theory, parallel architectures, graph partitioning, switching, merging, parallel languages, large-scale systems, program control structures, branch instructions |
14 | Mark J. Clement, Michael J. Quinn |
Multivariate statistical techniques for parallel performance prediction. |
HICSS (2) |
1995 |
DBLP DOI BibTeX RDF |
multivariate statistical techniques, parallel performance prediction, multicomputer efficiency, program execution time, architectural characterization, algorithmic characterization, critical model parameters, cache miss penalty, predicted execution time, standard error values, large variance values, performance evaluation, parallel processing, performance model, statistical analysis, data analysis, software performance evaluation, variance, confidence interval, random variables, message latency, multivariate data analysis, model parameters |
14 | John G. Cleary, Murray Pearson, Husam Kinawi |
The architecture of an optimistic CPU: the WarpEngine. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
optimistic CPU, WarpEngine, shared memory CPU, single instructions, memory latency tolerance, executable instructions, TimeWarp algorithm, optimistic, single linear address space, single thread of control, reliability, caches, parallel architectures, fault tolerant computing, concurrency control, synchronisation, synchronisation, shared memory systems, memory architecture, cache storage, memory system, memory model, time stamped, memory accesses, local memory |
14 | Milan M. Jovanovic, Milo Tomasevic, Veljko M. Milutinovic |
A simulation-based comparison of two reflective memory approaches. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
simulation-based comparison, reflective memory approaches, Reflective Memory/Memory Channel, RM/MC system, bus-based system architecture, update consistency mechanism, block transfers, simulation analysis, synthetic workload model, real-time response, run-time actions, compile-time actions, performance evaluation, real-time systems, virtual machines, shared memory systems, distributed memory systems, system buses, message latency, data handling, distributed shared memory systems, shared data |
14 | Geoffrey S. Hubona |
Evaluating user interface design with belief constructs. |
HICSS (4) |
1995 |
DBLP DOI BibTeX RDF |
user interface design evaluation, belief constructs, user acceptance predictors, task accuracy, task latency, user confidence, user productivity, accurate decisions, reduced decision times, user interfaces, human factors, human resource management, perceived usefulness, perceived ease of use, decision quality |
14 | V. Visvanathan, S. Ramanathan |
A modular systolic architecture for delayed least mean squares adaptive filtering. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
modular systolic architecture, delayed least mean squares adaptive filtering, coefficient adaptation, input sampling periods, output latency, convergence behavior, systolization technique, maximum sampling rate, multiply-accumulate processor modules, systolic arrays, pipeline processing, adaptive filters, convergence of numerical methods, least mean squares methods |
14 | Byoung-Joon Min, Sang-Seok Shin, Kee-Wook Rim |
Design and analysis of a multiprocessor system with extended fault tolerance. |
FTDCS |
1995 |
DBLP DOI BibTeX RDF |
extended fault tolerance, scalable multiprocessor system, tree-type interconnection networks, computational complexity, reliability, fault tolerant computing, multiprocessor interconnection networks, latency, multiprocessing systems, multiprocessor system, performance penalty, implementation complexity |
14 | David C. J. Naylor, Simon Jones 0001 |
A Performance Model for Multilayer Neural Networks in Linear Arrays. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
throughput rate, input-output bandwidth, two-hidden-layer network, performance evaluation, performance, performance model, latency, systolic arrays, multilayer perceptrons, feedforward neural nets, linear arrays, multilayer neural networks |
14 | Phillip Krueger, Niranjan G. Shivaratri |
Adaptive Location Policies for Global Scheduling. |
IEEE Trans. Software Eng. |
1994 |
DBLP DOI BibTeX RDF |
adaptive location policies, global scheduling algorithm, transfer policy, location policy, location policies, receiver-initiated, sender-initiated, symmetrically-initiated, system workload, search activities, short transfer latency, nonadaptive policies, system instability, scheduling, performance evaluation, distributed systems, load balancing, resource allocation, distributed processing, probability, load sharing, distributed scheduling, task migration, low overhead |
14 | P. Venkat Rangan |
Trust Requirements and Performance of a Fast Subtransprot-Level Protocol for Secure Communication. |
IEEE Trans. Software Eng. |
1993 |
DBLP DOI BibTeX RDF |
trust requirements, fast subtransport-level protocol, authenticated datagram protocol, host-to-host secure channels, agent-to-agent channels, average latency, performance, protocols, data integrity, Ethernet, security of data, secure communication, Sun workstations, maximum throughput |
14 | Ali Azarbayejani, Thad Starner, Bradley Horowitz, Alex Pentland |
Visually Controlled Graphics. |
IEEE Trans. Pattern Anal. Mach. Intell. |
1993 |
DBLP DOI BibTeX RDF |
visually controlled graphics, interactive graphics system, display latency, user interfaces, user interfaces, computer vision, computer vision, computer graphics, computer graphics, accuracy, interactive systems, compensation, computational efficiency, structure recovery |
14 | Divyakant Agrawal, Arthur J. Bernstein |
A Nonblocking Quorum Consensus Protocol for Replicated Data. |
IEEE Trans. Parallel Distributed Syst. |
1991 |
DBLP DOI BibTeX RDF |
nonblocking quorum protocol, one-copy serializability, fault tolerance, protocols, distributed databases, availability, database theory, replica control, fault tolerantcomputing, access latency |
14 | Kun-Lung Wu, W. Kent Fuchs, Janak H. Patel |
Error Recovery in Shared Memory Multiprocessors Using Private Caches. |
IEEE Trans. Parallel Distributed Syst. |
1990 |
DBLP DOI BibTeX RDF |
processor transient faults, user-transparent checkpointing, checkpointed computation state, recovery stacks, rollback propagation, rapidrecovery, fault tolerance, fault tolerant computing, multiprocessor interconnection networks, multiprocessing systems, shared memory multiprocessors, system recovery, buffer storage, cache coherence protocols, performance degradation, processor utilization, private caches, error latency |
14 | Riccardo Gusella, Stefano Zatti |
The Accuracy of the Clock Synchronization Achieved by TEMPO in Berkeley UNIX 4.3BSD. |
IEEE Trans. Software Eng. |
1989 |
DBLP DOI BibTeX RDF |
TEMPO, Berkeley UNIX 4.3BSD, network transmission latency, VAX computers, lower bounds, fault tolerant computing, Unix, local area network, local area networks, synchronisation, upper bounds, clock synchronization, distributed service |
11 | Dionysios Efstathiou, Andreas Koutsopoulos, Sotiris E. Nikoletseas |
Analysis and simulation for parameterizing the energy-latency trade-off for routing in sensor networks. |
MSWiM |
2010 |
DBLP DOI BibTeX RDF |
|
11 | Mirko Suznjevic, Ognjen Dobrijevic, Maja Matijasevic |
MMORPG Player actions: Network performance, session patterns and latency requirements analysis. |
Multim. Tools Appl. |
2009 |
DBLP DOI BibTeX RDF |
Player activity, Performance, Patterns, MMORPG, Networked game |
11 | Joshua S. Auerbach, David F. Bacon, Daniel T. Iercan, Christoph M. Kirsch, V. T. Rajan, Harald Röck, Rainer Trummer |
Low-latency time-portable real-time programming with Exotasks. |
ACM Trans. Embed. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
time portability, virtual machine, Real-time scheduling, UAVs |
11 | Feng Zou, Zhao Zhang 0002, Weili Wu 0001 |
Latency-Bounded Minimum Influential Node Selection in Social Networks. |
WASA |
2009 |
DBLP DOI BibTeX RDF |
influential nodes selection, Social network, information diffusion |
11 | Xiaohui Chen, Weidong Wang, Guo Wei 0001 |
Reducing Web Latency in Mobile Network. |
ACIS-ICIS |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto |
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
FPGAs, reconfigurable computing, mapping algorithms |
11 | Padmanabhan Pillai, Lily B. Mummert, Steven W. Schlosser, Rahul Sukthankar, Casey Helfrich |
SLIPstream: scalable low-latency interactive perception on streaming data. |
NOSSDAV |
2009 |
DBLP DOI BibTeX RDF |
cluster applications, computational perception, multimedia, parallel computing, stream processing, sensing |
11 | Koji Ishibashi, Hideki Ochiai, Ryuji Kohno |
Embedded forward error control technique (EFECT) for low-rate but low latency communications. |
IEEE Trans. Wirel. Commun. |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Ozgur Erdinc, Craig Brideau, Peter Willett 0001, Thia Kirubarajan |
The Problem of Test Latency in Machine Diagnosis. |
IEEE Trans. Syst. Man Cybern. Part A |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Diana Marculescu, Siddharth Garg |
Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Tsung-Han Tsai 0001, Chun-Nan Liu |
A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Prefix grouping, VLIW DSP processor, Multimedia, Parallel processing, Huffman coding |
11 | Sébastien Lafond, Johan Lilius |
Interrupt Costs in Embedded System with Short Latency Hardware Accelerators. |
ECBS |
2008 |
DBLP DOI BibTeX RDF |
Interrupt, Hardware accelerator |
11 | Vinod Namboodiri, Abtin Keshavarzian |
Alert: An Adaptive Low-Latency Event-Driven MAC Protocol for Wireless Sensor Networks. |
IPSN |
2008 |
DBLP DOI BibTeX RDF |
Wireless Sensor Networks, MAC Protocol |
11 | Krishna Kant Chintalapudi, Lakshmi Venkatraman |
On the Design of MAC Protocols for Low-Latency Hard Real-Time Discrete Control Applications over 802.15.4 Hardware. |
IPSN |
2008 |
DBLP DOI BibTeX RDF |
Discrete Control, Low-power, MAC, Hard Real-time |
11 | Wei Wang 0002, Mehul Motani, Vikram Srinivasan |
Dependent link padding algorithms for low latency anonymity systems. |
CCS |
2008 |
DBLP DOI BibTeX RDF |
anonymity systems, link padding, traffic analysis attack |
11 | Greg Hoover, Forrest Brewer, Chris Gill 0001 |
Latency-Insensitive Hardware/Software Interfaces. |
MEMOCODE |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Patrick P. Tsang, Sean W. Smith |
YASIR: A Low-Latency, High-Integrity Security Retrofit for Legacy SCADA Systems. |
SEC |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Ching-Wen Chen, Chuan-Chi Weng, Po-Jung Chen |
Design of a Low-Power and Low-Latency MAC Protocol with Nodes Grouping and Transmission Pipelining in Wireless Sensor Networks. |
VTC Spring |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan |
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Sergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci |
LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Holger Lange, Andreas Koch 0001 |
Low-latency high-bandwidth HW/SW communication in a virtual memory environment. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jan de Cuveland, Felix Rettig, Venelin Angelov, Volker Lindenstruth |
An FPGA-based high-speed, low-latency trigger processor for high-energy physics. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Yi-Neng Lin, Che-Wen Wu, Ying-Dar Lin, Yuan-Cheng Lai |
A Latency and Modulation Aware Bandwidth Allocation Algorithm for WiMAX Base Stations. |
WCNC |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Erik F. Golen, Nirmala Shenoy, Xiaojun Cao |
A Low Latency Scheme for Bulk RFID Tag Reading. |
WCNC |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Zhenning Kong, Edmund M. Yeh |
Connectivity and Latency in Large-Scale Wireless Networks with Unreliable Links. |
INFOCOM |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Parvathinathan Venkitasubramaniam, Lang Tong |
Throughput Anonymity Trade-off in Wireless Networks under Latency Constraints. |
INFOCOM |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Steven J. Murdoch, Robert N. M. Watson |
Metrics for Security and Performance in Low-Latency Anonymity Systems. |
Privacy Enhancing Technologies |
2008 |
DBLP DOI BibTeX RDF |
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