Search results for "finfet"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Qing Xie 0001, Xue Lin, Yanzhi Wang, Shuang Chen 0001, Mohammad Javad Dousti, Massoud Pedram	Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries.	IEEE Trans. Circuits Syst. II Express Briefs	2015	DBLP DOI BibTeX RDF
14	Ning Lu, Richard A. Wachnik	Modeling of Resistance in FinFET Local Interconnect.	IEEE Trans. Circuits Syst. I Regul. Pap.	2015	DBLP DOI BibTeX RDF
14	Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa	Structure optimization for timing in nano scale FinFET.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
14	Yu Yuan, Cecilia García Martin, Erdal Oruklu	Standard cell library characterization for FinFET transistors using BSIM-CMG models.	EIT	2015	DBLP DOI BibTeX RDF
14	Deeksha Anandani, Anurag Kumar, V. S. Kanchana Bhaaskaran	Gating techniques for 6T SRAM cell using different modes of FinFET.	ICACCI	2015	DBLP DOI BibTeX RDF
14	Jean-Pierre Raskin	FinFET versus UTBB SOI - A RF perspective.	ESSDERC	2015	DBLP DOI BibTeX RDF
14	Yves Laplanche	Implementation of ARM® Cores in FinFET technolgies.	ESSDERC	2015	DBLP DOI BibTeX RDF
14	Dong-Hyeok Son, Young-woo Jo, Ryun-Hwi Kim, Chan Heo, Jae Hwa Seo, Jin Su Kim, In Man Kang, Sorin Cristoloveanu, Jung-Hee Lee	Fabrication of high performance AlGaN/GaN FinFET by utilizing anisotropic wet etching in TMAH solution.	ESSDERC	2015	DBLP DOI BibTeX RDF
14	Shraddha Kothari, Chandan Joishi, Dhirendra Vaidya, Hasan Nejad, Benjamin Colombeau, Swaroop Ganguly, Saurabh Lodha	Metal gate VT modulation using PLAD N2 implants for Ge p-FinFET applications.	ESSDERC	2015	DBLP DOI BibTeX RDF
14	Kunzhi Yu, Cheng Li, Tsung-Ching Huang, M. Ashkan Seyedi, Dacheng Zhou, Christopher Wilson, Daniel A. Berkram, Samuel Palermo, Jonathan Q. Smela, Marco Fiorentino, Raymond G. Beausoleil	56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process.	MWSCAS	2015	DBLP DOI BibTeX RDF
14	Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi	Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power.	ISVLSI	2015	DBLP DOI BibTeX RDF
14	Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian	Overview study on fault modeling and test methodology development for FinFET-based memories.	EWDTS	2015	DBLP DOI BibTeX RDF
14	Phil Oldiges, Kenneth P. Rodbell, Michael S. Gordon, John G. Massey, Kevin Stawiasz, Conal E. Murray, Henry H. K. Tang, K. Kim, K. Paul Muller	SOI FinFET soft error upset susceptibility and analysis.	IRPS	2015	DBLP DOI BibTeX RDF
14	Franco Stellari, Keith A. Jenkins, Alan J. Weger, Barry P. Linder, Peilin Song	Self-heating characterization of FinFET SOI devices using 2D time resolved emission measurements.	IRPS	2015	DBLP DOI BibTeX RDF
14	Jian-Hsing Lee, Manjunatha Prabhu, Konstantin Korablev, Jagar Singh, Mahadeva Iyer Natarajan, Shesh Mani Pandey	Methodology to achieve planar technology-like ESD performance in FINFET process.	IRPS	2015	DBLP DOI BibTeX RDF
14	Yongsheng Sun, Canhui Zhan, Jianping Guo, Yiwei Fu, Guangming Li, Jun Xia	Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies.	IRPS	2015	DBLP DOI BibTeX RDF
14	Choelhwyi Bae, Sangwoo Pae, Cheong-sik Yu, Kangjung Kim, Yongshik Kim, Jongwoo Park 0001	SRAM stability design comprehending 14nm FinFET reliability.	IRPS	2015	DBLP DOI BibTeX RDF
14	N. Tam, Bharat L. Bhuva, Lloyd W. Massengill, Dennis R. Ball, Michael W. McCurdy, Michael L. Alles, Indranil Chatterjee	Multi-cell soft errors at the 16-nm FinFET technology node.	IRPS	2015	DBLP DOI BibTeX RDF
14	C. W. Chang, S. E. Liu, B. L. Lin, C. C. Chiu, Y.-H. Lee, K. Wu	Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects.	IRPS	2015	DBLP DOI BibTeX RDF
14	Nilesh Goel, P. Dubey, J. Kawa, S. Mahapatra	Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages.	IRPS	2015	DBLP DOI BibTeX RDF
14	Changze Liu, Hyun-Chul Sagong, Hyejin Kim, Seungjin Choo, Hyunwoo Lee, Yoohwan Kim, Hyunjin Kim, Bisung Jo, Minjung Jin, Jinjoo Kim, Sangsu Ha, Sangwoo Pae, Jongwoo Park 0001	Systematical study of 14nm FinFET reliability: From device level stress to product HTOL.	IRPS	2015	DBLP DOI BibTeX RDF
14	Miaomiao Wang 0006, Zuoguang Liu, Tenko Yamashita, James H. Stathis, Chia-Yu Chen	Separation of interface states and electron trapping for hot carrier degradation in ultra-scaled replacement metal gate n-FinFET.	IRPS	2015	DBLP DOI BibTeX RDF
14	I. K. Chen, C. L. Chen, Y.-H. Lee, R. Lu, Y. W. Lee, H. H. Hsu, Y. W. Tseng, Y. W. Lin, J. R. Shih	New TDDB lifetime model for AC inverter-like stress in advance FinFET structure.	IRPS	2015	DBLP DOI BibTeX RDF
14	Soonyoung Lee, Ilgon Kim, Sungmock Ha, Cheong-sik Yu, Jinhyun Noh, Sangwoo Pae, Jongwoo Park 0001	Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices.	IRPS	2015	DBLP DOI BibTeX RDF
14	Ji Li 0006, Qing Xie 0001, Yanzhi Wang, Shahin Nazarian, Massoud Pedram	Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique.	DATE	2015	DBLP BibTeX RDF
14	Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara	Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology.	DATE	2015	DBLP BibTeX RDF
14	A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy 0001	Asymmetric underlapped FinFET based robust SRAM design at 7nm node.	DATE	2015	DBLP BibTeX RDF
14	Osama Abdelkader, Hassan Mostafa, Hamdy Abd Elhamid, Ahmed M. Soliman	The impact of FinFET technology scaling on critical path performance under process variations.	ICEAC	2015	DBLP DOI BibTeX RDF
14	Alireza Shafaei, Shuang Chen 0001, Yanzhi Wang, Massoud Pedram	A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations.	ASP-DAC	2015	DBLP DOI BibTeX RDF
14	Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li	Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits.	ATS	2015	DBLP DOI BibTeX RDF
14	Alessandra Leonhardt, Luiz Fernando Ferreira, Sergio Bampi	Nanoscale FinFET global parameter extraction for the BSIM-CMG model.	LASCAS	2015	DBLP DOI BibTeX RDF
14	Felipe Rosa 0001, Raphael Martins Brum, Gilson I. Wirth, Luciano Ost, Ricardo Reis 0001	Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability.	ICECS	2015	DBLP DOI BibTeX RDF
14	Osama Abdelkader, Hassan Mostafa, Hamdy Abd Elhamid, Ahmed M. Soliman	Impact of technology scaling on the minimum energy point for FinFET based flip-flops.	ICECS	2015	DBLP DOI BibTeX RDF
14	Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis 0001	Process variability in FinFET standard cells with different transistor sizing techniques.	ICECS	2015	DBLP DOI BibTeX RDF
14	Po-Hsun Wu, Mark Po-Hung Lin, Xin Li 0001, Tsung-Yi Ho	Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment.	ISPD	2015	DBLP DOI BibTeX RDF
14	Kirti Bhanushali, W. Rhett Davis	FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology.	ISPD	2015	DBLP DOI BibTeX RDF
14	Juan Pablo Duarte, Sourabh Khandelwal, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan	BSIM-CMG: Standard FinFET compact model for advanced circuit design.	ESSCIRC	2015	DBLP DOI BibTeX RDF
14	Sanu Mathew, David Johnston, Paul Newman 0002, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Gregory K. Chen, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001	μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS.	ESSCIRC	2015	DBLP DOI BibTeX RDF
14	Alexander Fritsch, Michael Kugel, Rolf Sautter, Dieter F. Wendel, Juergen Pille, Otto A. Torreiter, Shankar Kalyanasundaram, Daniel A. Dobson	A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.	ESSCIRC	2015	DBLP DOI BibTeX RDF
14	Mei-Chen Chuang, Chia-Liang Tai, Ying-Chih Hsu, Alan Roth, Eric G. Soenen	A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from -50°C to 150°C in a 16nm FinFET process.	ESSCIRC	2015	DBLP DOI BibTeX RDF
14	Tatjana Pesic-Brdjanin, Nebojsa D. Jankovic	Sub-sircuit model of fully-depleted double-gate FinFET including the effects of oxide and interface trapped charge.	EUROCON	2015	DBLP DOI BibTeX RDF
14	Ermao Cai, Diana Marculescu	TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems.	ICCAD	2015	DBLP DOI BibTeX RDF
14	Sravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar	Optimization of FinFET-based circuits using a dual gate pitch technique.	ICCAD	2015	DBLP DOI BibTeX RDF
14	Mohamed Mohie El-Din, Hassan Mostafa, Hossam A. H. Fahmy, Yehea I. Ismail, Hamdy Abdelhamid	Performance evaluation of FinFET-based FPGA cluster under threshold voltage variation.	NEWCAS	2015	DBLP DOI BibTeX RDF
14	Mohsen Imani, Shruti Patil, Tajana Simunic Rosing	Hierarchical design of robust and low data dependent FinFET based SRAM array.	NANOARCH	2015	DBLP DOI BibTeX RDF
14	Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo	Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.	NANOARCH	2015	DBLP DOI BibTeX RDF
14	Srinivasa Banna	Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited).	CICC	2015	DBLP DOI BibTeX RDF
14	Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski	14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S.	ISSCC	2015	DBLP DOI BibTeX RDF
14	Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane 0001, Uddalak Bhattacharya, Kevin Zhang 0001	17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.	ISSCC	2015	DBLP DOI BibTeX RDF
14	Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang	17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies.	ISSCC	2015	DBLP DOI BibTeX RDF
14	Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu	10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver.	ISSCC	2015	DBLP DOI BibTeX RDF
14	Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park	14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology.	ISSCC	2015	DBLP DOI BibTeX RDF
14	Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park	15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology.	ISSCC	2015	DBLP DOI BibTeX RDF
14	Kyung-Hoae Koo, Liqiong Wei, John Keane 0001, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang 0001	A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist.	VLSIC	2015	DBLP DOI BibTeX RDF
14	Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan	14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation.	VLSIC	2015	DBLP DOI BibTeX RDF
14	Tsung-Kai Kao, Ping Chen, Jui-Yuan Tsai, Pao-Cheng Chiu	A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application.	VLSIC	2015	DBLP DOI BibTeX RDF
14	Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang	Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness.	ISCAS	2015	DBLP DOI BibTeX RDF
14	Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain	A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology.	SoCC	2015	DBLP DOI BibTeX RDF
14	Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang	Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications.	SoCC	2015	DBLP DOI BibTeX RDF
14	A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil	Through silicon via to FinFET noise coupling in 3-D integrated circuits.	ICICDT	2015	DBLP DOI BibTeX RDF
14	Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean	Modeling FinFET metal gate stack resistance for 14nm node and beyond.	ICICDT	2015	DBLP DOI BibTeX RDF
14	Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang	Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices.	ICICDT	2015	DBLP DOI BibTeX RDF
14	Geert Eneman, An De Keersgieter, Anda Mocuta, Nadine Collaert, Aaron Thean	FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below.	ICICDT	2015	DBLP DOI BibTeX RDF
14	Hector Villacorta, Roberto Gómez 0001, Sebastià A. Bota, Jaume Segura 0001, Víctor H. Champac	Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell.	LATS	2015	DBLP DOI BibTeX RDF
14	Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram	Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
14	Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi	Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET.	ACM Great Lakes Symposium on VLSI	2015	DBLP DOI BibTeX RDF
14	Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui	Employing the mixed FBB/RBB in the design of FinFET logic gates.	ASICON	2015	DBLP DOI BibTeX RDF
14	Meng-Chou Chang, Kai-Lun He	Design of low-power FinFET-based TCAMs with unevenly-segmented matchlines for routing table applications.	ASICON	2015	DBLP DOI BibTeX RDF
14	Alireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram	Design optimization of sense amplifiers using deeply-scaled FinFET devices.	ISQED	2015	DBLP DOI BibTeX RDF
14	Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov	Circuit design perspectives for Ge FinFET at 10nm and beyond.	ISQED	2015	DBLP DOI BibTeX RDF
14	Mohammad Saeed Abrishami, Alireza Shafaei, Yanzhi Wang, Massoud Pedram	Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies.	ISQED	2015	DBLP DOI BibTeX RDF
14	Roohollah Yarmand, Behzad Ebrahimi, Hassan Afzali-Kusha, Ali Afzali-Kusha, Massoud Pedram	High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors.	ISQED	2015	DBLP DOI BibTeX RDF
14	Chieh-Yang Chen, Wen-Tsung Huang, Yiming Li 0005	Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness.	ISQED	2015	DBLP DOI BibTeX RDF
14	Gurgen Harutyunyan, Grigor Tshagharyan, Yervant Zorian	Impact of parameter variations on FinFET faults.	VTS	2015	DBLP DOI BibTeX RDF
14	Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke	Diagnosing timing related cell internal defects for FinFET technology.	VLSI-DAT	2015	DBLP DOI BibTeX RDF
14	Sudeb Dasgupta, Bulusu Anand	Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges.	VLSID	2015	DBLP DOI BibTeX RDF
14	Chia-Liang Tai, Alan Roth, Eric G. Soenen	A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process.	A-SSCC	2015	DBLP DOI BibTeX RDF
14	Zoran Jaksic	Cache memory design in the FinFET era.		2015	RDF
14	Chun-Yi Lee, Niraj K. Jha	FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
14	Yang Yang, Niraj K. Jha	FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
14	Zia Abbas, Antonio Mastrandrea, Mauro Olivieri	A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
14	Ajay N. Bhoj, Niraj K. Jha	Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
14	K. Keerti Kumar, N. Bheema Rao	Power gating Technique using FinFET for Minimization of sub-Threshold Leakage Current.	J. Circuits Syst. Comput.	2014	DBLP DOI BibTeX RDF
14	Qian Xie, Renrong Liang, Jing Wang, Libin Liu, Jun Xu	Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects.	Sci. China Inf. Sci.	2014	DBLP DOI BibTeX RDF
14	Sourindra Chaudhuri, Niraj K. Jha	3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations.	ACM J. Emerg. Technol. Comput. Syst.	2014	DBLP DOI BibTeX RDF
14	Xianmin Chen, Niraj K. Jha	Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles.	ACM J. Emerg. Technol. Comput. Syst.	2014	DBLP DOI BibTeX RDF
14	Sourindra M. Chaudhuri, Prateek Mishra, Niraj K. Jha	Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology.	ACM J. Emerg. Technol. Comput. Syst.	2014	DBLP DOI BibTeX RDF
14	Piotr Zajac, Marcin Janicki, Michal Szermer, Andrzej Napieralski	Evaluating the impact of scaling on temperature in FinFET-technology multicore processors.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
14	Arundhati Bhattacharya, Aminul Islam 0002	Design and Analysis of Robust Spin Transfer Torque Magnetic Random Access Memory Bitcell Using FinFET.	J. Low Power Electron.	2014	DBLP DOI BibTeX RDF
14	Laurent Artola, Guillaume Hubert, Massimo Alioto	Comparative soft error evaluation of layout cells in FinFET technology.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Antonio Calomarde, Esteve Amat, Francesc Moll, Julio Vigara, Antonio Rubio 0001	SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang	Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Hemant Pardeshi, Chandan Kumar Sarkar	Analysis of flicker and thermal noise in p-channel Underlap DG FinFET.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Cristina Meinhardt, Alexandra L. Zimpeck, Ricardo A. L. Reis	Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi	Robust FinFET SRAM design based on dynamic back-gate voltage adjustment.	Microelectron. Reliab.	2014	DBLP DOI BibTeX RDF
14	Panagiotis Chaourani, Spyridon Nikolaidis 0001	A unified CMOS inverter model for planar and FinFET nanoscale technologies.	DDECS	2014	DBLP DOI BibTeX RDF
14	Mark Buckler, Arpan Vaidya, Xiaobin Liu, Wayne P. Burleson	Dynamic synchronizer flip-flop performance in FinFET technologies.	NOCS	2014	DBLP DOI BibTeX RDF
14	Vimal Kumar Mishra, Rajeev K. Chauhan	Impact of Ge substrate on drain current of Trigate N-FinFET.	ICACCI	2014	DBLP DOI BibTeX RDF
14	Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Asen Asenov	Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability.	ESSDERC	2014	DBLP DOI BibTeX RDF
14	Giulia Piccolo, P. I. Kuindersma, L.-Å. Ragnarsson, Raymond J. E. Hueting, Nadine Collaert, Jurriaan Schmitz	Silicon LEDs in FinFET technology.	ESSDERC	2014	DBLP DOI BibTeX RDF