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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 59 occurrences of 34 keywords
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Results
Found 1191 publication records. Showing 1191 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Qing Xie 0001, Xue Lin, Yanzhi Wang, Shuang Chen 0001, Mohammad Javad Dousti, Massoud Pedram |
Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 62-II(8), pp. 761-765, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Ning Lu, Richard A. Wachnik |
Modeling of Resistance in FinFET Local Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8), pp. 1899-1907, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa |
Structure optimization for timing in nano scale FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(9), pp. 20150297, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Yu Yuan, Cecilia García Martin, Erdal Oruklu |
Standard cell library characterization for FinFET transistors using BSIM-CMG models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: IEEE International Conference on Electro/Information Technology, EIT 2015, Dekalb, IL, USA, May 21-23, 2015, pp. 494-498, 2015, IEEE, 978-1-4799-8802-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Deeksha Anandani, Anurag Kumar, V. S. Kanchana Bhaaskaran |
Gating techniques for 6T SRAM cell using different modes of FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, Kochi, India, August 10-13, 2015, pp. 483-487, 2015, IEEE, 978-1-4799-8790-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Jean-Pierre Raskin |
FinFET versus UTBB SOI - A RF perspective. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 45th European Solid State Device Research Conference, ESSDERC 2015, Graz, Austria, September 14-18, 2015, pp. 84-88, 2015, IEEE, 978-1-4673-7133-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Yves Laplanche |
Implementation of ARM® Cores in FinFET technolgies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 45th European Solid State Device Research Conference, ESSDERC 2015, Graz, Austria, September 14-18, 2015, pp. 80-83, 2015, IEEE, 978-1-4673-7133-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Dong-Hyeok Son, Young-woo Jo, Ryun-Hwi Kim, Chan Heo, Jae Hwa Seo, Jin Su Kim, In Man Kang, Sorin Cristoloveanu, Jung-Hee Lee |
Fabrication of high performance AlGaN/GaN FinFET by utilizing anisotropic wet etching in TMAH solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 45th European Solid State Device Research Conference, ESSDERC 2015, Graz, Austria, September 14-18, 2015, pp. 130-133, 2015, IEEE, 978-1-4673-7133-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Shraddha Kothari, Chandan Joishi, Dhirendra Vaidya, Hasan Nejad, Benjamin Colombeau, Swaroop Ganguly, Saurabh Lodha |
Metal gate VT modulation using PLAD N2 implants for Ge p-FinFET applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 45th European Solid State Device Research Conference, ESSDERC 2015, Graz, Austria, September 14-18, 2015, pp. 214-217, 2015, IEEE, 978-1-4673-7133-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Kunzhi Yu, Cheng Li, Tsung-Ching Huang, M. Ashkan Seyedi, Dacheng Zhou, Christopher Wilson, Daniel A. Berkram, Samuel Palermo, Jonathan Q. Smela, Marco Fiorentino, Raymond G. Beausoleil |
56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MWSCAS ![In: IEEE 58th International Midwest Symposium on Circuits and Systems, MWSCAS 2015, Fort Collins, CO, USA, August 2-5, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-6558-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Behzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi |
Sub-Threshold SRAM Design in 14 Nm FinFET Technology with Improved Access Time and Leakage Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2015 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, Montpellier, France, July 8-10, 2015, pp. 74-79, 2015, IEEE Computer Society, 978-1-4799-8719-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Grigor Tshagharyan, Gurgen Harutyunyan, Samvel K. Shoukourian, Yervant Zorian |
Overview study on fault modeling and test methodology development for FinFET-based memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EWDTS ![In: 2015 IEEE East-West Design & Test Symposium, EWDTS 2015, Batumi, Georgia, September 26-29, 2015, pp. 1-4, 2015, IEEE Computer Society, 978-1-4673-7776-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Phil Oldiges, Kenneth P. Rodbell, Michael S. Gordon, John G. Massey, Kevin Stawiasz, Conal E. Murray, Henry H. K. Tang, K. Kim, K. Paul Muller |
SOI FinFET soft error upset susceptibility and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Franco Stellari, Keith A. Jenkins, Alan J. Weger, Barry P. Linder, Peilin Song |
Self-heating characterization of FinFET SOI devices using 2D time resolved emission measurements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 2, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Jian-Hsing Lee, Manjunatha Prabhu, Konstantin Korablev, Jagar Singh, Mahadeva Iyer Natarajan, Shesh Mani Pandey |
Methodology to achieve planar technology-like ESD performance in FINFET process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 3, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Yongsheng Sun, Canhui Zhan, Jianping Guo, Yiwei Fu, Guangming Li, Jun Xia |
Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 3, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Choelhwyi Bae, Sangwoo Pae, Cheong-sik Yu, Kangjung Kim, Yongshik Kim, Jongwoo Park 0001 |
SRAM stability design comprehending 14nm FinFET reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 13, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | N. Tam, Bharat L. Bhuva, Lloyd W. Massengill, Dennis R. Ball, Michael W. McCurdy, Michael L. Alles, Indranil Chatterjee |
Multi-cell soft errors at the 16-nm FinFET technology node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | C. W. Chang, S. E. Liu, B. L. Lin, C. C. Chiu, Y.-H. Lee, K. Wu |
Thermal behavior of self-heating effect in FinFET devices acting on back-end interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 2, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Nilesh Goel, P. Dubey, J. Kawa, S. Mahapatra |
Impact of time-zero and NBTI variability on sub-20nm FinFET based SRAM at low voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 5, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Changze Liu, Hyun-Chul Sagong, Hyejin Kim, Seungjin Choo, Hyunwoo Lee, Yoohwan Kim, Hyunjin Kim, Bisung Jo, Minjung Jin, Jinjoo Kim, Sangsu Ha, Sangwoo Pae, Jongwoo Park 0001 |
Systematical study of 14nm FinFET reliability: From device level stress to product HTOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 2, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Miaomiao Wang 0006, Zuoguang Liu, Tenko Yamashita, James H. Stathis, Chia-Yu Chen |
Separation of interface states and electron trapping for hot carrier degradation in ultra-scaled replacement metal gate n-FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | I. K. Chen, C. L. Chen, Y.-H. Lee, R. Lu, Y. W. Lee, H. H. Hsu, Y. W. Tseng, Y. W. Lin, J. R. Shih |
New TDDB lifetime model for AC inverter-like stress in advance FinFET structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 5, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Soonyoung Lee, Ilgon Kim, Sungmock Ha, Cheong-sik Yu, Jinhyun Noh, Sangwoo Pae, Jongwoo Park 0001 |
Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2015, Monterey, CA, USA, April 19-23, 2015, pp. 4, 2015, IEEE, 978-1-4673-7362-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Ji Li 0006, Qing Xie 0001, Yanzhi Wang, Shahin Nazarian, Massoud Pedram |
Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 1579-1582, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
14 | Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara |
Comparative study of power-gating architectures for nonvolatile FinFET-SRAM using spintronics-based retention technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 866-871, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
14 | A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy 0001 |
Asymmetric underlapped FinFET based robust SRAM design at 7nm node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 659-664, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
14 | Osama Abdelkader, Hassan Mostafa, Hamdy Abd Elhamid, Ahmed M. Soliman |
The impact of FinFET technology scaling on critical path performance under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEAC ![In: 5th International Conference on Energy Aware Computing Systems & Applications, ICEAC 2015, Cairo, Egypt, March 24-26, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-1771-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Alireza Shafaei, Shuang Chen 0001, Yanzhi Wang, Massoud Pedram |
A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: The 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, January 19-22, 2015, pp. 75-80, 2015, IEEE, 978-1-4799-7792-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li |
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 24th IEEE Asian Test Symposium, ATS 2015, Mumbai, India, November 22-25, 2015, pp. 181-186, 2015, IEEE Computer Society, 978-1-4673-9739-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Alessandra Leonhardt, Luiz Fernando Ferreira, Sergio Bampi |
Nanoscale FinFET global parameter extraction for the BSIM-CMG model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8332-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Felipe Rosa 0001, Raphael Martins Brum, Gilson I. Wirth, Luciano Ost, Ricardo Reis 0001 |
Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 137-140, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Osama Abdelkader, Hassan Mostafa, Hamdy Abd Elhamid, Ahmed M. Soliman |
Impact of technology scaling on the minimum energy point for FinFET based flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 462-465, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis 0001 |
Process variability in FinFET standard cells with different transistor sizing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2015 IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2015, Cairo, Egypt, December 6-9, 2015, pp. 121-124, 2015, IEEE, 978-1-5090-0246-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Po-Hsun Wu, Mark Po-Hung Lin, Xin Li 0001, Tsung-Yi Ho |
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015, pp. 25-31, 2015, ACM, 978-1-4503-3399-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Kirti Bhanushali, W. Rhett Davis |
FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015, pp. 165-170, 2015, ACM, 978-1-4503-3399-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Juan Pablo Duarte, Sourabh Khandelwal, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan |
BSIM-CMG: Standard FinFET compact model for advanced circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference, Graz, Austria, September 14-18, 2015, pp. 196-201, 2015, IEEE, 978-1-4673-7470-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Sanu Mathew, David Johnston, Paul Newman 0002, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders 0001, Himanshu Kaul, Gregory K. Chen, Amit Agarwal 0001, Steven Hsu, Ram Krishnamurthy 0001 |
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference, Graz, Austria, September 14-18, 2015, pp. 116-119, 2015, IEEE, 978-1-4673-7470-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Alexander Fritsch, Michael Kugel, Rolf Sautter, Dieter F. Wendel, Juergen Pille, Otto A. Torreiter, Shankar Kalyanasundaram, Daniel A. Dobson |
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference, Graz, Austria, September 14-18, 2015, pp. 343-346, 2015, IEEE, 978-1-4673-7470-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Mei-Chen Chuang, Chia-Liang Tai, Ying-Chih Hsu, Alan Roth, Eric G. Soenen |
A temperature sensor with a 3 sigma inaccuracy of ±2°C without trimming from -50°C to 150°C in a 16nm FinFET process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference, Graz, Austria, September 14-18, 2015, pp. 271-274, 2015, IEEE, 978-1-4673-7470-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Tatjana Pesic-Brdjanin, Nebojsa D. Jankovic |
Sub-sircuit model of fully-depleted double-gate FinFET including the effects of oxide and interface trapped charge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCON ![In: IEEE EUROCON 2015 - International Conference on Computer as a Tool, Salamanca, Spain, September 8-11, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8569-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Ermao Cai, Diana Marculescu |
TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015, pp. 500-507, 2015, IEEE, 978-1-4673-8389-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Sravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar |
Optimization of FinFET-based circuits using a dual gate pitch technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015, pp. 758-763, 2015, IEEE, 978-1-4673-8389-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Mohamed Mohie El-Din, Hassan Mostafa, Hossam A. H. Fahmy, Yehea I. Ismail, Hamdy Abdelhamid |
Performance evaluation of FinFET-based FPGA cluster under threshold voltage variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: IEEE 13th International New Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, June 7-10, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8893-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Mohsen Imani, Shruti Patil, Tajana Simunic Rosing |
Hierarchical design of robust and low data dependent FinFET based SRAM array. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 63-68, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo |
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NANOARCH ![In: Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015, pp. 112-117, 2015, IEEE Computer Society, 978-1-4673-7849-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Srinivasa Banna |
Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited). ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICC ![In: 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015, pp. 1-8, 2015, IEEE, 978-1-4799-8682-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski |
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane 0001, Uddalak Bhattacharya, Kevin Zhang 0001 |
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Kao-Cheng Lin, Dar Sun, Shin-Rung Wu, Jhon-Jhy Liaw, Chih-Yung Lin, Mu-Chi Chiang, Hung-Jen Liao, Shien-Yang Wu, Jonathan Chang |
17.2 A 64kb 16nm asynchronous disturb current free 2-port SRAM with PMOS pass-gates for FinFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Pier Andrea Francese, Thomas Toifl, Matthias Braendli, Christian Menolfi, Marcel A. Kossel, Thomas Morf, Lukas Kull, Toke Meyer Andersen, Hazar Yueksel, Alessandro Cevrero, Danny Luu |
10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Minyoung Song, Taeik Kim, Jihyun F. Kim, Wooseok Kim, Sung-Jin Kim, Hojin Park |
14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Sung-Jin Kim, Wooseok Kim, Minyoung Song, Jihyun F. Kim, Taeik Kim, Hojin Park |
15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015, Digest of Technical Papers, San Francisco, CA, USA, February 22-26, 2015, pp. 1-3, 2015, IEEE, 978-1-4799-6223-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Kyung-Hoae Koo, Liqiong Wei, John Keane 0001, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang 0001 |
A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015, pp. 266-, 2015, IEEE, 978-4-86348-502-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan |
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015, pp. 268-, 2015, IEEE, 978-4-86348-502-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Tsung-Kai Kao, Ping Chen, Jui-Yuan Tsai, Pao-Cheng Chiu |
A 16nm FinFet 19/39MHz 78/72dB DR noise-injected aggregated CTSDM ADC for configurable LTE advanced CCA/NCCA Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSIC ![In: Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015, pp. 260-, 2015, IEEE, 978-4-86348-502-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, pp. 2325-2328, 2015, IEEE, 978-1-4799-8391-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Vaibhav Verma, Sachin Taneja, Pritender Singh, Sanjeev Kumar Jain |
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015, pp. 304-309, 2015, IEEE, 978-1-4673-9094-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015, pp. 339-344, 2015, IEEE, 978-1-4673-9094-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | A. Rouhi Najaf Abadi, W. Guo, X. Sun, K. Ben Ali, Jean-Pierre Raskin, Martin Rack, C. Roda Neve, M. Choi, V. Moroz, Geert Van der Plas, Ingrid De Wolf, Eric Beyne, Philippe P. Absil |
Through silicon via to FinFET noise coupling in 3-D integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-7669-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Kenichi Miyaguchi, Bertrand Parvais, Lars-Åke Ragnarsson, Piet Wambacq, Praveen Raghavan, Abdelkarim Mercha, Anda Mocuta, Diederik Verkest, Aaron Thean |
Modeling FinFET metal gate stack resistance for 14nm node and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-7669-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-7669-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Geert Eneman, An De Keersgieter, Anda Mocuta, Nadine Collaert, Aaron Thean |
FinFET stressor efficiency on alternative wafer and channel orientations for the 14 nm node and below. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICDT ![In: 2015 International Conference on IC Design & Technology, ICICDT 2015, Leuven, Belgium, June 1-3, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-7669-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Hector Villacorta, Roberto Gómez 0001, Sebastià A. Bota, Jaume Segura 0001, Víctor H. Champac |
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATS ![In: 16th Latin-American Test Symposium, LATS 2015, Puerto Vallarta, Mexico, March 25-27, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4673-6710-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram |
Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 33-38, 2015, ACM, 978-1-4503-3474-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi |
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 95-98, 2015, ACM, 978-1-4503-3474-7. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui |
Employing the mixed FBB/RBB in the design of FinFET logic gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Meng-Chou Chang, Kai-Lun He |
Design of low-power FinFET-based TCAMs with unevenly-segmented matchlines for routing table applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Alireza Shafaei, Yanzhi Wang, Antonio Petraglia, Massoud Pedram |
Design optimization of sense amplifiers using deeply-scaled FinFET devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 280-283, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Saurabh Sinha, Lucian Shifren, Vikas Chandra, Brian Cline, Greg Yeric, Robert C. Aitken, Bingjie Cheng, Andrew R. Brown, Craig Riddet, C. Alexandar, Campbell Millar, Asen Asenov |
Circuit design perspectives for Ge FinFET at 10nm and beyond. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 57-60, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Mohammad Saeed Abrishami, Alireza Shafaei, Yanzhi Wang, Massoud Pedram |
Optimal choice of FinFET devices for energy minimization in deeply-scaled technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 234-238, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
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14 | Roohollah Yarmand, Behzad Ebrahimi, Hassan Afzali-Kusha, Ali Afzali-Kusha, Massoud Pedram |
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 10-17, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Chieh-Yang Chen, Wen-Tsung Huang, Yiming Li 0005 |
Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: Sixteenth International Symposium on Quality Electronic Design, ISQED 2015, Santa Clara, CA, USA, March 2-4, 2015, pp. 61-64, 2015, IEEE, 978-1-4799-7581-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Gurgen Harutyunyan, Grigor Tshagharyan, Yervant Zorian |
Impact of parameter variations on FinFET faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 33rd IEEE VLSI Test Symposium, VTS 2015, Napa, CA, USA, April 27-29, 2015, pp. 1-4, 2015, IEEE Computer Society, 978-1-4799-7597-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Huaxing Tang, Ting-Pu Tai, Wu-Tung Cheng, Brady Benware, Friedrich Hapke |
Diagnosing timing related cell internal defects for FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-6275-4. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Sudeb Dasgupta, Bulusu Anand |
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSID ![In: 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015, pp. 12-13, 2015, IEEE Computer Society, 978-1-4799-6658-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Chia-Liang Tai, Alan Roth, Eric G. Soenen |
A digital low drop-out regulator with wide operating range in a 16nm FinFET CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
A-SSCC ![In: IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015, pp. 1-4, 2015, IEEE, 978-1-4673-7191-9. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
14 | Zoran Jaksic |
Cache memory design in the FinFET era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2015 |
RDF |
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14 | Chun-Yi Lee, Niraj K. Jha |
FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(5), pp. 1150-1163, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Yang Yang, Niraj K. Jha |
FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(12), pp. 2462-2475, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Zia Abbas, Antonio Mastrandrea, Mauro Olivieri |
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(12), pp. 2549-2560, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Ajay N. Bhoj, Niraj K. Jha |
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(3), pp. 548-561, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | K. Keerti Kumar, N. Bheema Rao |
Power gating Technique using FinFET for Minimization of sub-Threshold Leakage Current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(8), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Qian Xie, Renrong Liang, Jing Wang, Libin Liu, Jun Xu |
Nanoscale triple-gate FinFET design considerations based on an analytical model of short-channel effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Inf. Sci. ![In: Sci. China Inf. Sci. 57(4), pp. 1-7, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Sourindra Chaudhuri, Niraj K. Jha |
3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 10(3), pp. 26:1-26:19, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Xianmin Chen, Niraj K. Jha |
Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 11(1), pp. 3:1-3:16, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Sourindra M. Chaudhuri, Prateek Mishra, Niraj K. Jha |
Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 11(2), pp. 19:1-19:20, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Piotr Zajac, Marcin Janicki, Michal Szermer, Andrzej Napieralski |
Evaluating the impact of scaling on temperature in FinFET-technology multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 45(12), pp. 1806-1813, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Arundhati Bhattacharya, Aminul Islam 0002 |
Design and Analysis of Robust Spin Transfer Torque Magnetic Random Access Memory Bitcell Using FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Low Power Electron. ![In: J. Low Power Electron. 10(2), pp. 220-227, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Laurent Artola, Guillaume Hubert, Massimo Alioto |
Comparative soft error evaluation of layout cells in FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(9-10), pp. 2300-2305, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Antonio Calomarde, Esteve Amat, Francesc Moll, Julio Vigara, Antonio Rubio 0001 |
SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(4), pp. 738-745, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang |
Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(4), pp. 698-711, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Hemant Pardeshi, Chandan Kumar Sarkar |
Analysis of flicker and thermal noise in p-channel Underlap DG FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(8), pp. 1549-1554, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Cristina Meinhardt, Alexandra L. Zimpeck, Ricardo A. L. Reis |
Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(9-10), pp. 2319-2324, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Behzad Ebrahimi, Ali Afzali-Kusha, Hamid Mahmoodi |
Robust FinFET SRAM design based on dynamic back-gate voltage adjustment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 54(11), pp. 2604-2612, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Panagiotis Chaourani, Spyridon Nikolaidis 0001 |
A unified CMOS inverter model for planar and FinFET nanoscale technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, pp. 242-245, 2014, IEEE Computer Society, 978-1-4799-4560-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Mark Buckler, Arpan Vaidya, Xiaobin Liu, Wayne P. Burleson |
Dynamic synchronizer flip-flop performance in FinFET technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014, pp. 104-110, 2014, IEEE, 978-1-4799-5347-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | Vimal Kumar Mishra, Rajeev K. Chauhan |
Impact of Ge substrate on drain current of Trigate N-FinFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2014 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2014, Delhi, India, September 24-27, 2014, pp. 1976-1980, 2014, IEEE, 978-1-4799-3078-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Asen Asenov |
Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 44th European Solid State Device Research Conference, ESSDERC 2014, Venice Lido, Italy, September 22-26, 2014, pp. 349-352, 2014, IEEE, 978-1-4799-4378-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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14 | Giulia Piccolo, P. I. Kuindersma, L.-Å. Ragnarsson, Raymond J. E. Hueting, Nadine Collaert, Jurriaan Schmitz |
Silicon LEDs in FinFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSDERC ![In: 44th European Solid State Device Research Conference, ESSDERC 2014, Venice Lido, Italy, September 22-26, 2014, pp. 274-277, 2014, IEEE, 978-1-4799-4378-4. The full citation details ...](Pics/full.jpeg) |
2014 |
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