Search results for "superscalar"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
8	David Wentzlaff, Anant Agarwal	A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation.	FCCM	2004	DBLP DOI BibTeX RDF
8	Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman	Scaling the issue window with look-ahead latency prediction.	ICS	2004	DBLP DOI BibTeX RDF	LHT, MNM, SILO, instruction sorting, CLP
8	Zhenyu Liu, Jiayue Qi	A Novel Rename Register Architecture and Performance Analysis.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
8	Zhigang Hu, Alper Buyuktosunoglu, Viji Srinivasan, Victor V. Zyuban, Hans M. Jacobson, Pradip Bose	Microarchitectural techniques for power gating of execution units.	ISLPED	2004	DBLP DOI BibTeX RDF	execution units, low power, microarchitecture, power-gating
8	Yong-Joon Park, Gyungho Lee	Repairing return address stack for buffer overflow protection.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	computer architecture, computer security, buffer overflow, intrusion tolerance
8	Pedro Chaparro, José González 0002, Antonio González 0001	Thermal-Aware Clustered Microarchitectures.	ICCD	2004	DBLP DOI BibTeX RDF
8	Oguz Ergin, Deniz Balkan, Dmitry V. Ponomarev, Kanad Ghose	Increasing Processor Performance Through Early Register Release.	ICCD	2004	DBLP DOI BibTeX RDF
8	Sriram Nadathur, Akhilesh Tyagi	IPC Driven Dynamic Associative Cache Architecture for Low Energy.	ICCD	2004	DBLP DOI BibTeX RDF
8	Patrick Carribault, Christophe Lemuet, Jean-Thomas Acquaviva, Albert Cohen 0001, William Jalby	Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures.	LCPC	2004	DBLP DOI BibTeX RDF
8	Rama Sangireddy	Register Organization for Enhanced On-Chip Parallelism.	ASAP	2004	DBLP DOI BibTeX RDF
8	Jongmyon Kim, D. Scott Wills	Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems.	ASAP	2004	DBLP DOI BibTeX RDF
8	Deniz Balkan, John Kalamatianos, David R. Kaeli	A Study of Errant Pipeline Flushes Caused by Value Misspeculation.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
8	Amaury Darsch, André Seznec	IATO: A Flexible EPIC Simulation Environment.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
8	Christian Tenllado, Carlos García 0001, Manuel Prieto 0001, Luis Piñuel, Francisco Tirado	Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study.	VECPAR	2004	DBLP DOI BibTeX RDF
8	Bogong Su, Jian Wang 0046, Erh-Wen Hu, Joseph B. Manzano	Software De-Pipelining Technique.	SCAM	2004	DBLP DOI BibTeX RDF
8	Sami Yehia, Olivier Temam	From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation.	ISCA	2004	DBLP DOI BibTeX RDF
8	Lieven Eeckhout, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere, Lizy Kurian John	Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies.	ISCA	2004	DBLP DOI BibTeX RDF
8	Michael L. Behm, John M. Ludden, Yossi Lichtenstein, Michal Rimon, Michael Vinov	Industrial experience with test generation languages for processor verification.	DAC	2004	DBLP DOI BibTeX RDF	test generation, functional verification, processor verification
8	Jack B. Dennis	Fresh Breeze: a multiprocessor chip architecture guided by modular programming principles.	SIGARCH Comput. Archit. News	2003	DBLP DOI BibTeX RDF
8	Christoforos E. Kozyrakis, David A. Patterson 0001	Scalable Vector Processors for Embedded Systems.	IEEE Micro	2003	DBLP DOI BibTeX RDF
8	Nathalie Julien, Johann Laurent, Eric Senn, Eric Martin 0001	Power Consumption Modeling and Characterization of the TI C6201.	IEEE Micro	2003	DBLP DOI BibTeX RDF
8	Chua-Chin Wang, Po-Ming Lee, Jun-Jie Wang, Chenn-Jung Huang	Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
8	Alan Mycroft, Richard Sharp	Higher-level techniques for hardware description and synthesis.	Int. J. Softw. Tools Technol. Transf.	2003	DBLP DOI BibTeX RDF	Static allocation, Behavioural hardware description, High-level synthesis, Functional languages, Hardware/software co-design
8	Giorgio Zoia, Claudio Alberti	A virtual DSP architecture for audio applications from a complexity analysis of MPEG-4 structured audio.	IEEE Trans. Multim.	2003	DBLP DOI BibTeX RDF
8	Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria	A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems.	PATMOS	2003	DBLP DOI BibTeX RDF
8	Yu Bai 0001, R. Iris Bahar	A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors.	ISVLSI	2003	DBLP DOI BibTeX RDF
8	Wei Qin, Sharad Malik	Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation.	DATE	2003	DBLP DOI BibTeX RDF
8	Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin	WaveScalar.	MICRO	2003	DBLP DOI BibTeX RDF
8	Se-Hyun Yang, Babak Falsafi	Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches.	MICRO	2003	DBLP DOI BibTeX RDF
8	Hai Li 0001, Swarup Bhunia, Yiran Chen 0001, T. N. Vijaykumar, Kaushik Roy 0001	Deterministic Clock Gating for Microprocessor Power Reduction.	HPCA	2003	DBLP DOI BibTeX RDF
8	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.	HPCA	2003	DBLP DOI BibTeX RDF
8	Jaeheon Jeong, Michel Dubois 0001	Cost-Sensitive Cache Replacement Algorithms.	HPCA	2003	DBLP DOI BibTeX RDF
8	Ali El-Moursy, David H. Albonesi	Front-End Policies for Improved Issue Efficiency in SMT Processors.	HPCA	2003	DBLP DOI BibTeX RDF
8	Seong-Won Lee, Jean-Luc Gaudiot	Clustered Microarchitecture Simultaneous Multithreading.	Euro-Par	2003	DBLP DOI BibTeX RDF
8	Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería	Counteracting Bank Misprediction in Sliced First-Level Caches.	Euro-Par	2003	DBLP DOI BibTeX RDF
8	Hans Vandierendonck, Hans Logie, Koenraad De Bosschere	Trace Substitution.	Euro-Par	2003	DBLP DOI BibTeX RDF
8	Tao Li 0006, Lizy Kurian John	Run-time modeling and estimation of operating system power consumption.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	low power, operating system, power estimation
8	Won Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain	HiDISC: A Decoupled Architecture for Data-Intensive Application.	IPDPS	2003	DBLP DOI BibTeX RDF	Memory access latency and Speculative pre-execution, Data prefetching, Data-intensive applications, Decoupled architecture
8	David Defour, Florent de Dinechin	Software Carry-Save: A Case Study for Instruction-Level Parallelism.	PaCT	2003	DBLP DOI BibTeX RDF
8	Michael L. Chu, Kevin Fan, Scott A. Mahlke	Region-based hierarchical operation partitioning for multicluster processors.	PLDI	2003	DBLP DOI BibTeX RDF	multicluster processor, operation partitioning, clustering, instruction-level parallelism, instruction scheduling, region-based compilation
8	Miroslav N. Velev	Automatic Abstraction of Equations in a Logic of Equality.	TABLEAUX	2003	DBLP DOI BibTeX RDF
8	Adrián Cristal, Daniel Ortega, Josep Llosa, Mateo Valero	Kilo-instruction Processors.	ISHPC	2003	DBLP DOI BibTeX RDF
8	Madhavi Gopal Valluri, Lizy Kurian John, Heather Hanson	Exploiting compiler-generated schedules for energy savings in high-performance processors.	ISLPED	2003	DBLP DOI BibTeX RDF	dynamic issue processors, very long instruction word architectures, instruction-level parallelism, low energy
8	Andreas Moshovos	Checkpointing alternatives for high performance, power-aware processors.	ISLPED	2003	DBLP DOI BibTeX RDF	checkpointing, power-aware, out-of-order execution, renaming, power density
8	Gurhan Kucuk, Dmitry Ponomarev 0001, Oguz Ergin, Kanad Ghose	Reducing reorder buffer complexity through selective operand caching.	ISLPED	2003	DBLP DOI BibTeX RDF	low-complexity datapath, short-lived values, low-power design, reorder buffer
8	Jaume Abella 0001, Antonio González 0001	On Reducing Register Pressure and Energy in Multiple-Banked Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
8	Sriram Nadathur, Akhilesh Tyagi	A Dependence Driven Efficient Dispatch Scheme.	ICCD	2003	DBLP DOI BibTeX RDF
8	Zhijie Shi, Xiao Yang 0001, Ruby B. Lee	Arbitrary Bit Permutations in One or Two Cycles.	ASAP	2003	DBLP DOI BibTeX RDF
8	Toshinori Sato	Exploiting Instruction Redundancy for Transient Fault Tolerance.	DFT	2003	DBLP DOI BibTeX RDF
8	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.	ISCA	2003	DBLP DOI BibTeX RDF
8	Il Park 0001, Babak Falsafi, T. N. Vijaykumar	Iimplicitly-Multithreaded Processors.	ISCA	2003	DBLP DOI BibTeX RDF
8	André Seznec, Antony Fraboulet	Effective ahead Pipelining of Instruction Block Address Generation.	ISCA	2003	DBLP DOI BibTeX RDF
8	Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French	A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels.	ISCA	2003	DBLP DOI BibTeX RDF
8	Paramjit S. Oberoi, Gurindar S. Sohi	Parallelism in the Front-End.	ISCA	2003	DBLP DOI BibTeX RDF
8	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue.	ISCA	2003	DBLP DOI BibTeX RDF
8	Anoop Iyer, Diana Marculescu	Microarchitecture-level power management.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
8	Andreas Moshovos, Gurindar S. Sohi	Reducing Memory Latency via Read-after-Read Memory Dependence Prediction.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	memory dependence prediction, cache, dynamic optimization, load
8	Marta Jiménez, José M. Llabería, Agustín Fernández	Register tiling in nonrectangular iteration spaces.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	register level, locality, Data reuse, loop optimization, loop tiling
8	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	Energy-Efficient Design of the Reorder Buffer.	PATMOS	2002	DBLP DOI BibTeX RDF
8	Brendon Cahoon, Kathryn S. McKinley	Simple and effective array prefetching in Java.	Java Grande	2002	DBLP DOI BibTeX RDF	array prefetching, Java, static analysis, memory optimization
8	Viji Srinivasan, David M. Brooks, Michael Gschwind, Pradip Bose, Victor V. Zyuban, Philip N. Strenski, Philip G. Emma	Optimizing pipelines for power and performance.	MICRO	2002	DBLP DOI BibTeX RDF
8	Robert S. Chappell, Francis Tseng, Adi Yoaz, Yale N. Patt	Microarchitectural support for precomputation microthreads.	MICRO	2002	DBLP DOI BibTeX RDF
8	Vlad Petric, Anne Bracy, Amir Roth	Three extensions to register integration.	MICRO	2002	DBLP DOI BibTeX RDF
8	Jamison D. Collins, Suleyman Sair, Brad Calder, Dean M. Tullsen	Pointer cache assisted prefetching.	MICRO	2002	DBLP DOI BibTeX RDF
8	Resit Sendag, David J. Lilja, Steven R. Kunkel	Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions.	Euro-Par	2002	DBLP DOI BibTeX RDF
8	Mohamed M. Zahran, Manoj Franklin	A Feasibility Study of Hierarchical Multithreading.	IPDPS	2002	DBLP DOI BibTeX RDF
8	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
8	Gurhan Kucuk, Dmitry Ponomarev 0001, Kanad Ghose	Low-complexity reorder buffer architecture.	ICS	2002	DBLP DOI BibTeX RDF	low-complexity datapath, low-power design, reorder buffer
8	Juan L. Aragón, José González 0002, Antonio González 0001, James E. Smith 0001	Dual path instruction processing.	ICS	2002	DBLP DOI BibTeX RDF	branch misprediction penalty, dual path processing, pre-scheduling, confidence estimation
8	Anoop Iyer, Diana Marculescu	Power efficiency of voltage scaling in multiple clock, multiple voltage cores.	ICCAD	2002	DBLP DOI BibTeX RDF
8	Oliverio J. Santana, Ayose Falcón, Enrique Fernández, Pedro Medina, Alex Ramírez, Mateo Valero	A Comprehensive Analysis of Indirect Branch Prediction.	ISHPC	2002	DBLP DOI BibTeX RDF	indirect branch, Multi-Stage Cascaded Predictor, branch prediction, microarchitecture, Branch Target Buffer
8	Dana S. Henry, Gabriel H. Loh, Rahul Sami	Speculative Clustered Caches for Clustered Processors.	ISHPC	2002	DBLP DOI BibTeX RDF
8	Michael C. Huang 0001, Jose Renau, Josep Torrellas	Energy-efficient hybrid wakeup logic.	ISLPED	2002	DBLP DOI BibTeX RDF	wakeup logic, low power, issue logic
8	Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev 0001	A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.	ICCD	2002	DBLP DOI BibTeX RDF
8	Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen	Trace Cache Performance Parameters.	ICCD	2002	DBLP DOI BibTeX RDF
8	Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen	A Mathematical Model of Trace Cache.	ASAP	2002	DBLP DOI BibTeX RDF
8	Mark D. Aagaard, Nancy A. Day, Meng Lou	Relating Multi-step and Single-Step Microprocessor Correctness Statements.	FMCAD	2002	DBLP DOI BibTeX RDF
8	Alex Pajuelo, Antonio González 0001, Mateo Valero	Speculative Dynamic Vectorization.	ISCA	2002	DBLP DOI BibTeX RDF	Speculative dynamic vectorization, wide buses, speculative data computation, control independence, vector instructions
8	André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides	Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor.	ISCA	2002	DBLP DOI BibTeX RDF	EV8 processor, Branch Prediction
8	Anoop Iyer, Diana Marculescu	Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors.	ISCA	2002	DBLP DOI BibTeX RDF
8	Michael Sung, Ronny Krashinsky, Krste Asanovic	Multithreading decoupled architectures for complexity-effective general purpose computing.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF
8	Jinsuo Zhang	The predictability of load address.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	context predictor, global context predictor, last address predictor, load address prediction, stack coloring, stride predictor, program behavior, hybrid predictor
8	Rolf B. Hilgendorf, Wolfram Sauer	Instruction translation for an experimental S/390 processor.	SIGARCH Comput. Archit. News	2001	DBLP DOI BibTeX RDF	IBM System/390
8	Ulrich Sigmund, Theo Ungerer	Die Multimediafaehigkeit von mehrfaedig superskalaren Prozessoren am Beispiel der MPEG-2-Decodierung.	Inform. Forsch. Entwickl.	2001	DBLP DOI BibTeX RDF	Mehrfädig superskalar, Superskalarprozessor, Multimediaprozessor, Multimediaeinheit, Videodecodierung, MPEG-2
8	Chi-Keung Luk, Todd C. Mowry	Architectural and compiler support for effective instruction prefetching: a cooperative approach.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	compiler optimization, instruction prefetching
8	David López 0001, Josep Llosa, Mateo Valero, Eduard Ayguadé	Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	numerical applications, performance/cost trade-off, instruction level parallelism, software pipelining, VLIW processors
8	Mahmut T. Kandemir, J. Ramanujam	Data Relation Vectors: A New Abstraction for Data Optimizations.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	compiler optimizations for memory hierarchy, reuse vectors, data relation vectors, loop transformations, Data reuse, cache locality, memory layouts
8	Sangyeun Cho, Pen-Chung Yew, Gyungho Lee	A High-Bandwidth Memory Pipeline for Wide Issue Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Data bandwidth, runtime stack, data stream partitioning, multiported data cache, instruction level parallelism, data locality
8	Daniel Kästner, Sebastian Winkel	ILP-based Instruction Scheduling for IA-64.	LCTES/OM	2001	DBLP DOI BibTeX RDF
8	Jesús Corbal, Roger Espasa, Mateo Valero	On the Efficiency of Reductions in µ-SIMD Media Extensions.	IEEE PACT	2001	DBLP DOI BibTeX RDF
8	Miroslav N. Velev, Randal E. Bryant	EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations.	CAV	2001	DBLP DOI BibTeX RDF
8	Sriram Padmanabhan, Timothy Malkemus, Ramesh C. Agarwal, Anant Jhingran	Block Oriented Processing of Relational Database Operations in Modern Computer Architectures.	ICDE	2001	DBLP DOI BibTeX RDF
8	Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan	Applying Caching to Two-Level Adaptive Branch Prediction.	DSD	2001	DBLP DOI BibTeX RDF	Two-level Adaptive Branch Predictors, Cached Correlated Branch Predictors, Prediction Cache
8	Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta	Performance characterization of a hardware mechanism for dynamic optimization.	MICRO	2001	DBLP DOI BibTeX RDF
8	Juan L. Aragón, José González 0002, José M. García 0001, Antonio González 0001	Confidence Estimation for Branch Prediction Reversal.	HiPC	2001	DBLP DOI BibTeX RDF
8	Aneesh Aggarwal, Manoj Franklin	Putting Data Value Predictors to Work in Fine-Grain Parallel Processors.	HiPC	2001	DBLP DOI BibTeX RDF
8	Soner Önder, Rajiv Gupta 0001	Instruction Wake-Up in Wide Issue Superscalars.	Euro-Par	2001	DBLP DOI BibTeX RDF
8	Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec	Topic 08+13: Instruction-Level Parallelism and Computer Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
8	M. Anton Ertl, David Gregg	The Behavior of Efficient Virtual Machine Interpreters on Modern Architectures.	Euro-Par	2001	DBLP DOI BibTeX RDF
8	Toshinori Sato, Itsujiro Arita	Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse.	Euro-Par	2001	DBLP DOI BibTeX RDF