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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 16149 publication records. Showing 16145 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Marek Jersak, Kai Richter 0001, Rafik Henia, Rolf Ernst, Frank Slomka |
Transformation of SDL specifications for system-level timing analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002, pp. 121-126, 2002, ACM, 1-58113-542-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SDL |
19 | Larry McMurchie, Carl Sechen |
WTA: waveform-based timing analysis for deep submicron circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 625-631, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Aloysius K. Mok, Chan-Gun Lee, Honguk Woo, Prabhudev Konana |
The Monitoring of Timing Constraints on Time Intervals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS'02), Austin, Texas, USA, December 3-5, 2002, pp. 191-200, 2002, IEEE Computer Society, 0-7695-1851-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Yasuo Matsubara, Takahiro Shakushi |
The Effects of Timing Dependence and Recursion on Parallel Program Schemata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 4th International Symposium, ISHPC 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings, pp. 291-300, 2002, Springer, 3-540-43674-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long |
Static timing analysis based circuit-limited-yield estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 81-84, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Konstantinos Doris, Arthur H. M. van Roermund, Domine Leenaerts |
A general analysis on the timing jitter in D/A converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 117-120, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | J. B. Miller, John C. McEachen, Herschel H. Loomis Jr., Michael A. Tope, D. B. Copeland |
An analysis of noise in timing-based communications over local area networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 1-4, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Richard A. Kemmerer |
A Practical Approach to Identifying Storage and Timing Channels: Twenty Years Later. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACSAC ![In: 18th Annual Computer Security Applications Conference (ACSAC 2002), 9-13 December 2002, Las Vegas, NV, USA, pp. 109-118, 2002, IEEE Computer Society, 0-7695-1828-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Alan Grigg, Neil C. Audsley |
Reservation-Based Timing Analysis -A Practical Engineering Approach for Distributed Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 8th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2001), 17-20 April 2001, Washington, DC, USA, pp. 103-110, 2001, IEEE Computer Society, 0-7695-1086-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Emilio Vivancos, Christopher A. Healy, Frank Mueller 0001, David B. Whalley |
Parametric Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 88-93, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Xuandong Li, Cui Meng, Yu Pei 0001, Jianhua Zhao, Guoliang Zheng |
Timing Analysis of UML Activity Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UML ![In: «UML» 2001 - The Unified Modeling Language, Modeling Languages, Concepts, and Tools, 4th International Conference, Toronto, Canada, October 1-5, 2001, Proceedings, pp. 62-75, 2001, Springer, 3-540-42667-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Paul Kartschoke, Stephen F. Geissler |
Timing Driven Wiring on an Advanced Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 408-413, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Nina Amla, E. Allen Emerson, Kedar S. Namjoshi, Richard J. Trefler |
Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for the Construction and Analysis of Systems, 7th International Conference, TACAS 2001 Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2001 Genova, Italy, April 2-6, 2001, Proceedings, pp. 465-479, 2001, Springer, 3-540-41865-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri |
Timing Verification and Delay Test Generation for Hierarchical Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 157-162, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Timing optimization on routed designs with incremental placementand routing characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2), pp. 188-196, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Kenneth J. Turner, F. Javier Argul-Marin, Stephen D. Laing |
Concurrent Specification and Timing Analysis of Digital Hardware Using SDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 1001-1008, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Chris Dick, Fred Harris 0001, Michael Rice |
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 195-204, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Tong Xiao, Malgorzata Marek-Sadowska |
Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 115-120, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi |
TACO: timing analysis with coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 266-269, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Sung-Kwan Kim, Sang Lyul Min, Rhan Ha |
Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 20th IEEE Real-Time Systems Symposium, Phoenix, AZ, USA, December 1-3, 1999, pp. 22-31, 1999, IEEE Computer Society, 0-7695-0475-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
real-time systems, WCET analysis |
19 | Costas Mourlas, David A. Duce, Michael D. Wilson |
On Satisfying Timing and Resource Constraints in Distributed Multimedia Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMCS, Vol. 2 ![In: IEEE International Conference on Multimedia Computing and Systems, ICMCS 1999, Florence, Italy, June 7-11, 1999. Volume II, pp. 16-20, 1999, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Real-Time Synchronization, Quality of Service, Resource Management, Real-Time Constraints, Distributed Multimedia Systems |
19 | Lorraine E. P. Rice, Albert Mo Kim Cheng |
Timing Analysis of the X-38 Space Station Crew Return Vehicle Avionics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real Time Technology and Applications Symposium ![In: Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium, RTAS'99, Vancouver, British Columbia, Canada, June 2-4, 1999, pp. 255-, 1999, IEEE Computer Society, 0-7695-0194-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Yi-Kan Cheng, Sung-Mo Kang |
Temperature-driven power and timing analysis for CMOS ULSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 214-217, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Miodrag Potkonjak, Mani B. Srivastava |
Behavioral optimization using the manipulation of timing constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10), pp. 936-947, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Thomas Lundqvist, Per Stenström |
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES'98, Montreal, Canada, June 1998, Proceedings, pp. 1-15, 1998, Springer, 3-540-65075-X. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Jonathan T. Trostle |
Timing Attacks Against Trusted Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
S&P ![In: Security and Privacy - 1998 IEEE Symposium on Security and Privacy, Oakland, CA, USA, May 3-6, 1998, Proceedings, pp. 125-134, 1998, IEEE Computer Society, 0-8186-8386-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey |
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 184-193, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Yuji Kukimoto, Robert K. Brayton |
Hierarchical Functional Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 580-585, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Anmol Mathur, C. L. Liu 0001 |
Timing-driven placement for regular architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(6), pp. 597-608, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Marios Mavronicolas, Marina Papatriantafilou, Philippas Tsigas |
The Impact of Timing on Linearizability in Counting Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: 11th International Parallel Processing Symposium (IPPS '97), 1-5 April 1997, Geneva, Switzerland, Proceedings, pp. 684-688, 1997, IEEE Computer Society, 0-8186-7792-9. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Rolf Ernst, Wei Ye 0002 |
Embedded program timing analysis based on path clustering and architecture classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 598-604, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Christopher G. Knight, Adit D. Singh, Victor P. Nelson |
An IDDQ Sensor for Concurrent Timing Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France, pp. 281-289, 1997, IEEE Computer Society, 0-8186-8168-3. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik |
Effective Heuristics for Timing Driven Constructive Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 38-45, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Chanhee Oh, M. Ray Mercer |
Efficient logic-level timing analysis using constraint-guided critical path search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(3), pp. 346-355, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Yves Blaquière, Michel R. Dagenais, Yvon Savaria |
Timing analysis speed-up using a hierarchical and a multimode approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2), pp. 244-255, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
19 | Lo Ko, David B. Whalley, Marion G. Harmon |
Supporting User-Friendly Analysis of Timing Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, & Tools for Real-Time Systems ![In: Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, Compilers, & Tools for Real-Time Systems (LCT-RTS 1995). La Jolla, California, USA, June 21-22, 1995, pp. 99-107, 1995, ACM. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Henrik Hulgaard, Steven M. Burns |
Efficient Timing Analysis of a Class of Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 7th International Conference, Liège, Belgium, July, 3-5, 1995, Proceedings, pp. 423-436, 1995, Springer, 3-540-60045-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang |
Certified timing verification and the transition delay of a logic circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(3), pp. 333-342, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | C. Thomas Gray, Wentai Liu, Ralph K. Cavin III |
Timing constraints for wave-pipelined systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), pp. 987-1004, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee |
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 190-194, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Meng-Lin Yu, Bryan D. Ackland |
VLSI timing simulation with selective dynamic regionization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 195-199, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | John R. Feehrer, Harry F. Jordan |
Timing uncertainty analysis for time-of-flight systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 728-735, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | David C. Ku, Giovanni De Micheli |
Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6), pp. 696-718, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Wolf-Dieter Tiedemann |
Bus Protocol Conversion: from Timing Diagrams to State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST'91, A Selection of Papers from the Second International Workshop on Computer Aided Systems Theory, Krems, Austria, April 15-19, 1991, Proceedings, pp. 365-377, 1991, Springer, 3-540-55354-1. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
19 | Robert Tjärnström |
Automatic generation of timing specifications for CMOS transistor subnetworks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 524-528, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | P. A. Subrahmanyam |
What's in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hardware Specification, Verification and Synthesis ![In: Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings, pp. 202-223, 1989, Springer, 3-540-97226-9. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Sally A. Hayati, Alice C. Parker |
Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 75-80, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | James J. Cherry |
Pearl: A CMOS Timing Analyzer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 148-153, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
19 | H. C. Yen, Subbarao Ghanta, David Hung-Chang Du |
A Path Selection Algorithm for Timing Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988., pp. 720-723, 1988, ACM. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP BibTeX RDF |
|
19 | Mario Barbacci, Jeannette M. Wing |
Specifying Functional and Timing Behavior for Real-Time Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARLE (2) ![In: PARLE, Parallel Architectures and Languages Europe, Volume II: Parallel Languages, Eindhoven, The Netherlands, June 15-19, 1987, Proceedings, pp. 124-140, 1987, Springer, 3-540-17945-3. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Sumit Ghosh |
A rule-based approach to unifying functional and fault simulation and timing verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, USA, June, 1986., pp. 677-682, 1986, IEEE Computer Society Press. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
19 | Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin 0001 |
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 56(2-3), pp. 167-186, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Prototyping, Refinement, High-level synthesis, Design space exploration, System level design |
19 | Pei-Hsin Ho |
Industrial clock design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 139-140, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
low power, variability, physical design, clock tree synthesis |
19 | Kwangok Jeong, Andrew B. Kahng, Hailong Yao |
Revisiting the linear programming framework for leakage power vs. performance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 127-134, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Marios Mavronicolas, Michael Merritt, Gadi Taubenfeld |
Sequentially consistent versus linearizable counting networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Distributed Comput. ![In: Distributed Comput. 21(4), pp. 249-269, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Balancing networks, Inconsistency fractions, Sequential consistency, Linearizability, Counting networks |
19 | Parham Geramifar, Mohammad Reza Ay, Mojtaba Shamsaei Zafarghandi, George Loudos, Arman Rahmim |
Monte Carlo assessment of time-of-flight benefits on the LYSO-based discovery RX PET/CT scanner. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBI ![In: Proceedings of the 2008 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, Paris, France, May 14-17, 2008, pp. 364-367, 2008, IEEE, 978-1-4244-2003-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Bao Liu 0001 |
Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 527-532, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Vahid Garousi |
Traffic-aware Stress Testing of Distributed Real-Time Systems Based on UML Models in the Presence of Time Uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICST ![In: First International Conference on Software Testing, Verification, and Validation, ICST 2008, Lillehammer, Norway, April 9-11, 2008, pp. 92-101, 2008, IEEE Computer Society, 978-0-7695-3127-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Time Uncertainty, UML, Distributed Real-Time Systems, Stress Testing |
19 | Guenter Khyo, Peter P. Puschner, Martin Delvai |
An Operating System for a Time-Predictable Computing Node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEUS ![In: Software Technologies for Embedded and Ubiquitous Systems, 6th IFIP WG 10.2 International Workshop, SEUS 2008, Anacarpi, Capri Island, Italy, October 1-3, 2008, Proceedings, pp. 150-161, 2008, Springer, 978-3-540-87784-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Temporal Predictability, Determinism, Real-Time Operating Systems, Time-Triggered Architecture |
19 | Daxian Yun, Yanjie Peng, Jun Han 0003, Xiaoyang Zeng |
Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2490-2493, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001 |
Multiple Coupling Effects Oriented Path Delay Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 383-388, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
crosstalk, delay test, path delay fault |
19 | Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor |
Test-Pattern Grading and Pattern Selection for Small-Delay Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 233-239, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Small-delay defects, pattern grading, pattern selection, ATPG |
19 | Shanna-Shaye Forbes, Hiren D. Patel, Edward A. Lee, Hugo A. Andrade |
An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DS-RT ![In: 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications, 27-29 October 2008, Vancouver, BC, Canada, Proceedings, pp. 322-325, 2008, IEEE Computer Society, 978-0-7695-3425-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Yan Lin 0001, Lei He 0001 |
Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 636-641, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Huan Ren, Shantanu Dutt |
Constraint satisfaction in incremental placement with application to performance optimization under power constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 251-258, 2007, IEEE, 1-4244-1258-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Guilan Dai, Xiaoying Bai, Chongchong Zhao |
A Framework for Time Consistency Verification for Web Processes Based on Annotated OWL-S. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GCC ![In: Grid and Cooperative Computing, Sixth International Conference on Grid and Cooperative Computing, GCC 2007, August 16-18, 2007, Urumchi, Xinjiang, China, Proceedings, pp. 346-353, 2007, IEEE Computer Society, 0-7695-2871-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Vineet Wason, Rajeev Murgai, William W. Walker |
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 271-277, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Suleman Surti, Joel S. Karp, Lucretiu M. Popescu, Margaret E. Daube-Witherspoon, Matthew E. Werner |
Investigation of time-of-flight benefit for fully 3-DPET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Medical Imaging ![In: IEEE Trans. Medical Imaging 25(5), pp. 529-538, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Xianfeng Li, Abhik Roychoudhury, Tulika Mitra |
Modeling out-of-order processors for WCET analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Real Time Syst. ![In: Real Time Syst. 34(3), pp. 195-227, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache |
19 | Shige Wang, Kang G. Shin |
Task Construction for Model-Based Design of Embedded Control Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 32(4), pp. 254-264, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Task construction, model transformation, embedded software, model-based design |
19 | Ad M. G. Peeters |
Clockless IC design using handshake technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006, pp. 169, 2006, ACM, 1-59593-299-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | June J. Skelly |
Temporal interface designs for modeling and simulation: reducing display clutter by temporal fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the Winter Simulation Conference WSC 2006, Monterey, California, USA, December 3-6, 2006, pp. 1210-1215, 2006, IEEE Computer Society, 1-4244-0501-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Leonard Lee, Li-C. Wang |
On bounding the delay of a critical path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 81-88, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | I-De Huang, Sandeep K. Gupta 0001 |
Selection of Paths for Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 208-215, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Ghassan Kbar, Wathiq Mansoor |
Mobile Station Location Based on Hybrid of Signal Strength and Time of Arrival. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMB ![In: 2005 International Conference on Mobile Business (ICMB 2005), 11-13 July 2005, Sydney, Australia, pp. 585-591, 2005, IEEE Computer Society, 0-7695-2367-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
MS positioning, Wireless, GSM |
19 | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004, pp. 611-618, 2004, IEEE Computer Society / ACM, 0-7803-8702-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Junhyung Um, Taewhan Kim |
Synthesis of arithmetic circuits considering layout effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11), pp. 1487-1503, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Li-Da Huang, Hung-Ming Chen, D. F. Wong 0001 |
Global Wire Bus Configuration with Minimum Delay Uncertainty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10050-10055, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Insik Shin, Insup Lee 0001 |
Periodic Resource Model for Compositional Real-Time Guarantees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 24th IEEE Real-Time Systems Symposium (RTSS 2003), 3-5 December 2003, Cancun, Mexico, pp. 2-13, 2003, IEEE Computer Society, 0-7695-2044-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng |
On theoretical and practical considerations of path selection for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 94-100, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Junhyung Um, Taewhan Kim |
Layout-aware synthesis of arithmetic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 207-212, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
layout, high performance, carry-save-adder |
19 | Juan Zamorano, José F. Ruiz, Juan Antonio de la Puente |
Implementing Ada.Real_Time.Clock and Absolute Delays in Real-Time Kernels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ada-Europe ![In: Reliable Software Technologies: Ada Europe 2001, 6th Ade-Europe International Conference Leuven, Belgium, May 14-18, 2001, Proceedings, pp. 317-327, 2001, Springer, 3-540-42123-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Irina B. Virbitskaite, E. Pokozy |
Parametric Behaviour Analysis for Time Petri Nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 5th International Conference, PaCT-99, St. Petersburg, Russia, September 6-10, 1999, Proceedings, pp. 134-140, 1999, Springer, 3-540-66363-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Karl-Heinz Zimmermann |
A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 17(1), pp. 21-41, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Karl-Heinz Zimmermann, Wolfgang Achtziger |
Finding Space-Time Transformations for Uniform Recurrences via Branching Parametric Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 15(3), pp. 259-274, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Shangping Ren, Gul Agha |
RTsynchronizer: Language Support for Real-Time Specifications in Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Languages, Compilers, & Tools for Real-Time Systems ![In: Proceedings of the ACM SIGPLAN 1995 Workshop on Languages, Compilers, & Tools for Real-Time Systems (LCT-RTS 1995). La Jolla, California, USA, June 21-22, 1995, pp. 50-59, 1995, ACM. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
19 | David K. Probst, Hon Fung Li |
Verifying Timed Behavior Automata with Input/Output Critical Races. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 5th International Conference, CAV '93, Elounda, Greece, June 28 - July 1, 1993, Proceedings, pp. 424-437, 1993, Springer, 3-540-56922-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Balasubramanya Bhat, Frank Mueller 0001 |
Making DRAM Refresh Predictable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECRTS ![In: 22nd Euromicro Conference on Real-Time Systems, ECRTS 2010, Brussels, Belgium, July 6-9, 2010, pp. 145-154, 2010, IEEE Computer Society, 978-0-7695-4111-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
DRAM Refresh, Real-Time Systems, Timing Analysis, DRAM, Worst-Case Execution Time, Timing Predictability |
19 | Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta |
Accelerating Synchronous Sequential Circuits Using an Adaptive Clock. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2010: 23rd International Conference on VLSI Design, 9th International Conference on Embedded Systems, Bangalore, India, 3-7 January 2010, pp. 176-181, 2010, IEEE Computer Society, 978-0-7695-3928-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
VLSI, CAD, delays, Timing, sequential circuits, Timing optimization |
19 | Ali Dasdan |
Provably efficient algorithms for resolving temporal and spatial difference constraint violations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(1), pp. 8:1-8:24, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
interface timing, layout compaction, scheduling, real-time systems, constraint satisfaction, timing constraints, Behavioral synthesis, multimedia synchronization, rate analysis |
19 | Susanne Graf, Ileana Ober, Iulian Ober |
A real-time profile for UML. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Softw. Tools Technol. Transf. ![In: Int. J. Softw. Tools Technol. Transf. 8(2), pp. 113-127, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Real-time profile, Modeling, Real-time systems, UML, Formal verification, Timing analysis, OMEGA, Timing properties |
19 | Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001 |
A practical clock tree synthesis for semi-synchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000, pp. 159-164, 2000, ACM, 1-58113-191-7. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling |
19 | Stephen H. Unger |
Hazards, Critical Races, and Metastability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(6), pp. 754-768, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
critical race, dynamic hazards, essential hazards, inertial delays, pure delays, sequential logic, timing problems, delays, Asynchronous, metastability, timing simulation |
17 | Guihai Yan, Yinhe Han 0001, Xiaowei Li 0001 |
ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 60(9), pp. 1219-1232, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Lifetime reliability, aging sensor, self-adaptive, NBTI, timing adaptation |
17 | JingZheng Wu, Liping Ding, Yongji Wang 0002, Wei Han |
Identification and Evaluation of Sharing Memory Covert Timing Channel in Xen Virtual Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE CLOUD ![In: IEEE International Conference on Cloud Computing, CLOUD 2011, Washington, DC, USA, 4-9 July, 2011, pp. 283-291, 2011, IEEE Computer Society, 978-1-4577-0836-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Channel Identification, Channel Scenario Construction, Channel Performance Evaluation, Cloud Computing, Xen, Covert Timing Channel |
17 | Yit Kwong Chin, Lai Kuan Lee, Nurmin Bolong, Soo Siang Yang, Kenneth Tze Kin Teo |
Exploring Q-Learning Optimization in Traffic Signal Timing Plan Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CICSyN ![In: Third International Conference on Computational Intelligence, Communication Systems and Networks, CICSyN 2011, Bali, Indonesia, 26-28 July, 2011, pp. 269-274, 2011, IEEE Computer Society, 978-1-4577-0975-3. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Traffic Signal Timing Plan, Traffic Flow Control, Q-Learning |
17 | Haile Yu, Qiang Xu 0001, Philip Heng Wai Leong |
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 539-544, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
Architectural Symmetry, LE swap, FPGA, Timing Yield |
17 | Wen-Chang Hsu, Shih-Hao Hung, Chia-Heng Tu |
A Virtual Timing Device for Program Performance Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 2255-2260, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance evaluation, embedded system, functional simulation, virtual platform, Timing estimation |
17 | Haibo Zeng 0001, Arkadeb Ghosal, Marco Di Natale |
Timing Analysis and Optimization of FlexRay Dynamic Segment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: 10th IEEE International Conference on Computer and Information Technology, CIT 2010, Bradford, West Yorkshire, UK, June 29-July 1, 2010, pp. 1932-1939, 2010, IEEE Computer Society, 978-0-7695-4108-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Scheduling, Timing Analysis, FlexRay |
17 | Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele |
Timing Analysis for TDMA Arbitration in Resource Sharing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: 16th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2010, Stockholm, Sweden, April 12-15, 2010, pp. 215-224, 2010, IEEE Computer Society, 978-0-7695-4001-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
Worst-Case Timing Analysis, Real-Time Systems, Time Division Multiple Access (TDMA) |
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