Search results for "timing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Marek Jersak, Kai Richter 0001, Rafik Henia, Rolf Ernst, Frank Slomka	Transformation of SDL specifications for system-level timing analysis.	CODES	2002	DBLP DOI BibTeX RDF	SDL
19	Larry McMurchie, Carl Sechen	WTA: waveform-based timing analysis for deep submicron circuits.	ICCAD	2002	DBLP DOI BibTeX RDF
19	Aloysius K. Mok, Chan-Gun Lee, Honguk Woo, Prabhudev Konana	The Monitoring of Timing Constraints on Time Intervals.	RTSS	2002	DBLP DOI BibTeX RDF
19	Yasuo Matsubara, Takahiro Shakushi	The Effects of Timing Dependence and Recursion on Parallel Program Schemata.	ISHPC	2002	DBLP DOI BibTeX RDF
19	Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long	Static timing analysis based circuit-limited-yield estimation.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Konstantinos Doris, Arthur H. M. van Roermund, Domine Leenaerts	A general analysis on the timing jitter in D/A converters.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
19	J. B. Miller, John C. McEachen, Herschel H. Loomis Jr., Michael A. Tope, D. B. Copeland	An analysis of noise in timing-based communications over local area networks.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
19	Richard A. Kemmerer	A Practical Approach to Identifying Storage and Timing Channels: Twenty Years Later.	ACSAC	2002	DBLP DOI BibTeX RDF
19	Alan Grigg, Neil C. Audsley	Reservation-Based Timing Analysis -A Practical Engineering Approach for Distributed Real-Time Systems.	ECBS	2001	DBLP DOI BibTeX RDF
19	Emilio Vivancos, Christopher A. Healy, Frank Mueller 0001, David B. Whalley	Parametric Timing Analysis.	LCTES/OM	2001	DBLP DOI BibTeX RDF
19	Xuandong Li, Cui Meng, Yu Pei 0001, Jianhua Zhao, Guoliang Zheng	Timing Analysis of UML Activity Diagrams.	UML	2001	DBLP DOI BibTeX RDF
19	Paul Kartschoke, Stephen F. Geissler	Timing Driven Wiring on an Advanced Microprocessor.	DSD	2001	DBLP DOI BibTeX RDF
19	Nina Amla, E. Allen Emerson, Kedar S. Namjoshi, Richard J. Trefler	Assume-Guarantee Based Compositional Reasoning for Synchronous Timing Diagrams.	TACAS	2001	DBLP DOI BibTeX RDF
19	Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri	Timing Verification and Delay Test Generation for Hierarchical Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
19	Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Timing optimization on routed designs with incremental placementand routing characterization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Kenneth J. Turner, F. Javier Argul-Marin, Stephen D. Laing	Concurrent Specification and Timing Analysis of Digital Hardware Using SDL.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
19	Chris Dick, Fred Harris 0001, Michael Rice	Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
19	Tong Xiao, Malgorzata Marek-Sadowska	Worst Delay Estimation in Crosstalk Aware Static Timing Analysis.	ICCD	2000	DBLP DOI BibTeX RDF
19	Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi	TACO: timing analysis with coupling.	DAC	2000	DBLP DOI BibTeX RDF
19	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis.	RTSS	1999	DBLP DOI BibTeX RDF	real-time systems, WCET analysis
19	Costas Mourlas, David A. Duce, Michael D. Wilson	On Satisfying Timing and Resource Constraints in Distributed Multimedia Systems.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF	Real-Time Synchronization, Quality of Service, Resource Management, Real-Time Constraints, Distributed Multimedia Systems
19	Lorraine E. P. Rice, Albert Mo Kim Cheng	Timing Analysis of the X-38 Space Station Crew Return Vehicle Avionics.	IEEE Real Time Technology and Applications Symposium	1999	DBLP DOI BibTeX RDF
19	Yi-Kan Cheng, Sung-Mo Kang	Temperature-driven power and timing analysis for CMOS ULSI circuits.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
19	Miodrag Potkonjak, Mani B. Srivastava	Behavioral optimization using the manipulation of timing constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
19	Thomas Lundqvist, Per Stenström	Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques.	LCTES	1998	DBLP DOI BibTeX RDF
19	Jonathan T. Trostle	Timing Attacks Against Trusted Path.	S&P	1998	DBLP DOI BibTeX RDF
19	Jonathan T.-Y. Chang, Chao-Wen Tseng, Chien-Mo James Li, Mike Purtell, Edward J. McCluskey	Analysis of pattern-dependent and timing-dependent failures in an experimental test chip.	ITC	1998	DBLP DOI BibTeX RDF
19	Yuji Kukimoto, Robert K. Brayton	Hierarchical Functional Timing Analysis.	DAC	1998	DBLP DOI BibTeX RDF
19	Anmol Mathur, C. L. Liu 0001	Timing-driven placement for regular architectures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
19	Marios Mavronicolas, Marina Papatriantafilou, Philippas Tsigas	The Impact of Timing on Linearizability in Counting Networks.	IPPS	1997	DBLP DOI BibTeX RDF
19	Rolf Ernst, Wei Ye 0002	Embedded program timing analysis based on path clustering and architecture classification.	ICCAD	1997	DBLP DOI BibTeX RDF
19	Christopher G. Knight, Adit D. Singh, Victor P. Nelson	An IDDQ Sensor for Concurrent Timing Error Detection.	DFT	1997	DBLP DOI BibTeX RDF
19	R. V. Raj, N. S. Murty, P. S. Nagendra Rao, Lalit M. Patnaik	Effective Heuristics for Timing Driven Constructive Placement.	VLSI Design	1997	DBLP DOI BibTeX RDF
19	Chanhee Oh, M. Ray Mercer	Efficient logic-level timing analysis using constraint-guided critical path search.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
19	Yves Blaquière, Michel R. Dagenais, Yvon Savaria	Timing analysis speed-up using a hierarchical and a multimode approach.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
19	Lo Ko, David B. Whalley, Marion G. Harmon	Supporting User-Friendly Analysis of Timing Constraints.	Workshop on Languages, Compilers, & Tools for Real-Time Systems	1995	DBLP DOI BibTeX RDF
19	Henrik Hulgaard, Steven M. Burns	Efficient Timing Analysis of a Class of Petri Nets.	CAV	1995	DBLP DOI BibTeX RDF
19	Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang	Certified timing verification and the transition delay of a logic circuit.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
19	C. Thomas Gray, Wentai Liu, Ralph K. Cavin III	Timing constraints for wave-pipelined systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
19	Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee	Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics.	ICCAD	1994	DBLP DOI BibTeX RDF
19	Meng-Lin Yu, Bryan D. Ackland	VLSI timing simulation with selective dynamic regionization.	ICCAD	1994	DBLP DOI BibTeX RDF
19	John R. Feehrer, Harry F. Jordan	Timing uncertainty analysis for time-of-flight systems.	ICCAD	1994	DBLP DOI BibTeX RDF
19	David C. Ku, Giovanni De Micheli	Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
19	Wolf-Dieter Tiedemann	Bus Protocol Conversion: from Timing Diagrams to State Machines.	EUROCAST	1991	DBLP DOI BibTeX RDF
19	Robert Tjärnström	Automatic generation of timing specifications for CMOS transistor subnetworks.	EURO-DAC	1990	DBLP DOI BibTeX RDF
19	P. A. Subrahmanyam	What's in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous Components.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
19	Sally A. Hayati, Alice C. Parker	Automatic Production of Controller Specifications from Control and Timing Behavioral Descriptions.	DAC	1989	DBLP DOI BibTeX RDF
19	James J. Cherry	Pearl: A CMOS Timing Analyzer.	DAC	1988	DBLP BibTeX RDF
19	H. C. Yen, Subbarao Ghanta, David Hung-Chang Du	A Path Selection Algorithm for Timing Analysis.	DAC	1988	DBLP BibTeX RDF
19	Mario Barbacci, Jeannette M. Wing	Specifying Functional and Timing Behavior for Real-Time Applications.	PARLE (2)	1987	DBLP DOI BibTeX RDF
19	Sumit Ghosh	A rule-based approach to unifying functional and fault simulation and timing verification.	DAC	1986	DBLP DOI BibTeX RDF
19	Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin 0001	Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Prototyping, Refinement, High-level synthesis, Design space exploration, System level design
19	Pei-Hsin Ho	Industrial clock design.	ISPD	2009	DBLP DOI BibTeX RDF	low power, variability, physical design, clock tree synthesis
19	Kwangok Jeong, Andrew B. Kahng, Hailong Yao	Revisiting the linear programming framework for leakage power vs. performance optimization.	ISQED	2009	DBLP DOI BibTeX RDF
19	Marios Mavronicolas, Michael Merritt, Gadi Taubenfeld	Sequentially consistent versus linearizable counting networks.	Distributed Comput.	2008	DBLP DOI BibTeX RDF	Balancing networks, Inconsistency fractions, Sequential consistency, Linearizability, Counting networks
19	Parham Geramifar, Mohammad Reza Ay, Mojtaba Shamsaei Zafarghandi, George Loudos, Arman Rahmim	Monte Carlo assessment of time-of-flight benefits on the LYSO-based discovery RX PET/CT scanner.	ISBI	2008	DBLP DOI BibTeX RDF
19	Bao Liu 0001	Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression.	DATE	2008	DBLP DOI BibTeX RDF
19	Vahid Garousi	Traffic-aware Stress Testing of Distributed Real-Time Systems Based on UML Models in the Presence of Time Uncertainty.	ICST	2008	DBLP DOI BibTeX RDF	Time Uncertainty, UML, Distributed Real-Time Systems, Stress Testing
19	Guenter Khyo, Peter P. Puschner, Martin Delvai	An Operating System for a Time-Predictable Computing Node.	SEUS	2008	DBLP DOI BibTeX RDF	Temporal Predictability, Determinism, Real-Time Operating Systems, Time-Triggered Architecture
19	Daxian Yun, Yanjie Peng, Jun Han 0003, Xiaoyang Zeng	Tracking loop for IR-UWB communications in IEEE 802.15 multi-path channels.	ISCAS	2008	DBLP DOI BibTeX RDF
19	Minjin Zhang, Huawei Li 0001, Xiaowei Li 0001	Multiple Coupling Effects Oriented Path Delay Test Generation.	VTS	2008	DBLP DOI BibTeX RDF	crosstalk, delay test, path delay fault
19	Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor	Test-Pattern Grading and Pattern Selection for Small-Delay Defects.	VTS	2008	DBLP DOI BibTeX RDF	Small-delay defects, pattern grading, pattern selection, ATPG
19	Shanna-Shaye Forbes, Hiren D. Patel, Edward A. Lee, Hugo A. Andrade	An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture.	DS-RT	2008	DBLP DOI BibTeX RDF
19	Yan Lin 0001, Lei He 0001	Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction.	DATE	2007	DBLP DOI BibTeX RDF
19	Huan Ren, Shantanu Dutt	Constraint satisfaction in incremental placement with application to performance optimization under power constraints.	ICCD	2007	DBLP DOI BibTeX RDF
19	Guilan Dai, Xiaoying Bai, Chongchong Zhao	A Framework for Time Consistency Verification for Web Processes Based on Annotated OWL-S.	GCC	2007	DBLP DOI BibTeX RDF
19	Vineet Wason, Rajeev Murgai, William W. Walker	An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.	VLSI Design	2007	DBLP DOI BibTeX RDF
19	Suleman Surti, Joel S. Karp, Lucretiu M. Popescu, Margaret E. Daube-Witherspoon, Matthew E. Werner	Investigation of time-of-flight benefit for fully 3-DPET.	IEEE Trans. Medical Imaging	2006	DBLP DOI BibTeX RDF
19	Xianfeng Li, Abhik Roychoudhury, Tulika Mitra	Modeling out-of-order processors for WCET analysis.	Real Time Syst.	2006	DBLP DOI BibTeX RDF	Worst-case execution time (WCET) analysis, Out-of-order superscalar processor, Branch prediction, Instruction cache
19	Shige Wang, Kang G. Shin	Task Construction for Model-Based Design of Embedded Control Software.	IEEE Trans. Software Eng.	2006	DBLP DOI BibTeX RDF	Task construction, model transformation, embedded software, model-based design
19	Ad M. G. Peeters	Clockless IC design using handshake technology.	ISPD	2006	DBLP DOI BibTeX RDF
19	June J. Skelly	Temporal interface designs for modeling and simulation: reducing display clutter by temporal fusion.	WSC	2006	DBLP DOI BibTeX RDF
19	Leonard Lee, Li-C. Wang	On bounding the delay of a critical path.	ICCAD	2006	DBLP DOI BibTeX RDF
19	I-De Huang, Sandeep K. Gupta 0001	Selection of Paths for Delay Testing.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
19	Ghassan Kbar, Wathiq Mansoor	Mobile Station Location Based on Hybrid of Signal Strength and Time of Arrival.	ICMB	2005	DBLP DOI BibTeX RDF	MS positioning, Wireless, GSM
19	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	A yield improvement methodology using pre- and post-silicon statistical clock scheduling.	ICCAD	2004	DBLP DOI BibTeX RDF
19	Junhyung Um, Taewhan Kim	Synthesis of arithmetic circuits considering layout effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Li-Da Huang, Hung-Ming Chen, D. F. Wong 0001	Global Wire Bus Configuration with Minimum Delay Uncertainty.	DATE	2003	DBLP DOI BibTeX RDF
19	Insik Shin, Insup Lee 0001	Periodic Resource Model for Compositional Real-Time Guarantees.	RTSS	2003	DBLP DOI BibTeX RDF
19	Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng	On theoretical and practical considerations of path selection for delay fault testing.	ICCAD	2002	DBLP DOI BibTeX RDF
19	Junhyung Um, Taewhan Kim	Layout-aware synthesis of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	layout, high performance, carry-save-adder
19	Juan Zamorano, José F. Ruiz, Juan Antonio de la Puente	Implementing Ada.Real_Time.Clock and Absolute Delays in Real-Time Kernels.	Ada-Europe	2001	DBLP DOI BibTeX RDF
19	Irina B. Virbitskaite, E. Pokozy	Parametric Behaviour Analysis for Time Petri Nets.	PaCT	1999	DBLP DOI BibTeX RDF
19	Karl-Heinz Zimmermann	A Unifying Lattice-Based Approach for the Partitioning of Systolic Arrays via LPGS and LSGP.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
19	Karl-Heinz Zimmermann, Wolfgang Achtziger	Finding Space-Time Transformations for Uniform Recurrences via Branching Parametric Linear Programming.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
19	Shangping Ren, Gul Agha	RTsynchronizer: Language Support for Real-Time Specifications in Distributed Systems.	Workshop on Languages, Compilers, & Tools for Real-Time Systems	1995	DBLP DOI BibTeX RDF
19	David K. Probst, Hon Fung Li	Verifying Timed Behavior Automata with Input/Output Critical Races.	CAV	1993	DBLP DOI BibTeX RDF
19	Balasubramanya Bhat, Frank Mueller 0001	Making DRAM Refresh Predictable.	ECRTS	2010	DBLP DOI BibTeX RDF	DRAM Refresh, Real-Time Systems, Timing Analysis, DRAM, Worst-Case Execution Time, Timing Predictability
19	Arijit Mondal, Partha Pratim Chakrabarti, Pallab Dasgupta	Accelerating Synchronous Sequential Circuits Using an Adaptive Clock.	VLSI Design	2010	DBLP DOI BibTeX RDF	VLSI, CAD, delays, Timing, sequential circuits, Timing optimization
19	Ali Dasdan	Provably efficient algorithms for resolving temporal and spatial difference constraint violations.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	interface timing, layout compaction, scheduling, real-time systems, constraint satisfaction, timing constraints, Behavioral synthesis, multimedia synchronization, rate analysis
19	Susanne Graf, Ileana Ober, Iulian Ober	A real-time profile for UML.	Int. J. Softw. Tools Technol. Transf.	2006	DBLP DOI BibTeX RDF	Real-time profile, Modeling, Real-time systems, UML, Formal verification, Timing analysis, OMEGA, Timing properties
19	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
19	Stephen H. Unger	Hazards, Critical Races, and Metastability.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	critical race, dynamic hazards, essential hazards, inertial delays, pure delays, sequential logic, timing problems, delays, Asynchronous, metastability, timing simulation
17	Guihai Yan, Yinhe Han 0001, Xiaowei Li 0001	ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF	Lifetime reliability, aging sensor, self-adaptive, NBTI, timing adaptation
17	JingZheng Wu, Liping Ding, Yongji Wang 0002, Wei Han	Identification and Evaluation of Sharing Memory Covert Timing Channel in Xen Virtual Machines.	IEEE CLOUD	2011	DBLP DOI BibTeX RDF	Channel Identification, Channel Scenario Construction, Channel Performance Evaluation, Cloud Computing, Xen, Covert Timing Channel
17	Yit Kwong Chin, Lai Kuan Lee, Nurmin Bolong, Soo Siang Yang, Kenneth Tze Kin Teo	Exploring Q-Learning Optimization in Traffic Signal Timing Plan Management.	CICSyN	2011	DBLP DOI BibTeX RDF	Traffic Signal Timing Plan, Traffic Flow Control, Q-Learning
17	Haile Yu, Qiang Xu 0001, Philip Heng Wai Leong	On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry.	FPL	2011	DBLP DOI BibTeX RDF	Architectural Symmetry, LE swap, FPGA, Timing Yield
17	Wen-Chang Hsu, Shih-Hao Hung, Chia-Heng Tu	A Virtual Timing Device for Program Performance Analysis.	CIT	2010	DBLP DOI BibTeX RDF	performance evaluation, embedded system, functional simulation, virtual platform, Timing estimation
17	Haibo Zeng 0001, Arkadeb Ghosal, Marco Di Natale	Timing Analysis and Optimization of FlexRay Dynamic Segment.	CIT	2010	DBLP DOI BibTeX RDF	Scheduling, Timing Analysis, FlexRay
17	Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele	Timing Analysis for TDMA Arbitration in Resource Sharing Systems.	IEEE Real-Time and Embedded Technology and Applications Symposium	2010	DBLP DOI BibTeX RDF	Worst-Case Timing Analysis, Real-Time Systems, Time Division Multiple Access (TDMA)