|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 314 occurrences of 223 keywords
|
|
|
Results
Found 410 publication records. Showing 410 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
98 | Gerhard P. Fettweis |
DSPs: why don't they just go away!. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 93-93, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
93 | Peter Westermann, Ludwig Schwoerer, André Kaufmann |
Applying Data Mapping Techniques to Vector DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(1), pp. 57-72, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Vector DSPs, Vectorizing compilers |
70 | Peter Westermann, Hartmut Schröder |
Modeling Scalable SIMD DSPs in LISA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 161-170, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
SIMD DSPs, Scalable Processor Models, LISA |
65 | Peter Westermann, Ludwig Schwoerer, André Kaufmann |
Applying Data Mapping Techniques to Vector DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 1-8, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
65 | Michael Hosemann, Gerhard P. Fettweis |
On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 313-322, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
59 | Björn Franke, Michael F. P. O'Boyle |
Compiler parallelization of C programs for multi-core DSPs with multiple address spaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 219-224, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
address resolution, multiple address space compilation, DSPs, data partitioning |
54 | Michael Hosemann, Gerhard P. Fettweis |
On Enhancing SIMD-controlled DSPs for Performing Recursive Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 43(2-3), pp. 125-142, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
54 | Markus Lorenz, Peter Marwedel |
Phase Coupled Code Generation for DSPs Using a Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1270-1275, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Jie Guo 0007, Michael Hosemann, Gerhard P. Fettweis |
Employing Compilers for Determining Architectural Features of Application-Specific DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 7-10 September 2004, Dresden, Germany, pp. 39-44, 2004, IEEE Computer Society, 0-7695-2080-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
54 | Paul S. Graham, Brent E. Nelson |
Frequency-Domain Sonar Processing in FPGAs and DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 306-307, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
44 | V. Parthasarathy, S. Aram valartha Bharathi, V. Rhymend Uthariaraj |
Performance Analysis of Embedded Media Applications in Newer ARM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 14-17 June 2005, Oslo, Norway, pp. 210-214, 2005, IEEE Computer Society, 0-7695-2381-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
ARM v6, DSP Extensions, Instruction set architecture (ISA), Single Instruction Multiple Data (SIMD) |
44 | Jeonghun Cho, Yunheung Paek, David B. Whalley |
Fast memory bank assignment for fixed-point digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(1), pp. 52-74, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
dual memory banks, nonorthogonal architecture, Compiler, DSP, dependence analysis, maximum spanning tree |
44 | Gene Frantz |
Digital Signal Processor Trends. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(6), pp. 52-59, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Jintao Wang, Rui Lv, Pengdong Gao, Yongquan Lu, Chu Qiu, Wenhua Yu |
The Design of HDTV H.264 Encoding System Based on Multi-DSPs Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSSE (4) ![In: International Conference on Computer Science and Software Engineering, CSSE 2008, Volume 4: Embedded Programming / Database Technology / Neural Networks and Applications / Other Applications, December 12-14, 2008, Wuhan, China, pp. 54-57, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
43 | Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton |
Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Appl. Intell. ![In: Appl. Intell. 26(1), pp. 53-67, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Memory assignment, Repair method, Genetic algorithm, Multi-Objective optimization, Embedded processors |
43 | Dan Zhang, Zeng-zhi Li, Hai Wang, Tao Zhan |
A Novel Genetic Algorithm for Variable Partition of Dual Memory Bank DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICNC (3) ![In: Advances in Natural Computation, First International Conference, ICNC 2005, Changsha, China, August 27-29, 2005, Proceedings, Part III, pp. 883-892, 2005, Springer, 3-540-28320-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
43 | Siddharth Rele, Vipin Jain, Santosh Pande, J. Ramanujam |
Compact and efficient code generation through program restructuringon limited memory embedded DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(4), pp. 477-494, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
43 | Rainer Leupers |
Instruction Scheduling for Clustered VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 291-300, 2000, IEEE Computer Society, 0-7695-0622-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Naji Ghazal, A. Richard Newton, Jan M. Rabaey |
Predicting performance potential of modern DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 332-335, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(1), pp. 112-122, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
43 | Marcos Luiz Mucheroni, Célio Estevan Morón, José Hiroki Saito |
ArchMDSP: using DSPs for parallel image processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 23rd EUROMICRO Conference '97, New Frontiers of Information Technology, 1-4 September 1997, Budapest, Hungary, pp. 584-590, 1997, IEEE Computer Society, 0-8186-8129-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
ArchMDSP, image mapping, real-time problems, fault-tolerant problems, sub-image distribution available, Sun SparcStation, Sbus, multiple-module carrier card, TMS320C40 processors, timing measurements, 8 Mbyte, parallel architecture, parallel machines, parallel machine, speedup, operators, digital signal processors, communication overhead, parallel programming environment, image size, pipeline structure, parallel image processing |
39 | Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers |
Offset assignment using simultaneous variable coalescing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(4), pp. 864-883, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Stack offset assignment, address registers, autoincrement addressing modes, variable coalescing, DSPs, register allocation |
33 | M. Van Der Horst, Kees van Berkel 0001, Johan Lukkien, Rudolf H. Mak |
Recursive Filtering on a Vector DSP with Linear Speedup. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 379-386, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | Ross Snider, Yongming Zhu |
Developing a Data Driven System for Computational Neuroscience. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part III, pp. 822-826, 2004, Springer, 3-540-22116-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara |
Memory allocation method for indirect addressing with an index register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 199-202, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Sadagopan Srinivasan, Vinodh Cuppu, Bruce L. Jacob |
Transparent data-memory organizations for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 44-48, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Sungjoon Jung, Yunheung Paek |
The very portable optimizer for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 84-92, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Adrian Johnstone, Elizabeth Scott, Tim Womack |
Experience Paper: Reverse Compilation of Digital Signal Processor Assembler Source to ANSI-C. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSM ![In: 1999 International Conference on Software Maintenance, ICSM 1999, Oxford, England, UK, August 30 - September 3, 1999, pp. 316-325, 1999, IEEE Computer Society, 0-7695-0016-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
reverse compilation, low to high level language translation, digital signal processing |
33 | Mazen A. R. Saghir, Paul Chow, Corinna G. Lee |
Exploiting Dual Data-Memory Banks in Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: ASPLOS-VII Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996., pp. 234-243, 1996, ACM Press, 0-89791-767-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | Chun Jason Xue, Tiantian Liu 0001, Zili Shao, Jingtong Hu, Zhiping Jia, Weijia Jia 0001, Edwin Hsing-Mean Sha |
Address assignment sensitive variable partitioning and scheduling for DSPS with multiple memory banks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 1453-1456, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
32 | Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek |
Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC Workshops ![In: Emerging Directions in Embedded and Ubiquitous Computing, EUC 2006 Workshops: NCUS, SecUbiq, USN, TRUST, ESO, and MSA, Seoul, Korea, August 1-4, 2006, Proceedings, pp. 741-754, 2006, Springer, 3-540-36850-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Partha Biswas, Nikil D. Dutt |
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(10), pp. 1216-1226, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction |
32 | Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob |
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 364-375, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Viera Sipková |
Efficient Variable Allocation to Dual Memory Banks of DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 359-372, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Partha Biswas, Nikil D. Dutt |
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 104-112, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment |
32 | Markus Lorenz, Lars Wehmeyer, Thorsten Dräger |
Energy aware compilation for DSPs with SIMD instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 94-101, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
zero overhead hardware loop, DSP, vectorization, energy minimization, SIMD instruction |
32 | Eugenio Suárez Cáner, José Manoel de Seixas, Rodrigo Coura Torres |
A Development Environment for Multilayer Neural Network Applications Mapped onto DSPs with Multiprocessing Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VECPAR ![In: High Performance Computing for Computational Science - VECPAR 2002, 5th International Conference, Porto, Portugal, June 26-28, 2002, Selected Papers and Invited Talks, pp. 717-730, 2002, Springer, 3-540-00852-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Nagisa Ishiura, Tatsuo Watanabe |
Datapath oriented codesign method of application specific DSPs using retargetable compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 55-58, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
32 | Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama |
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11), pp. 1319-1328, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Gary William Grewal, Thomas Charles Wilson |
Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T). ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 192-202, 2001, ACM/IEEE Computer Society, 0-7695-1369-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel |
Optimized address assignment for DSPs with SIMD memory accesses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 415-420, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Low-power realization of FIR filters on programmable DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 546-553, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Guido Araujo, Sharad Malik |
Code generation for fixed-point DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 3(2), pp. 136-161, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
scheduling, code generation, register allocation |
32 | Jan M. Rabaey, Marlene Wan |
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 341-342, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
32 | Thomas Charles Wilson, Gary William Grewal |
Shake And Bake: A Method of Mapping Code to Irregular DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 506-508, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | Gary William Grewal |
A Global Mode Instruction Minimization Technique for Embedded DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), March 22-23, 1996, Ames, IA, USA, pp. 18-, 1996, IEEE Computer Society, 0-8186-7502-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
32 | Rainer Leupers, Peter Marwedel |
Time-constrained code compaction for DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 54-59, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
code generation techniques, digital signal processing algorithms, encoding restrictions, exact timing behavior, hard real-time constraints, integer programming model, local code compaction, programmable DSP, rigid heuristics, time-constrained code compaction, real-time systems, timing, integer programming, instruction-level parallelism, source coding, automatic programming, digital signal processing chips, side-effects |
32 | Edward A. Lee, E. Goei, H. Heine, W.-H. Ho, Shuvra S. Bhattacharyya, Jeffery C. Bier, E. Guntvedt |
GABRIEL: A Design Environment for Programmable DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 141-146, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
27 | Atsushi Ishii, Toyotaro Suzumura |
Elastic Stream Computing with Clouds. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE CLOUD ![In: IEEE International Conference on Cloud Computing, CLOUD 2011, Washington, DC, USA, 4-9 July, 2011, pp. 195-202, 2011, IEEE Computer Society, 978-1-4577-0836-7. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
SPADE, Amazon EC2, Cloud, Dynamic Load Balancing, DSMS, Data Stream Processing, System S, DSPS |
27 | Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra |
Global array reference allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(2), pp. 336-357, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Address registers, auto-increment addressing modes, DSPs, register allocation |
22 | André Ludwig, Marek Kowalkiewicz |
Supporting Service Level Agreement Creation with Past Service Behavior Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIS (Workshops) ![In: Business Information Systems Workshops, BIS 2009 International Workshops, Poznan, Poland, April 27-29, 2009. Revised Papers, pp. 375-385, 2009, Springer, 978-3-642-03423-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Dynamic Service Profiling, Service behavior, Service Level Agreement, Contracting |
22 | Hong Liu 0002, Ke Wu, Peter Meusel, Nikolaus Seitz, Gerd Hirzinger, M. H. Jin, Yiwei Liu, Shaowei Fan, T. Lan, Zhaopeng Chen |
Multisensory five-finger dexterous hand: The DLR/HIT Hand II. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IROS ![In: 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, September 22-26, 2008, Acropolis Convention Center, Nice, France, pp. 3692-3697, 2008, IEEE, 978-1-4244-2057-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli |
ADAPTO: full-adder based reconfigurable architecture for bit level operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3434-3437, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Hangpei Tian, Deyuan Gao, Deli Wang, Yian Zhu, Shengbing Zhang, Jing Wang |
Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MUE ![In: 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 24-26 April 2008, Busan, Korea, pp. 330-335, 2008, IEEE Computer Society, 978-0-7695-3134-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Instruction Set, Software Radio |
22 | Yi-Hsuan Lee, Cheng Chen |
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(3), pp. 281-296, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
non-orthogonal architecture, code generation, DSP |
22 | Doosan Cho, Ravi Ayyagari, Gang-Ryung Uh, Yunheung Paek |
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 16th International Conference, CC 2007, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2007, Braga, Portugal, March 26-30, 2007, Proceedings, pp. 16-31, 2007, Springer, 978-3-540-71228-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Muhammet Fikret Ercan |
Parallel Image Understanding on a Multi-DSP System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (2) ![In: Computational Science and Its Applications - ICCSA 2007, International Conference, Kuala Lumpur, Malaysia, August 26-29, 2007. Proceedings, Part II, pp. 1-12, 2007, Springer, 978-3-540-74475-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Ozcan Ozturk 0001, Mahmut T. Kandemir, Suleyman Tosun |
An ILP based approach to address code generation for digital signal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 37-42, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
code generation, DSP, integer linear programming |
22 | Takashi Shono, Yushi Shirato, Hiroyuki Shiba, Kazuhiro Uehara, Katsuhiko Araki, Masahiro Umehira |
IEEE 802.11 wireless LAN implemented on software defined radio with hybrid programmable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 4(5), pp. 2299-2308, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Björn Franke, Michael F. P. O'Boyle |
A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 16(3), pp. 234-245, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
conversion from sequential to parallel forms, modeling, evaluation, compilers, measurement, performance measures, interprocessor communications, arrays, real-time and embedded systems, restructuring, Parallel processors, simulation of multiple-processor systems, reverse engineering and reengineering, signal processing systems |
22 | Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard P. Fettweis |
Synchronous Transfer Architecture (STA). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 343-352, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Kees A. Vissers |
Programming models and architectures for FPGA platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 1, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong |
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 150-161, 2004, IEEE Computer Society, 0-7695-2143-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
22 | Jae C. Oh, Madhura S. Tamhankar, Daniel Mossé |
Design of Very Lightweight Agents for Reactive Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECBS ![In: 10th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2003), 7-10 April 2003, Huntsville, AL, USA, pp. 149-158, 2003, IEEE Computer Society, 0-7695-1917-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Björn Franke, Michael F. P. O'Boyle |
Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 104-113, 2003, IEEE Computer Society, 0-7695-2021-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Erik Eckstein, Bernhard Scholz |
Addressing Mode Selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 337-346, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
22 | Heiko Michel, Alexander Worm, Norbert Wehn, Michael Münch |
Hardware/Software Trade-Offs for Advanced 3G Channel Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 396-401, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
22 | Christoph W. Keßler, Andrzej Bednarski |
A Dynamic Programming Approach to Optimal Integrated Code Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES/OM ![In: Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA, pp. 165-174, 2001, ACM, 1-58113-425-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
integrated code generation, time profile, dynamic programming, register allocation, instruction scheduling, instruction selection |
22 | Ashok Sudarsanam, Sharad Malik |
Simultaneous reference allocation in code generation for dual data memory bank ASIPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(2), pp. 242-264, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
memory bank assignment, code generation, register allocation, code optimization, graph labelling |
22 | David W. Currie, Alan J. Hu, Sreeranga P. Rajan |
Automatic formal verification of DSP software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 130-135, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
22 | Anupam Basu, Rainer Leupers, Peter Marwedel |
Register-Constrained Address Computation in DSP Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 929-930, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
DSP compiler, address computation, embedded processors |
22 | Shuvra S. Bhattacharyya, Edward A. Lee |
Scheduling synchronous dataflow graphs for efficient looping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 6(3), pp. 271-288, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Yang Wang, Qinglin Wang, Xiangdong Pei, Songzhu Mei, Rongchun Li, Jie Liu 0002 |
High performance dilated convolutions on multi-core DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCF Trans. High Perform. Comput. ![In: CCF Trans. High Perform. Comput. 6(1), pp. 78-93, February 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
21 | Wei Tang 0010, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang |
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023, pp. 1-2, 2023, IEEE, 978-4-86348-806-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Deshun Bi, Xiaowen Tian, Shengguo Li, Dezun Dong |
Efficiently Running SpMV on Multi-Core DSPs for Block Sparse Matrix. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 29th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2023, Ocean Flower Island, China, December 17-21, 2023, pp. 1912-1919, 2023, IEEE, 979-8-3503-3071-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yufei Guo, Xinjie An, Shijie Li, Yingbo Cui, Peng Zhang, Biao Long, Shanshan Li |
MTMap: A Long-Read Alignment Tool based on Multi-Core DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BIBM ![In: IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2023, Istanbul, Turkiye, December 5-8, 2023, pp. 863-866, 2023, IEEE, 979-8-3503-3748-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Yang Wang, Qinglin Wang, Xiangdong Pei, Songzhu Mei, Jie Liu 0002 |
Optimizing Pointwise Convolutions on Multi-core DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (7) ![In: Algorithms and Architectures for Parallel Processing - 23rd International Conference, ICA3PP 2023, Tianjin, China, October 20-22, 2023, Proceedings, Part VII, pp. 209-223, 2023, Springer, 978-981-97-0861-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Deshun Bi, Shengguo Li, Yichen Zhang, Xiaojian Yang, Dezun Dong |
Efficiently Running SpMV on Multi-core DSPs for Banded Matrix. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICA3PP (5) ![In: Algorithms and Architectures for Parallel Processing - 23rd International Conference, ICA3PP 2023, Tianjin, China, October 20-22, 2023, Proceedings, Part V, pp. 201-220, 2023, Springer, 978-981-97-0807-9. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Xiaolei Zhao, Zhaoyun Chen, Yang Shi, Mei Wen, Chunyun Zhang |
Automatic End-to-End Joint Optimization for Kernel Compilation on DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, pp. 1-6, 2023, IEEE, 979-8-3503-2348-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
21 | Shangfei Yin, Qinglin Wang, Ruochen Hao, Tianyang Zhou, Songzhu Mei, Jie Liu 0002 |
Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2208.05872, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Shun Orita, Akiko Narita, Kenji Ichijo |
Design of Multicore Dataflow DSPs with Different Loop Iteration Mechanisms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE-TW ![In: IEEE International Conference on Consumer Electronics - Taiwan, ICCE-TW 2022, Taipei, Taiwan, July 6-8, 2022, pp. 109-110, 2022, IEEE, 978-1-6654-7050-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Wei Niu 0002, Jiexiong Guan, Xipeng Shen, Yanzhi Wang, Gagan Agrawal, Bin Ren |
GCD2: A Globally Optimizing Compiler for Mapping DNNs to Mobile DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 55th IEEE/ACM International Symposium on Microarchitecture, MICRO 2022, Chicago, IL, USA, October 1-5, 2022, pp. 512-529, 2022, IEEE, 978-1-6654-6272-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Bowen Zhu, Yanyi Wang, Weiping Li, Feng Wang, Jiaxuan Liu, Jianjun Yu |
40-Gbit/s W-band Signal Delivery over 4600-m Wireless Distance Employing Advanced DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC Workshops ![In: 2022 IEEE International Conference on Communications Workshops, ICC Workshops 2022, Seoul, Korea, May 16-20, 2022, pp. 904-909, 2022, IEEE, 978-1-6654-2671-8. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Elliott Wen, Jiaxing Shen |
DSPBooster: Offloading Unmodified Mobile Applications to DSPs for Power-performance Optimal Execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COMPSAC ![In: 46th IEEE Annual Computers, Software, and Applications Conferenc, COMPSAC 2022, Los Alamitos, CA, USA, June 27 - July 1, 2022, pp. 614-623, 2022, IEEE, 978-1-6654-8810-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson 0001, Per Larsson-Edefors |
Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NorCAS ![In: IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, Norway, October 25-26, 2022, pp. 1-6, 2022, IEEE, 979-8-3503-4550-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Ankita Shah, Uma Shanker Tiwary |
Dominance Submissiveness Predisposition Scale (DSPS): Development and Validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHI ![In: Intelligent Human Computer Interaction - 14th International Conference, IHCI 2022, Tashkent, Uzbekistan, October 20-22, 2022, Revised Selected Papers, pp. 188-200, 2022, Springer, 978-3-031-27198-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | Shangfei Yin, Qinglin Wang, Ruochen Hao, Tianyang Zhou, Songzhu Mei, Jie Liu 0002 |
Optimizing Irregular-Shaped Matrix-Matrix Multiplication on Multi-Core DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: IEEE International Conference on Cluster Computing, CLUSTER 2022, Heidelberg, Germany, September 5-8, 2022, pp. 451-461, 2022, IEEE, 978-1-6654-9856-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
21 | David Uzan, Roger Kahn, Shlomo Weiss |
Perceptron based filtering of futile prefetches in embedded VLIW DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Archit. ![In: J. Syst. Archit. 110, pp. 101826, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
21 | Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin |
Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2019, pp. 1380, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
21 | Elif Bilge Kavun, Nele Mentens, Jo Vliegen, Tolga Yalçin |
Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: 2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019, pp. 1-2, 2019, IEEE, 978-1-7281-1957-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Rui Qin 0002, Yong Yuan, Fei-Yue Wang 0001 |
Exploring Optimal Revenue Models For DSPs In Real Time Bidding Advertising. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOLI ![In: 2019 IEEE International Conference on Service Operations and Logistics, and Informatics, SOLI 2019, Zhengzhou, China, November 6-8, 2019, pp. 181-185, 2019, IEEE, 978-1-7281-2853-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
21 | Amir HajiRassouliha, Andrew J. Taberner, Martyn P. Nash, Poul M. F. Nielsen |
Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Signal Process. Image Commun. ![In: Signal Process. Image Commun. 68, pp. 101-119, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Yuan Li, Wei Li 0032, Lu Li 0005 |
Hyperspectral Anomaly Dectection on Multicore DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISP-BMEI ![In: 11th International Congress on Image and Signal Processing, BioMedical Engineering and Informatics, CISP-BMEI 2018, Beijing, China, October 13-15, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-7604-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
21 | Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout |
A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Hardw. Syst. Secur. ![In: J. Hardw. Syst. Secur. 1(3), pp. 219-236, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Sander Vocke, Henk Corporaal, Roel Jordans, Rosilde Corvino, Rick J. M. Nas |
Extending Halide to Improve Software Development for Imaging DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 14(3), pp. 21:1-21:25, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Rui Chang, Jun Wu 0006, Haoqi Ren |
A compilation method for zero overhead loop in DSPs with VLIW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCSP ![In: 9th International Conference on Wireless Communications and Signal Processing, WCSP 2017, Nanjing, China, October 11-13, 2017, pp. 1-7, 2017, IEEE, 978-1-5386-2062-5. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
21 | Shiming Sun, Hongxu Jiang, Bo Li 0006 |
An efficient Markov chain-based data prefetching for motion estimation of HEVC on multi-core DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Multim. Tools Appl. ![In: Multim. Tools Appl. 75(13), pp. 8019-8043, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Sheng Liu 0001, Haiyan Chen, Jianghua Wan, Yaohua Wang |
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2016, Pittsburgh, PA, USA, July 11-13, 2016, pp. 426-430, 2016, IEEE Computer Society, 978-1-4673-9039-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Amine Mrabet, Nadia El Mrabet, Ronan Lashermes, Jean-Baptiste Rigaud, Belgacem Bouallegue, Sihem Mesnager, Mohsen Machhout |
A Scalable and Systolic Architectures of Montgomery Modular Multiplication for Public Key Cryptosystems Based on DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPACE ![In: Security, Privacy, and Applied Cryptography Engineering - 6th International Conference, SPACE 2016, Hyderabad, India, December 14-18, 2016, Proceedings, pp. 138-156, 2016, Springer, 978-3-319-49444-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
21 | Xiangyang Liu, Hua Bao |
Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 80(2), pp. 153-161, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 410 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ 5][ >>] |
|