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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 38 occurrences of 34 keywords
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Results
Found 48 publication records. Showing 48 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
33 | C. P. Ravikumar, Rahul Kumar |
Divide-and-Conquer IDDQ Testing for Core-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 761-766, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Bart Vermeulen, Tom Waayers, Sjaak Bakker |
Multi-TAP Controller Architecture for Digital System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 417-424, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
system-chips, IEEE-1149.1, software-debug, design-for-debug, multi-TAP |
28 | Indradeep Ghosh, Sujit Dey, Niraj K. Jha |
A fast and low-cost testing technique for core-based system-chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8), pp. 863-877, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Yankin Tanurhan |
Processors and FPGAs Quo Vadis? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 39(11), pp. 108-110, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Programmable system chips, Embedded computing |
21 | Prab Varma, Sandeep Bhatia |
A structured test re-use methodology for core-based system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 294-302, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
Testing embedded-core based system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 130-143, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Yervant Zorian |
System-Chip Test Strategies (Tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 752-757, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
system-on-chip test, testing embedded core, intellectual property test |
19 | Prab Varma |
System Chip Test Challenges, Are There Solutions Today? (Panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 750-751, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Erik Jan Marinissen |
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 435-454, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
system chips, test protocol, test protocol scheduling, test generation, expansion, embedded cores |
17 | Iasson Vassiliou, Henry Chang, Alper Demir 0001, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli |
A video driver system designed using a top-down, constraint-driven methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 463-468, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Analog CAD, Video Driver System Chips, Analog Behavioral Modeling, Design Methodologies |
14 | Yong-Xiao Chen, Jin-Fu Li 0001 |
Testing of Non-volatile Logic-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, pp. 224-229, 2014, IEEE Computer Society, 978-1-4799-6030-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
14 | W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang |
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 5(4), pp. 238-246, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/0710.4687, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
14 | Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park |
An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 139-150, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing |
14 | Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty |
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 285-290, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 44-49, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Bart Vermeulen |
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 407-416, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
scan-based debug, Design-for-Debug (DfD), clock gating, silicon debug, multiple-clock domains |
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 425-435, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
TAM and wrapper design, test scheduling, SOC-test |
14 | Tom Waayers |
An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1145-1154, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Erik Jan Marinissen |
A novel test time reduction algorithm for test architecture design for core-based system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 7th European Test Workshop, ETW 2002, Corfu, Greece, May 26-29, 2002, pp. 7-12, 2002, IEEE Computer Society, 0-7695-1715-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Bart Vermeulen |
Data invalidation analysis for scan-based debug on multiple-clock system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 7th European Test Workshop, ETW 2002, Corfu, Greece, May 26-29, 2002, pp. 61-66, 2002, IEEE Computer Society, 0-7695-1715-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Kumar Goel, Bart Vermeulen |
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 1103-1110, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Bart Vermeulen, Tom Waayers, Sjaak Bakker |
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 55-63, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
14 | Mohsen Nahvi, André Ivanov |
A packet switching communication-based test access mechanism for system chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001, pp. 81-86, 2001, IEEE Computer Society, 0-7695-1017-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
14 | Erik Jan Marinissen, Yervant Zorian |
Testing Embedded Core-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001., pp. 2, 2001, IEEE. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
14 | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
Testing Embedded-Core-Based System Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 32(6), pp. 52-60, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
14 | Luciano Lavagno, Sujit Dey, Rajesh K. Gupta 0001 |
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 21-23, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
13 | Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel |
Core-Based Scan Architecture for Silicon Debug. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 638-647, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
7 | Érika F. Cota, Chunsheng Liu |
Constraint-Driven Test Scheduling for NoC-Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), pp. 2465-2478, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
7 | A. Richard Newton |
Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 501, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
7 | Kwang-Ting (Tim) Cheng |
Cocktail approach to functional verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 108, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
validation, functional verification, multiprocessor SoC, SiP, BISR |
7 | Shyue-Kung Lu, Shih-Chang Huang |
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 60-64, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
7 | YongJoon Kim, DongSub Song, YongSeung Shin, Sunghoon Chun, Sungho Kang 0001 |
A New Maximal Diagnosis Algorithm for Bus-structured Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 349-357, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
7 | Greg Stitt, Frank Vahid |
Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 19(6), pp. 36-43, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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7 | C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma |
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 462-467, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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6 | Erik Jan Marinissen, Yervant Zorian |
Guest Editors' Introduction: The Status of IEEE Std 1500. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 26(1), pp. 6-7, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Kwang-Ting (Tim) Cheng |
Supporting cost-effective innovation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(3), pp. 212, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nanoscale, variability, IR drop, power supply noise |
6 | Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez |
Testing and Diagnosis of Power Switches in SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETS ![In: 11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006, pp. 145-150, 2006, IEEE Computer Society, 0-7695-2566-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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6 | Rajesh K. Gupta 0001 |
Driving Research in System-Chip Design Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 36(7), pp. 95-97, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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6 | Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(2), pp. 207-215, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
march test algorithm, memory diagnostics, BIST, memory testing, CAM |
6 | Sandeep Kumar Goel, Erik Jan Marinissen |
SOC test architecture design for efficient utilization of test bandwidth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(4), pp. 399-429, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization |
6 | Erik Jan Marinissen, Rohit Kapur, Maurice Lousberg, Teresa L. McLaurin, Mike Ricchetti, Yervant Zorian |
On IEEE P1500's Standard for Embedded Core Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 365-383, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
core test wrapper, core test language, compliance levels, standardization, embedded cores |
6 | Sandeep K. Shukla, Frederic Doucet, Rajesh K. Gupta 0001 |
Structured Component Composition Frameworks for Embedded System Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPC ![In: High Performance Computing - HiPC 2002, 9th International Conference, Bangalore, India, December 18-21, 2002, Proceedings, pp. 663-678, 2002, Springer, 3-540-00303-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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6 | Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin |
Test Scheduling of BISTed Memory Cores for SOC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 356-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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6 | Jin-Fu Li 0001, Ruey-Shing Tzeng, Cheng-Wen Wu |
Testing and Diagnosing Embedded Content Addressable Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 389-394, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
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6 | Juha-Pekka Soininen, Sandrine Boumard, Tommi Salminen, Hannu Heusala |
Application of Decision-Making Method for Architecture Selection of ADSL Modem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 21-29, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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6 | Yervant Zorian, Erik Jan Marinissen |
System chip test: how will it impact your design? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 136-141, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
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6 | S. J. Krolikoski, Frank Schirrmeister, B. Salefski, J. Rowson, Grant Martin |
Methodology and technology for virtual component driven hardware/software co-design on the system-level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 456-459, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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