Search results for "BSIM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
122	ChenMing Hu	BSIM - making the first international standard MOSFET model.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	BSIM, MOS, compact modeling
78	Junlin Zhou, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in p-MOSFETs in the saturationregion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
50	Sudhir M. Gowda, Bing J. Sheu	BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
39	Dingming Xie, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
39	Chung-Ping Wan, Bing J. Sheu	Temperature dependence modeling for MOS VLSI circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
33	Amr M. Bayoumi, Yasser Y. Hanafy	Massive parallelization of SPICE device model evaluation on GPU-based SIMD architectures.	IFMT	2008	DBLP DOI BibTeX RDF	BSIM, parallel computing, graphics processing units, GPGPU, SIMD, SPICE, manycore
31	Yang Xiang, Stanislav Tyaginov, Michiel Vandemaele, Zhicheng Wu, Jacopo Franco, Erik Bury, Brecht Truijen, Bertrand Parvais, Dimitri Linten, Ben Kaczer	A BSIM-Based Predictive Hot-Carrier Aging Compact Model.	IRPS	2021	DBLP DOI BibTeX RDF
31	Chetan Gupta, Ravi Goel, Harshit Agarwal, Chenming Hu, Yogesh Singh Chauhan	BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design.	CICC	2019	DBLP DOI BibTeX RDF
31	Shivendra Singh Parihar, Ramchandra Gurjar	Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model.	VDAT	2019	DBLP DOI BibTeX RDF
31	Muyu Yang, Erdal Oruklu	Full Adder Circuit Design Using Lateral Gate-All-Around (LGAA) FETs Based on BSIM-CMG Mode.	MWSCAS	2018	DBLP DOI BibTeX RDF
31	Pragya Kushwaha, K. Bala Krishna, Harshit Agarwal, Sourabh Khandelwal, Juan Pablo Duarte, Chenming Hu, Yogesh Singh Chauhan	Thermal resistance modeling in FDSOI transistors with industry standard model BSIM-IMG.	Microelectron. J.	2016	DBLP DOI BibTeX RDF
31	Yu Yuan, Cecilia García Martin, Erdal Oruklu	Standard cell library characterization for FinFET transistors using BSIM-CMG models.	EIT	2015	DBLP DOI BibTeX RDF
31	Alessandra Leonhardt, Luiz Fernando Ferreira, Sergio Bampi	Nanoscale FinFET global parameter extraction for the BSIM-CMG model.	LASCAS	2015	DBLP DOI BibTeX RDF
31	Juan Pablo Duarte, Sourabh Khandelwal, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan	BSIM-CMG: Standard FinFET compact model for advanced circuit design.	ESSCIRC	2015	DBLP DOI BibTeX RDF
31	Neelam Patil, Cecilia García Martin, Erdal Oruklu	Performance evaluation of multi-gate fets using the BSIM-CMG model.	EIT	2014	DBLP DOI BibTeX RDF
31	Cecilia García Martin, Erdal Oruklu	Performance evaluation of FinFET pass-transistor full adders with BSIM-CMG model.	MWSCAS	2014	DBLP DOI BibTeX RDF
31	Yang Xiao 0008, Martin A. Trefzer, James Alfred Walker, Simon J. Bale, Andy M. Tyrrell	Two step evolution strategy for device motif BSIM model parameter extraction.	IEEE Congress on Evolutionary Computation	2014	DBLP DOI BibTeX RDF
31	Navid Paydavosi, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Juan Pablo Duarte, Srivatsava Jandhyala, Ali M. Niknejad, Chenming Hu	BSIM - SPICE Models Enable FinFET and UTB IC Designs.	IEEE Access	2013	DBLP DOI BibTeX RDF
31	Liwei Gong, Yuan Xu, Zhi Zhang, Weiwei Shi 0001, Robert K. F. Teng	An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology.	ASICON	2013	DBLP DOI BibTeX RDF
31	Yogesh Singh Chauhan, Sriramkumar Venugopalan, Navid Paydavosi, Pragya Kushwaha, Srivatsava Jandhyala, Juan Pablo Duarte, Shantanu Agnihotri, Chandan Yadav, Harshit Agarwal, Ali M. Niknejad, Chenming Calvin Hu	BSIM compact MOSFET models for SPICE simulation.	MIXDES	2013	DBLP BibTeX RDF
31	Yogesh Singh Chauhan, Sriramkumar Venugopalan, Mohammed A. Karim, Sourabh Khandelwal, Navid Paydavosi, Pankaj Thakur, Ali M. Niknejad, Chenming Hu	BSIM - Industry standard compact MOSFET models.	ESSCIRC	2012	DBLP DOI BibTeX RDF
31	Ai Nishiba, Hiroharu Kawanaka, Haruhiko Takase, Shinji Tsuruoka	A Proposal of Genetic Operations for BSIM Parameter Extraction Using Real-Coded Genetic Algorithm.	J. Adv. Comput. Intell. Intell. Informatics	2011	DBLP DOI BibTeX RDF
31	Xuemei Xi, Jin He 0003, Mohan V. Dunga, Chung-Hsun Lin, Babak Heydari, Hui Wan 0003, Mansun Chan, Ali M. Niknejad, Chenming Hu	The next generation BSIM for sub-100nm mixed-signal circuit simulation.	CICC	2004	DBLP DOI BibTeX RDF
20	Shaoxi Wang, Rui He, Lihong Zhang	MOSFET model assessment for submicron and nanometer bulk-driven applications.	CCECE	2009	DBLP DOI BibTeX RDF
20	Bo Hu, C.-J. Richard Shi	Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
20	Qiang Zhang, Ying Zhuo, Zhenghu Gong	A Trust Inspection Model Based on Society Behavior Similarity Rule in Dynamic Networks.	CSSE (3)	2008	DBLP DOI BibTeX RDF
20	Dinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao	Finite-Point Gate Model for Fast Timing and Power Analysis.	ISQED	2008	DBLP DOI BibTeX RDF
20	Ka Nang Leung, Yanqi Zheng	Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads.	DELTA	2008	DBLP DOI BibTeX RDF	frequency compensation, large capacitive load, Amplifier
20	Min Chen 0024, Wei Zhao, Frank Liu 0001, Yu Cao 0001	Fast statistical circuit analysis with finite-point based transistor model.	DATE	2007	DBLP DOI BibTeX RDF
20	Xudong Niu, Yan Song, Bo Li, Wei Bian, Yadong Tao, Feng Liu, Jinhua Hu, Yu Chen, Frank He	Tests on Symmetry and Continuity between BSIM4 and BSIM5.	ISQED	2007	DBLP DOI BibTeX RDF	BSIM4, BSIM5, CMOS circuit design, symmetry, continuity, compact model
20	Domenik Helms, Marko Hoyer, Wolfgang Nebel	Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage.	PATMOS	2006	DBLP DOI BibTeX RDF
20	James Moritz, Yichuang Sun	100MHz, 6th order, leap-frog gm-C high Q bandpass filter and on-chip tuning scheme.	ISCAS	2006	DBLP DOI BibTeX RDF
20	Carlos Galup-Montoro, Márcio C. Schneider, Viriato C. Pahim	Fundamentals of next generation compact MOSFET models.	SBCCI	2005	DBLP DOI BibTeX RDF	MOSFET model, inversion-charge model, surface potential model, compact model
20	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation PART-I MOSFETs and CMOS inverters.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
20	Michael Walter Payton, Fat Duen Ho	A physically-derived large-signal nonquasi-static MOSFET model for computer aided device and circuit simulation part-II the CMOS NOR gate and the CMOS NAND gate.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
20	Songqing Zhang, Vineet Wason, Kaustav Banerjee	A probabilistic framework to estimate full-chips subthreshold leakage power distribution considering within-die and die-to-die P-T-V variations.	ISLPED	2004	DBLP DOI BibTeX RDF	die-to-die variations, electrothermal couplings, subthreshold leakage power distribution, yield estimation, process variations, within-die variations
20	Shrutin Ulman	Analytical Expressions For Static Characteristics of Submicron CMOS Inverters.	VLSI Design	2004	DBLP DOI BibTeX RDF
20	Chung Kei Thomas Chan, Christofer Toumazou	Design of a class E power amplifier with non-linear transistor output capacitance and finite DC-feed inductance.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
20	Hong June Park, Ping Keung Ko, Chenming Hu	A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF