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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 57 occurrences of 47 keywords
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Results
Found 28 publication records. Showing 28 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
140 | Ramakrishna Voorakaranam, Abhijit Chatterjee |
Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 342-357, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
analog verification, fault diagnosis, test generation, analog testing, Backtrace |
120 | Martin Stáva, Ondrej Novák |
Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 251-256, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, VLSI, ATPG, hardware, on-line learning, Backtrace |
86 | Rajesh Ramadoss, Michael L. Bushnell |
Test generation for mixed-signal devices using signal flow graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 242-248, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
mixed-signal devices, reverse simulation approach, component tolerances, analog input sinusoids, test generation results, analog backtrace method, high-order analog circuits, fault diagnosis, test generation, integrated circuit testing, automatic testing, circuit analysis computing, mixed analogue-digital integrated circuits, signal flow graphs, signal flow graphs, nonlinear circuits |
74 | Alfred V. Gomes, Abhijit Chatterjee |
Robust optimization based backtrace method for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 304-308, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
47 | Kim T. Le, Kewal K. Saluja |
A Heuristic Measure to Maximize Detected Faults per Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 13(1), pp. 57-60, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
combinational circuit testing, dynamic test compaction, fault selection, test generation, testability measures, backtrace |
47 | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
An efficient automatic test generation system for path delay faults in combinational circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 161-165, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests |
40 | Rajesh Ramadoss, Michael L. Bushnell |
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 189-205, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
analog test generation, mixed-signal test generation, back tracing, parametric faults, catastrophic faults |
40 | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang |
Computation of floating mode delay in combinational circuits: practice and implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12), pp. 1924-1936, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
34 | Jingling Zhao, Congxiang Yu, Yunze Ni |
A Universal Defense System Based on Backtrace Canary for ELF Against Vulnerabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AINA ![In: Advanced Information Networking and Applications - Proceedings of the 34th International Conference on Advanced Information Networking and Applications, AINA-2020, Caserta, Italy, 15-17 April., pp. 444-457, 2020, Springer, 978-3-030-44040-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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34 | Lee Aaron Newberg |
Memory-efficient dynamic programming backtrace and pairwise local sequence alignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Bioinform. ![In: Bioinform. 24(16), pp. 1772-1778, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Martin Stáva, Ondrej Novák |
HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006, pp. 250-252, 2006, IEEE Computer Society, 1-4244-0185-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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34 | Chao Liu 0001, Xifeng Yan, Hwanjo Yu, Jiawei Han 0001, Philip S. Yu |
Mining Behavior Graphs for "Backtrace" of Noncrashing Bugs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SDM ![In: Proceedings of the 2005 SIAM International Conference on Data Mining, SDM 2005, Newport Beach, CA, USA, April 21-23, 2005, pp. 286-297, 2005, SIAM, 978-0-89871-593-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
34 | Andrei Mekler, Jaan Raik |
Multiple-objective backtrace for solving test generation constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003, pp. 123-126, 2003, IEEE, 0-7803-8160-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
34 | Antonio Lioy |
Adaptative backtrace and dynamic partitioning enhance ATPG. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 62-65, 1988, IEEE, 0-8186-0872-2. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
27 | Dong Shi, Xinming Zhang 0001, Wenbo Zhu, Enbo Wang |
RCDS: A Ranking-Based Algorithm to Compute the CDS of the Ad Hoc Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCM (1) ![In: NCM 2008, The Fourth International Conference on Networked Computing and Advanced Information Management, Gyeongju, Korea, September 2-4, 2008 - Volume 1, pp. 591-596, 2008, IEEE Computer Society, 978-0-7695-3322-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
ad hoc networks, broadcast, connected dominating set, backtrace |
27 | Hideo Fujiwara, Takeshi Shimono |
On the Acceleration of Test Generation Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 32(12), pp. 1137-1144, 1983. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP DOI BibTeX RDF |
multiple backtrace, PODEM algorithm, decision tree, test generation, sensitization, Combinational logic circuits, D-algorithm, stuck faults |
20 | Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman |
Parallel fault backtracing for calculation of fault coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 667-672, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Jing Yang 0003, Mary Lou Soffa, Leo Selavo, Kamin Whitehouse |
Clairvoyant: a comprehensive source-level debugger for wireless sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SenSys ![In: Proceedings of the 5th International Conference on Embedded Networked Sensor Systems, SenSys 2007, Sydney, NSW, Australia, November 6-9, 2007, pp. 189-203, 2007, ACM, 978-1-59593-763-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
embedded debugging, wireless sensor networks, distributed debugging, source-level debugging |
20 | Andrew M. Cheadle, A. J. Field, J. W. Ayres, Neil Dunn, Richard A. Hayden, Johan Nyström-Persson |
Visualising dynamic memory allocators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 5th International Symposium on Memory Management, ISMM 2006, Ottawa, Ontario, Canada, June 10-11, 2006, pp. 115-125, 2006, ACM, 1-59593-221-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
visualisation of objects, garbage collection, memory management, dynamic memory allocation, language implementation |
20 | Hanhua Chen, Hai Jin 0001 |
Identifying Community Structure in Semantic Peer-to-Peer Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SKG ![In: 2006 International Conference on Semantics, Knowledge and Grid (SKG 2006), 1-3 November 2006, Guilin, China, pp. 25, 2006, IEEE Computer Society, 0-7695-2673-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Wojciech Bozejko, Mieczyslaw Wodecki |
Solving the Flow Shop Problem by Parallel Tabu Search. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 22-25 September 2002, Warsaw, Poland, pp. 189-194, 2002, IEEE Computer Society, 0-7695-1730-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang |
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 117-128, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | M. Stancic, Liquan Fang, M. H. H. Weusthof, R. M. W. Tijink, Hans G. Kerkhoff |
A New Test Generation Approach for Embedded Analogue Cores in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 861-869, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Ramakrishna Voorakaranam, Abhijit Chatterjee |
Hierarchical Test Generation for Analog Circuits Using Incremental Test Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 296-303, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Wangning Long, Shiyuan Yang, Zhongcheng Li, Yinghua Min |
Memory Efficient ATPG for Path Delay Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 326-331, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Delay Testing, Automatic Test Generation, IC Testing, Path Sensitization |
20 | Thomas M. Sarfert, Remo G. Markgraf, Michael H. Schulz, Erwin Trischler |
A hierarchical test pattern generation system based on high-level primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1), pp. 34-44, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
20 | Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert |
SOCRATES: a highly efficient automatic test pattern generation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1), pp. 126-137, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
20 | M. Ladjadj, John F. McDonald 0001 |
Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 509-515, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
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