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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 1530 publication records. Showing 1332 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
122 | Yajuan He, Chip-Hong Chang, Jiangmin Gu, Hossam A. H. Fahmy |
A novel covalent redundant binary Booth encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 69-72, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
84 | Justin Hensley, Anselmo Lastra, Montek Singh |
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 128-137, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
84 | Chung Nan Lyu, David W. Matula |
Redundant Binary Booth Recoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 50-, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
84 | Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija |
Energy efficient implementation of parallel CMOS multipliers with improved compressors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 147-152, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
arithmetic and logic structures, VLSI, low-power design, high- speed arithmetic, booth encoding |
77 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis |
C-Testable modified-Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 241-260, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model |
71 | Min-An Song, Lan-Da Van, Chih-Chyau Yang, Shih-Chieh Chiu, Sy-Yen Kuo |
A framework for the design of error-aware power-efficient fixed-width Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 81-84, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
71 | Justin Hensley, Anselmo Lastra, Montek Singh |
An Area- and Energy-Efficient Asynchronous Booth Multiplier for Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 18-25, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
71 | Hwang-Cherng Chow, I-Chyn Wey |
A 3.3 V 1 GHz high speed pipelined Booth multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 457-460, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
71 | Li-Hsun Chen, Oscal T.-C. Chen |
A low-complexity and high-speed Booth-algorithm FIR architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 338-341, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
71 | T. Sansaloni, Javier Valls, Keshab K. Parhi |
Digit-Serial Complex-Number Multipliers on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 105-115, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
complex-number multipliers, digit-serial arithmetic, FPGA, Booth recoding |
65 | Wen-Chang Yeh, Chein-Wei Jen |
High-Speed Booth Encoded Parallel Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(7), pp. 692-701, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding |
65 | Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Effective Built-In Self-Test for Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 15(3), pp. 105-111, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Booth multipliers, Built-In Self Test, design for testability, data paths |
58 | Hong-An Huang, Yen-Chin Liao, Hsie-Chia Chang |
A self-compensation fixed-width booth multiplier and its 128-point FFT applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
58 | Hanho Lee |
Reconfigurable Power-Aware Scalable Booth Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part I, pp. 176-183, 2005, Springer, 3-540-28894-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. |
Improved-Booth encoding for low-power multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 62-65, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
52 | Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos |
Modified Booth Modulo 2n-1 Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(3), pp. 370-374, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Mersenne arithmetic, one's complement arithmetic, Booth multipliers, VLSI design, Residue Number System |
52 | Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi |
54x54-bit radix-4 multiplier based on modified booth algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 233-236, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
compressor, adder, multiplier, booth encoder, wallace tree |
52 | Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou |
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings, pp. 121-129, 1999, IEEE Computer Society, 0-7695-0325-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Modified Booth Multipliers, Low Power, Built In Self Test, VLSI Testing |
52 | Michael Nicolaidis, Ricardo de Oliveira Duarte |
Design of Fault-Secure Parity-Prediction Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 7-14, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Booth multipliers, Self-checking circuits |
52 | Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu |
Design of C-Testable Multipliers Based on the Modified Booth Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 42-47, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model |
52 | S. M. Aziz |
A C-testable modified Booth's array multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 278-282, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier |
52 | D. V. Poornaiah, P. V. Ananda Mohan |
Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 392-397, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
concurrent multiplier-accumulator architecture, second order modified Booth algorithm, sign extension bits minimization algorithm, sign-bit updating algorithm, multi-bit recoded parallel multipliers, computation time reduction, CMOS standard cell technology, 35 ns, 50 pF, parallel algorithms, VLSI, VLSI, parallel architectures, digital arithmetic, multiplication, CMOS logic circuits, multiplying circuits, accumulation, 1 micron |
45 | Hsing-Chung Liang, Pao-Hsin Huang, Yan-Fei Tang |
Testing Transition Delay Faults in Modified Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1693-1697, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Rizwan Mudassir, Mohab Anis, Javid Jaffari |
Switching activity reduction in low power Booth multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3306-3309, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
45 | Young Eun Kim, J. O. Yoon, K. J. Cho, Jin-Gyun Chung, S. I. Cho, S. S. Choi |
Efficient design of modified Booth multipliers for predetermined coefficients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
45 | Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José Monteiro 0001, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis |
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia, pp. 25-39, 2005, Springer, 978-0-387-73660-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
45 | Alok A. Katkar, James E. Stine |
Modified booth truncated multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 444-447, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
VLSI, arithmetic |
45 | Hwang-Cherng Chow, I-Chyn Wey |
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 121-124, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
45 | Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou |
Sub-word and reduced-width Booth multipliers for DSP applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 575-578, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Shugang Wei, Shuangching Chen, Kensuke Shimizu |
Fast modular multiplication using Booth recoding based on signed-digit number arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (2) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 31-36, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Raj S. Katti |
A modified Booth algorithm for high radix fixed-point multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(4), pp. 522-524, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
45 | Jos van Sas, Chay Nowé, Didier Pollet, Francky Catthoor, Paul Vanoostende, Hugo De Man |
Design of a C-testable booth multiplier using a realistic fault model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 5(1), pp. 29-41, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
test generation, design for testability, fault modelling, Array multipliers, C-testability |
45 | Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou |
A high-speed radix-4 multiplexer-based array multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 115-118, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
modified booth, multiplexer-based, radix-4 multiplier, array multiplier |
45 | Peter-Michael Seidel, Lee D. McFearin, David W. Matula |
Secondary Radix Recodings for Higher Radix Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(2), pp. 111-123, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
recoding, high radix, digit set, mixed radix representation, partial product reduction, Booth recoding, Binary multiplication |
45 | Eric M. Schwarz, Robert M. Averill III, Leon J. Sigal |
A Radix-8 CMOS S/390 Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 2-9, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Booth algorithm, computer arithmetic, multiplication, multiplier, floating-point unit |
45 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin |
Design tradeoffs in high speed multipliers and FIR filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 29-32, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high speed multipliers, high speed FIR filters, modified Booth recoding, pipeline granularity, transistor count, activity factor reduction, guarded evaluation, gate-level pipelining, half-bit level pipelining, bit-level pipelining, delay, clocking, digital filters, FIR filters, multiplying circuits, power dissipation, design tradeoffs, pipeline arithmetic, operation speed |
39 | Seokho Lee, Youngmin Kim |
Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2020, Yeosu, South Korea, October 21-24, 2020, pp. 73-74, 2020, IEEE, 978-1-7281-8331-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
39 | Hyunpil Kim, Sangook Moon, Yong-Surk Lee |
Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 11(13), pp. 20140407, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
39 | Wolfgang J. Paul, Peter-Michael Seidel |
To Booth or not to Booth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 32(1-2), pp. 5-40, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
39 | Louis P. Rubinfield |
A Proof of the Modified Booth's Algorithm for Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(10), pp. 1014-1015, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Modified Booth's algorithm, multiplicand, multiplier, partial product |
39 | Jung-Yup Kang, Jean-Luc Gaudiot |
A Simple High-Speed Multiplier Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(10), pp. 1253-1258, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Booth, modified Booth, Multiplier, partial products |
38 | Peter Heinzmann, Lothar Müller, Stéphane Racine, Ljiljana Vukelja |
The Fototeddy Strategy - Web Site Attraction Through Physical Interaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ENTER ![In: Information and Communication Technologies in Tourism, ENTER 2007, Proceedings of the International Conference in Ljubljana, Slovenia, 2007, pp. 401-412, 2007, Springer, 978-3-211-69564-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
web site promotion, human computer interaction, user experience, gesture control |
38 | Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
A New Pipelined Array Architecture for Signed Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003, pp. 65-70, 2003, IEEE Computer Society, 0-7695-2009-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
38 | Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
A New Architecture for Signed Radix-2m Pure Array Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 112-117, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
38 | Peter-Michael Seidel, Lee D. McFearin, David W. Matula |
Binary Multiplication Radix-32 and Radix-256. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 11-17 June 2001, Vail, CO, USA, pp. 23-32, 2001, IEEE Computer Society, 0-7695-1150-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian |
Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA, pp. 15-21, 2001, IEEE Computer Society, 0-7695-1122-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Wen-Lian Hsu |
PC-Trees vs. PQ-Trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COCOON ![In: Computing and Combinatorics, 7th Annual International Conference, COCOON 2001, Guilin, China, August 20-23, 2001, Proceedings, pp. 207-217, 2001, Springer, 3-540-42494-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Tim Courtney, Richard H. Turner, Roger F. Woods |
Multiplexer Based Reconfiguration for Virtex Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 749-758, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
38 | Joe Booth, Jackson Booth |
Marathon Environments: Multi-Agent Continuous Control Benchmarks in a Modern Video Game Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1902.09097, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
38 | Larry Booth, Elizabeth Vidal de Garcia, Vickie Booth, Eveling G. Castro Gutierrez |
Going Global: A Faculty Connection between Peru and the United States. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AMCIS ![In: Sustainable IT Collaboration Around the Globe. 16th Americas Conference on Information Systems, AMCIS 2010, Lima, Peru, August 12-15, 2010, pp. 560, 2010, Association for Information Systems. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
38 | David Booth, Stephane Booth |
On the mathematics behind the entropy diversification measure in strategic management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Math. Oper. Res. ![In: Int. J. Math. Oper. Res. 1(4), pp. 532-540, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
38 | Kam Fui Lau, Art Gowan, Fred Hartfield, Vickie Booth, Larry Booth, Wayne Summers |
The Georgia webBSIT: profile of an online student. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGITE Conference ![In: Proceedings of the 10th Conference on Information Technology Education, SIGITE 2009, Fairfax, Virginia, USA, October 22-24, 2009, pp. 3-7, 2009, ACM, 978-1-60558-765-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
e-learning, online learning, distance education |
38 | Kam Fui Lau, Han Reichgelt, Vickie Booth, Larry Booth, Art Gowan |
The Georgia WebBSIT: an innovative collaborative online baccalaureate degree in information technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGITE Conference ![In: Proceedings of the 9th Conference on Information Technology Education, SIGITE 2008, Cincinnati, OH, USA, October 16-18, 2008, pp. 205-212, 2008, ACM, 978-1-60558-329-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
e-learning, online learning, distance education |
32 | Chiou-Yng Lee, Yu-Hsin Chiu, Che Wun Chiou |
New Bit-Parallel Systolic Multiplier over GF(2m) Using The Modified Booth's Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 610-613, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
32 | Daniel Marienfeld, Egor S. Sogomonyan, Vitalij Ocheretnij, Michael Gössel |
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 76-81, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
32 | Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury |
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece, pp. 207-215, 2004, IEEE Computer Society, 0-7695-2133-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
32 | Jin-Hua Hong, Cheng-Wen Wu |
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 474-484, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Hao-Yung Lo, Hsiu-Feng Lin, Chichyang Chen, Jenshiuh Liu, Chia-Cheng Liu |
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(3), pp. 245-269, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generator, BIST, computer arithmetic, polynomials, VLSI design, multiplication, division |
32 | Shugang Wei, Kensuke Shimizu |
Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 221-224, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
32 | Kiwon Choi, Minkyu Song |
Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 701-704, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
32 | Michael Nicolaidis, Ricardo de Oliveira Duarte |
Fault-Secure Parity Prediction Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 16(3), pp. 90-101, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
32 | Kazue Sako, Joe Kilian |
Receipt-Free Mix-Type Voting Scheme - A Practical Solution to the Implementation of a Voting Booth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '95, International Conference on the Theory and Application of Cryptographic Techniques, Saint-Malo, France, May 21-25, 1995, Proceeding, pp. 393-403, 1995, Springer, 3-540-59409-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
32 | Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr. |
Modified Booth algorithm for high radix fixed-point multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 164-167, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
32 | Jalil Fadavi-Ardekani |
M×N Booth encoded multiplier generator using optimized Wallace trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 120-125, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
32 | Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002 |
High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2006, 9th International Conference, Busan, Korea, November 30 - December 1, 2006, Proceedings, pp. 81-93, 2006, Springer, 3-540-49112-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder |
32 | Yijun Liu, Stephen B. Furber |
The design of a low power asynchronous multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 301-306, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Booth's algorithm, low power, benchmark, multiplier, asynchronous logic |
32 | Wieland Fischer, Jean-Pierre Seifert |
High-Speed Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CT-RSA ![In: Topics in Cryptology - CT-RSA 2004, The Cryptographers' Track at the RSA Conference 2004, San Francisco, CA, USA, February 23-27, 2004, Proceedings, pp. 264-277, 2004, Springer, 3-540-20996-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Sedlaks algorithm, Computer arithmetic, Modular multiplication, Implementation issues, Booth recoding |
32 | Wieland Fischer, Jean-Pierre Seifert |
Unfolded Modular Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISAAC ![In: Algorithms and Computation, 14th International Symposium, ISAAC 2003, Kyoto, Japan, December 15-17, 2003, Proceedings, pp. 726-735, 2003, Springer, 3-540-20695-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Sedlaks algorithm, Computer arithmetic, Modular multiplication, Implementation issues, Booth recoding |
32 | Geoff Knagge, David Garrett, Sivarama Venkatesan, Chris Nicol |
Matrix datapath architecture for an iterative 4x4 MIMO noise whitening algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 153-156, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
matrix multipliction, noise whitening, MIMO, booth recoding |
32 | Michael J. Schulte, James E. Stine |
Symmetric Bipartite Tables for Accurate Function Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 175-183, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
approximations, computer arithmetic, error analysis, table lookup, Elementary functions, Taylor series, symmetric, bipartite, Booth encoding, accurate |
32 | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita |
Power analysis and low-power scheduling techniques for embedded DSP software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), September 13-15, 1995, Cannes, France, pp. 110-115, 1995, ACM, 0-89791-771-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor |
32 | Menghui Zheng, Alexander Albicki |
Low power and high speed multiplication design through mixed number representations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 566-576, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products |
32 | Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami |
A fast-multiplier generator for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 53-56, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips |
32 | Richard Booth 0001, Thomas Andreas Meyer |
On the Dynamics of Total Preorders: Revising Abstract Interval Orders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECSQARU ![In: Symbolic and Quantitative Approaches to Reasoning with Uncertainty, 9th European Conference, ECSQARU 2007, Hammamet, Tunisia, October 31 - November 2, 2007, Proceedings, pp. 42-53, 2007, Springer, 978-3-540-75255-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Minhyeok Shin, Hanho Lee |
A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 960-963, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | E. Vincent Cross II, Yolanda McMillian, Priyanka Gupta, Philicity Williams, Kathryn Nobles, Juan E. Gilbert |
Prime III: a user centered voting system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: Extended Abstracts Proceedings of the 2007 Conference on Human Factors in Computing Systems, CHI 2007, San Jose, California, USA, April 28 - May 3, 2007, pp. 2351-2356, 2007, ACM, 978-1-59593-642-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Cecilia Katzeff, Vanessa Ware |
Video storytelling as mediation of organizational learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NordiCHI ![In: Proceedings of the 4th Nordic Conference on Human-Computer Interaction 2006, Oslo, Norway, October 14-18, 2006, pp. 311-320, 2006, ACM, 1-59593-325-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
music festival, volunteer work, video, storytelling, communities of practice, workplace learning |
26 | Mateus Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José Monteiro 0001 |
Design of a radix-2m hybrid array multiplier using carry save adder format. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 172-177, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
hybrid multiplier, low power, carry save adder |
26 | Li-Hsun Chen, Oscal T.-C. Chen, Teng-Yi Wang, Yung-Cheng Ma |
A multiplication-accumulation computation unit with optimized compressors and minimized switching activities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 6118-6121, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Li-Hsun Chen, Oscal T.-C. Chen |
A hardware-efficient FIR architecture with input-data and tap folding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 544-547, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Oscal T.-C. Chen, Sandy Wang, Yi-Wen Wu |
Minimization of switching activities of partial products for designing low-power multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(3), pp. 418-433, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | David W. Matula, Alex Fit-Florea |
Prescaled Integer Division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 15-18 June 2003, Santiago de Compostela, Spain, pp. 63-, 2003, IEEE Computer Society, 0-7695-1894-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
26 | Masayuki Abe, Koutarou Suzuki |
Receipt-Free Sealed-Bid Auction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Information Security, 5th International Conference, ISC 2002 Sao Paulo, Brazil, September 30 - October 2, 2002, Proceedings, pp. 191-199, 2002, Springer, 3-540-44270-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
bid-rigging, receipt-free, chameleon bit-commitment, Sealed-bid auction |
26 | Nan-Ying Shen, Oscal T.-C. Chen |
Low-power multipliers by minimizing switching activities of partial products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 93-96, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Johann Großschädl |
A unified radix-4 partial product generator for integers and binary polynomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 567-570, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Oscal T.-C. Chen, Wei-Lung Liu |
An FIR processor with programmable dynamic data ranges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(4), pp. 440-446, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
26 | Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn |
The SNAP Project: Design of Floating Point Arithmetic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 13th Symposium on Computer Arithmetic (ARITH-13 '97), 6-9 July 1997, Asilomar, CA, USA, pp. 156-, 1997, IEEE Computer Society, 0-8186-7846-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit |
20 | Srikant Kumar Beura, Sudeshna Manjari Mahanta, Bishnulatpam Pushpa Devi, Prabir Saha |
Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 94, pp. 102096, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Srikanth Immareddy, Arunmetha Sundaramoorthy, Aravindhan Alagarsamy |
Design and implementation of hybrid (radix-8 Booth and TRAM) approximate multiplier using 15-4 approximate compressors for image processing application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Real Time Image Process. ![In: J. Real Time Image Process. 21(2), pp. 50, April 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Muhammad Hamis Haider, Hao Zhang 0041, Seok-Bum Ko |
Decoder Reduction Approximation Scheme for Booth Multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 73(3), pp. 735-746, March 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
20 | Xinhui Kang, Shin'ya Nagasawa |
Integrating evaluation grid method and support vector regression for automobile trade booth design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Fuzzy Syst. ![In: J. Intell. Fuzzy Syst. 44(5), pp. 7709-7722, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Yongxia Sheng, Huaguo Liang, Bao Fang, Cuiyun Jiang, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu |
Design of approximate Booth multipliers based on error compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 90, pp. 183-189, May 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Gunho Park, Jaeha Kung, Youngjoo Lee |
Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(3), pp. 1154-1158, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao 0002, Masanori Hashimoto, Hao Yu 0001 |
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2246-2250, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Muhammad Hamis Haider, Seok-Bum Ko |
Booth Encoding-Based Energy Efficient Multipliers for Deep Learning Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 70(6), pp. 2241-2245, June 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Basant Kumar Mohanty |
Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Emerg. Sel. Topics Circuits Syst. ![In: IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1), pp. 165-174, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Michael Madden 0003, Dan Szafaran, Philomena Gray, Justin Pelletier, Ted Selker |
A Canary in the Voting Booth: Attacks on a Virtual Voting Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDF2C (1) ![In: Digital Forensics and Cyber Crime - 14th EAI International Conference, ICDF2C 2023, New York City, NY, USA, November 30, 2023, Proceedings, Part I, pp. 3-18, 2023, Springer, 978-3-031-56579-3. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Zainab Aizaz, Kavita Khare, Aizaz Tirmizi |
FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023, pp. 210, 2023, IEEE, 979-8-3503-1205-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Keshav Thosar, Hargobind Singh, Sreejit Chatterjee, Dayanand Ambawade |
Blockchain-based Booth-less Tolling System using GPS and Image Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AIIoT ![In: 2023 IEEE World AI IoT Congress (AIIoT), Seattle, WA, USA, June 7-10, 2023, pp. 380-383, 2023, IEEE, 979-8-3503-3761-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
20 | Eunice Gabrielle A. Reyes, Gerome Kaye M. Cangco, Shiela Mae C. Ilagan, Hazel P. Pacunayen, Jeunise A. Piamonte, Josephine D. German |
An Application of Queueing Theory on the Ticketing Booth of Light Rail Transit 1 (LRT-1) Central Station. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSIE ![In: 5th International Conference on Management Science and Industrial Engineering, MSIE 2023, Chiang Mai, Thailand, April 27-29, 2023, pp. 192-198, 2023, ACM. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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