Search results for "CDR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
213	C. W. Ong, J. C. Tay	A Robust Rule-Based Event Management Architecture for Call-Data Records.	KES	2004	DBLP DOI BibTeX RDF	CDR loss rate, event filtering and correlation, Rule-based system
105	Dongwoo Hong, Kwang-Ting (Tim) Cheng	Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links.	VTS	2008	DBLP DOI BibTeX RDF	Bang-Bang CDR, BER Estimation
79	Sitt Tontisirin, Reinhard Tielert	A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock.	ISCAS	2006	DBLP DOI BibTeX RDF
77	Pin-Han Ho, János Tapolcai, Tibor Cinkler	Segment shared protection in mesh communications networks with bandwidth guaranteed tunnels.	IEEE/ACM Trans. Netw.	2004	DBLP DOI BibTeX RDF	survivable routing, working and protection paths, integer linear programming (ILP), shared risk link group (SRLG), segment shared protection (SSP)
64	Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang, Guohui Situ, Tad A. Kwasniewski	A full-rate truly monolithic CMOS CDR for low-cost applications.	CCECE	2009	DBLP DOI BibTeX RDF
64	Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici	A low-power, multichannel gated oscillator-based CDR for short-haul applications.	ISLPED	2005	DBLP DOI BibTeX RDF
62	Amna Humayun, Wafa Basit, Ghulam A. Farrukh, Fakhar Lodhi, Rabea Aden	An empirical analysis of team review approaches for teaching quality software development.	ICSE (1)	2010	DBLP DOI BibTeX RDF
62	Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang	A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique.	ISCAS	2006	DBLP DOI BibTeX RDF
58	Giorgio Corani, Chris Edgar, Isabelle Marshall, Keith Wesnes, Marco Zaffalon	Classification of Dementia Types from Cognitive Profiles Data.	PKDD	2006	DBLP DOI BibTeX RDF	CDR computerized assessment system, classification, dementia
55	Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe	High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique.	VLSI Design	2010	DBLP DOI BibTeX RDF	Clock and data recovery (CDR), CDR jitter, Phase
48	Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli	A 1/4 rate linear phase detector for PLL-based CDR circuits.	ISCAS	2006	DBLP DOI BibTeX RDF
48	Francesco Centurelli, Alessandro Golfarelli, Jesus Guinea, Leonardo Masini, Damiana Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti	A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
48	M. Ramezani, C. André T. Salama	A 10Gb/s CDR with a half-rate bang-bang phase detector.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
48	Jeroen Wijnands, Sietse Dijkstra, Wijnand Derks, Willem Jonker	Experimenting NT Cluster Technology for Massive CDR Processing.	Databases in Telecommunications	2001	DBLP DOI BibTeX RDF
48	Wijnand Derks, Sietse Dijkstra, H. D. Enting, Willem Jonker, Jeroen Wijnands	Experimenting NUMA for Scalable CDR Processing.	DEXA	2000	DBLP DOI BibTeX RDF
46	Ralph Lange, Frank Dürr, Kurt Rothermel	Online trajectory data reduction using connection-preserving dead reckoning.	MobiQuitous	2008	DBLP DOI BibTeX RDF	online trajectory reduction, dead reckoning, MOD
46	William R. Dieter, Henry G. Dietz	Computer Aided Engineering of Cluster Computers.	ISPASS	2008	DBLP DOI BibTeX RDF
46	Jingyan Xu, Chi Liu, Yuchuan Wang, Eric C. Frey, Benjamin M. W. Tsui	Quantitative Rotating Multisegment Slant-Hole SPECT Mammography With Attenuation and Collimator-Detector Response Compensation.	IEEE Trans. Medical Imaging	2007	DBLP DOI BibTeX RDF
46	David Rennie, Manoj Sachdev	Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
46	Hyoungsoo Kim, Youngsik Hur, Moonkyun Maeng, Franklin Bien, Soumya Chandramouli, Edward Gebara, Joy Laskar	A Novel Clock Recovery Scheme with Improved Jitter Tolerance for PAM4 Signaling.	IWSOC	2005	DBLP DOI BibTeX RDF
46	Sung-Eun Kim, Seong-Jun Song, Sung Min Park 0001, Hoi-Jun Yoo	CMOS optical receiver chipset for gigabit Ethernet applications.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
46	Thorsten Adler, Erich Barke	Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications.	DATE	2000	DBLP DOI BibTeX RDF
46	Hormoz Djahanshahi, C. André T. Salama	Differential 0.35µm CMOS circuits for 622 MHz/933 MHz monolithic clock and data recovery applications.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
46	Zhong Shao, John H. Reppy, Andrew W. Appel	Unrolling Lists.	LISP and Functional Programming	1994	DBLP DOI BibTeX RDF
35	Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim	A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces.	ISSCC	2022	DBLP DOI BibTeX RDF
35	Manoranjan Dash, Kee Kiat Koo, James Decraene, Ghim-Eng Yap, Wei Wu 0020, João Bártolo Gomes, Amy Shi Nash, Xiaoli Li 0001	CDR-To-MoVis: Developing a Mobility Visualization System from CDR data.	ICDE	2015	DBLP DOI BibTeX RDF
31	Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi	An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
31	Jonathan H. Morra, Zhuowen Tu, Liana G. Apostolova, Amity E. Green, Christina Avedissian, Sarah K. Madsen, Neelroop Parikshak, Xue Hua, Arthur W. Toga, Clifford R. Jack, Norbert Schuff, Michael Weiner, Paul M. Thompson	Mapping hippocampal degeneration in 400 subjects with a novel automated segmentation approach.	ISBI	2008	DBLP DOI BibTeX RDF
31	David Rennie, Manoj Sachdev	A Novel Tri-State Binary Phase Detector.	ISCAS	2007	DBLP DOI BibTeX RDF
31	Chang-Kyung Seong, Seung-Woo Lee, Woo-Young Choi	A 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit with enhanced phase resolution.	ISCAS	2006	DBLP DOI BibTeX RDF
31	Farah Khan, Nigel Baker	Optimization of Charging Control in 3G Mobile Networks.	NEW2AN	2006	DBLP DOI BibTeX RDF	Charging data, Tariff Models, UMTS, Opnet
31	David McSherry	Completeness Criteria for Retrieval in Recommender Systems.	ECCBR	2006	DBLP DOI BibTeX RDF
31	Mark H. Carpenter, C. A. Kennedy, Hester Bijl, S. A. Viken, Veer N. Vatsa	Fourth-Order Runge-Kutta Schemes for Fluid Mechanics Applications.	J. Sci. Comput.	2005	DBLP DOI BibTeX RDF	backward differentiation formulae, modified extended efficiency, convection-diffusion-reaction, turbulence, time discretization, Runge-Kutta, High-order
31	François Bouteruche, Éric Anquetil, Nicolas Ragot	Handwritten Gesture Recognition Driven by the Spatial Context of Strokes.	ICDAR	2005	DBLP DOI BibTeX RDF
31	Ching-Hsien Hsu, Kun-Ming Yu	A Compressed Diagonals Remapping Technique for Dynamic Data Redistribution on Banded Sparse Matrix.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	compressed diagonals remapping, parallel algorithm, sparse matrix, runtime support, data redistribution, banded matrix
31	Longzhuang Li, Yi Shang, Wei Zhang, Hongchi Shi	A General Method for Statistical Performance Evaluation.	HICSS	2003	DBLP DOI BibTeX RDF
31	Ching-Hsien Hsu, Kun-Ming Yu	A Compressed Diagonals Remapping Technique for Dynamic Data Redistribution on Banded Sparse Matrix.	ISPA	2003	DBLP DOI BibTeX RDF
31	Stefano A. Cerri, Vincenzo Loia	A Concurrent, Distributed Architecture for Diagnostic Reasoning.	User Model. User Adapt. Interact.	1997	DBLP DOI BibTeX RDF	ABCL/1 programming language, actors, student modeling, concurrent object-oriented programming, diagnostic reasoning, actor model
31	Michel Parigot	On the Representation of Data in Lambda-Calculus.	CSL	1989	DBLP DOI BibTeX RDF
28	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
18	Li Wang 0083, Zhao Zhang 0004, Can Wang 0009, Rehan Azmat, Weimin Shi, C. Patrick Yue	A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
18	Kim Valerie Carl, Oliver Hinz	What we already know about corporate digital responsibility in IS research: A review and conceptualization of potential CDR activities.	Electron. Mark.	2024	DBLP DOI BibTeX RDF
18	Zhijia Yang, Byron Mason, Edward Winward, Mark Cary	Two-Dimensional Transient Cycle Decomposition and Reduction (CDR) for Data Driven Nonlinear Dynamic System Modeling.	IEEE Access	2024	DBLP DOI BibTeX RDF
18	Hua Qin, Weihong Chen, Ni Li, Tao Wang, Yaqi Deng, Gelan Yang, Yang Peng	CDR: Bandwidth-Efficient Cross-Interface Downlink Relay Scheme for Low-Power Multihop Wireless Networks.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
18	Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu	A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
18	Hsi-Kai Peng, Shen-Iuan Liu	A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
18	Yi-Hao Lan, Shen-Iuan Liu	A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
18	Woosung Jeon, Dongsup Kim	AbFlex: designing antibody complementarity determining regions with flexible CDR definition.	Bioinform.	2024	DBLP DOI BibTeX RDF
18	Yen-Po Lin, Pen-Jui Peng, Chun-Chang Lu, Po-Ting Shen, Yun-Cheng Jao, Ping-Hsuan Hsieh	7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.	ISSCC	2024	DBLP DOI BibTeX RDF
18	Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, Byungsub Kim	A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin	A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement.	IEEE J. Solid State Circuits	2023	DBLP DOI BibTeX RDF
18	Qingzhi Hou, Honghan Du, Zewei Sun, Jianping Wang, Xiaojing Wang, Jianguo Wei	PINN-CDR: A Neural Network-Based Simulation Tool for Convection-Diffusion-Reaction Systems.	Int. J. Intell. Syst.	2023	DBLP DOI BibTeX RDF
18	Woojung Kim, Woojin Hong, Jae Joon Kim, Myunghee Lee	A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless CDR With an Unlimited Bilateral Frequency Detection Scheme.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
18	Xiangyu Meng 0003, Wang Xie, Jiaqi Zhang, Zhao Zhang 0004	A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
18	Viren Dias, Lasantha Fernando, Yusen Lin, Vanessa Frías-Martínez, Louiqa Raschid	Framework to Study Migration Decisions Using Call Detail Record (CDR) Data.	IEEE Trans. Comput. Soc. Syst.	2023	DBLP DOI BibTeX RDF
18	Zhen Gu, Xiaojun Bi 0003	28 Gbaud PAM-4 Burst-Mode CDR With Reconfigurable Sampling Scheme.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
18	Sanghee Lee, Byungjun Kang, Woogeun Rhee, Deog-Kyoon Jeong	A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Yu-Hong Yang, Mou Tzou, Tai-Cheng Lee	A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
18	Jianli Zhao, Lutong Yao, Tingting Li, Lijun Qu, Sheng Fang 0001, Shidong Zheng, Maoguo Gong, Liang Li, Hao Li, Tianheng Zhang	CDR-ULPT:Cross-domain recommendation for e-commerce using user-level preferences transfer network.	Electron. Commer. Res. Appl.	2023	DBLP DOI BibTeX RDF
18	Yang Li 0130, Zihou Guo, Xin Gao 0001, Guohua Wang	MMCL-CDR: enhancing cancer drug response prediction with multi-omics and morphology images contrastive representation learning.	Bioinform.	2023	DBLP DOI BibTeX RDF
18	Yanyu Chen, Yao Yao 0006, Wai Kin Victor Chan, Li Xiao, Kai Zhang, Liang Zhang, Yun Ye	CDR-Adapter: Learning Adapters to Dig Out More Transferring Ability for Cross-Domain Recommendation Models.	CoRR	2023	DBLP DOI BibTeX RDF
18	Zijie Song, Jiawei Chen 0007, Sheng Zhou 0004, Qihao Shi, Yan Feng, Chun Chen 0001, Can Wang 0001	CDR: Conservative Doubly Robust Learning for Debiased Recommendation.	CoRR	2023	DBLP DOI BibTeX RDF
18	Eleni Giovanoudi, Dimitrios Rafailidis	Multi-Task Learning with Loop Specific Attention for CDR Structure Prediction.	CoRR	2023	DBLP DOI BibTeX RDF
18	Wenya Chen, Qingsong Cai, Zhong Yang, Shushan Qiao	A 0.8-6Gb/s wireline receiver based on the spectrum-balancing equalizer and semi-digital dual loop CDR.	IEICE Electron. Express	2023	DBLP DOI BibTeX RDF
18	Zijie Song, Jiawei Chen 0007, Sheng Zhou 0004, Qihao Shi, Yan Feng, Chun Chen 0001, Can Wang 0001	CDR: Conservative Doubly Robust Learning for Debiased Recommendation.	CIKM	2023	DBLP DOI BibTeX RDF
18	Hanho Choi, Ha-Il Song, Hyosup Won, Jun Young Yoo, Woohyun Kwon, Huxian Jin, Konan Kwon, Cheong Min Lee, Gain Kim, Jake Eu, Sean Park, Hyeon-Min Bae	An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm.	ESSCIRC	2023	DBLP DOI BibTeX RDF
18	Zhaoyu Zhang, Zhao Zhang 0004, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE.	ESSCIRC	2023	DBLP DOI BibTeX RDF
18	Zhao Zhang 0004, Zhaoyu Zhang, Yong Chen, Nan Qi, Jian Liu 0021, Nanjian Wu, Liyuan Liu	A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
18	Yuqing Mao, Yoann Charlon, Yves Leduc, Gilles Jacquemod	New design of an ultra low power CDR architecture using FDSOI 28 nm technology.	NEWCAS	2023	DBLP DOI BibTeX RDF
18	Chien-Kai Kao, Shih-Che Hung, Tse-Hsien Yeh, Chen-Yu Hsiao	A 37.8dB Channel Loss 0.6μs Lock Time CDR with Flash Frequency Acquisition in 5nm FinFET.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Seungwoo Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Hyunsu Park, Youngwook Kwon, Chulwoo Kim	A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications.	ISSCC	2023	DBLP DOI BibTeX RDF
18	Xiaowen Shao, Baisong Liu, Xueyuan Zhang, Junru Li, Ercong Xu, Shiqi Wu	Graph Collaborative Filtering and Data Augmentation Strategies in Dual-Target CDR.	CoopIS	2023	DBLP DOI BibTeX RDF
18	Aki Nagano	Institutional Values and CDR for Green ITC: Transforming E-waste to Ethical Gems.	WINCOM	2023	DBLP DOI BibTeX RDF
18	Woosong Jung, Minkyo Shim, Seungha Roh, Deog-Kyoon Jeong	A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector.	ISCAS	2023	DBLP DOI BibTeX RDF
18	Oliver Bollverk, Amnir Hadachi	CDR-based Trajectory Reconstruction of Mobile Network Data Using Transformers.	MT-ITS	2023	DBLP DOI BibTeX RDF
18	Xin Lu, Heng Zhang, Leilei Wang, Tao Fang, Chunhui Zhang, Feng Wang, Li Du, Yashe Liu, Xiangfei Chen, Yuan Du	A Non-Centralized Routing Scheme with Phase-Caching CDR for Nanosecond-Level Optical Switching Systems.	ASICON	2023	DBLP DOI BibTeX RDF
18	Seoung-Geun Cho, Jin-Ku Kang	A PAM-4 Baud-Rate CDR with High-Gain Phase Detector Using Shared Sampler.	ISOCC	2023	DBLP DOI BibTeX RDF
18	Shu-Chi Wang, Ching-Yuan Yang	Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector.	ISOCC	2023	DBLP DOI BibTeX RDF
18	Sihan Kim, Changmin Song, Jinseok Kim, Yonghun Oh, Changwan Kim, Young-Chan Jang	A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller.	ISOCC	2023	DBLP DOI BibTeX RDF
18	Yanyu Chen, Yao Yao 0006, Wai Kin Victor Chan, Li Xiao, Kai Zhang, Liang Zhang, Yun Ye	CDR-Adapter: Learning Adapters to Dig Out More Transferring Ability for Cross-Domain Recommendation Models.	eCom@SIGIR	2023	DBLP BibTeX RDF
18	Shakeeb Abdullah, John W. M. Rogers, Wenyu Zhou, Rony E. Amaya	A 56 GHz InP VCO for Use in 112 GBaud (112 GBit/s NRZ or 224 GBit/s PAM-4) InP Integrated Optical Receiver Front-End CDR Block.	CCECE	2023	DBLP DOI BibTeX RDF
18	Cláudia Rodrigues, Marco Veloso, Ana Alves 0001, Carlos Bento	Using CDR Data to Understand Post-pandemic Mobility Patterns.	EPIA (2)	2023	DBLP DOI BibTeX RDF
18	Xiaoteng Zhao, Yong Chen 0005, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins	A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang 0187, Leliang Li, Guike Li, Zhao Zhang 0004, Jian Liu 0021, Nanjian Wu, Liyuan Liu, Yong Chen 0005, Xi Xiao, Nan Qi	A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Xiaoteng Zhao, Yong Chen 0005, Pui-In Mak, Rui Paulo Martins	A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Haram Ju, Kwangho Lee, Kwanseo Park, Woosong Jung, Deog-Kyoon Jeong	Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Tae-Jin Kim, Jae-Woo Park, Hyun-Wook Lim, Jae-Youl Lee, Jung-Hoon Chun	An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Guanrong Hou, Behzad Razavi	A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Kwanseo Park, Minkyo Shim, Han-Gon Ko, Borivoje Nikolic, Deog-Kyoon Jeong	Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
18	Na Yang, Hang Yu, Ying Lu, Yehui Zhang, Yunchuan Zheng	Evaluating the Applicability of PERSIANN-CDR Products in Drought Monitoring: A Case Study of Long-Term Droughts over Huaihe River Basin, China.	Remote. Sens.	2022	DBLP DOI BibTeX RDF
18	Alexander Huber	CDR bei Einsatz von KI in Unternehmensführung und algorithmischen Entitäten.	Wirtschaftsinformatik Manag.	2022	DBLP DOI BibTeX RDF
18	Tawfiq Musah, Abishek Namachivayam	Robust Timing Error Detection for Multilevel Baud-Rate CDR.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Meysam M. Khanghah, Khosrov Dabbagh-Sadeghipour, Denis Kelly, Cleitus Antony, Peter Ossieur, Paul D. Townsend	A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
18	Sanggeun Lee, Ramesh Harjani, Taehyoun Oh	Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Yun-Sheng Yao, Chang-Cheng Huang, Shen-Iuan Liu	A Wide-Range FD for Referenceless Baud-Rate CDR Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Wei-Ming Chen, Yun-Sheng Yao, Shen-Iuan Liu	A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong	A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Wen-Chi Huang, Shen-Iuan Liu	A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Ankur Bal, Rupesh Singh, Aradhana Kumari, Vikas Dhanda	A Low-Cost 0.00063-mm2, 0.44-pJ/b, 2-Gb/s All-Digital Fully Synthesizable CDR for Serial Links Using Single-Phase Input Clock.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
18	Brennan Abanades, Guy Georges, Alexander Bujotzek, Charlotte M. Deane	ABlooper: fast accurate antibody CDR loop structure prediction with accuracy estimation.	Bioinform.	2022	DBLP DOI BibTeX RDF