Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
169 | Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee |
Prospect of ballistic CNFET in high performance applications: Modeling and analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(3), pp. 12, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance |
169 | Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee |
Modeling and analysis of circuit performance of ballistic CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 717-722, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance |
123 | Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi |
Performance assessment of analog circuits with carbon nanotube FET (CNFET). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 163-166, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
analog, circuits |
120 | Saurabh Sinha, Asha Balijepalli, Yu Cao |
A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 502-507, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Schottky barrier, analog design metrics, modeling, CNT |
100 | Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong |
Carbon nanotube transistor compact model for circuit design and performance optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(2), pp. 7:1-7:20, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
VerilogA, carbon nanotube FET, compact model, CNT, HSPICE |
87 | Nishant Patil, Albert Lin, Jie Zhang 0007, H.-S. Philip Wong, Subhasish Mitra |
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 304-309, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CNFET, carbon nanotube transistor, carbon nanotubes |
80 | Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra |
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(10), pp. 1725-1736, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
80 | Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra |
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 958-961, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Hamidreza Hashempour, Fabrizio Lombardi |
Device Model for Ballistic CNFETs Using the First Conducting Band. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 178-186, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CNFET, charge density, self-consistent voltage, drain-source current, CAD, approximation, carbon nanotube, closed-form |
67 | Chaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee |
Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 250-255, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
RF performance, carbon nanotube FET (CNFET), modeling |
63 | Jie Zhang 0007, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra |
Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 889-892, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CNT correlation, carbon nanotube, yield optimization, CNT |
60 | Bao Liu 0001 |
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 853-858, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
60 | Jie Zhang 0007, Nishant Patil, Arash Hazeghi, Subhasish Mitra |
Carbon nanotube circuits in the presence of carbon nanotube density variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 71-76, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CNT correlation, CNT density variation, carbon nanotube, CNT |
60 | Jie Zhang 0007, Nishant Patil, Subhasish Mitra |
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1009-1014, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
60 | Wei Zhang 0012, Niraj K. Jha |
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 281-288, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
50 | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli |
Programmable logic circuits based on ambipolar CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 339-340, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CNFET, FPGA, PLA, carbon nanotube |
47 | Kaustav Banerjee, Yasin Khatami, Chaitanya Kshirsagar, Seid Hadi Rasouli |
Graphene based transistors: physics, status and future perspectives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 65-66, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
cnfet, gnr-fet., graphene, carbon nanotubes |
23 | Ahmad Karimi, Keivan Navi |
The design of adder, subtractor, and derivative circuits without the use of op-amp in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 113, pp. 109047, January 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
23 | Zihao Yang, Minghui Yin, Yunxia You, Zhiqiang Li, Xin Liu, Weihua Zhang |
Design of a high performance CNFET 10T SRAM cell at 5nm technology node. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(12), pp. 20230171, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda |
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023, Tokyo, Japan, January 16-19, 2023, pp. 763-768, 2023, ACM, 978-1-4503-9783-4. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Shivani Thakur, Srinivasu Bodapati |
Ternary Systolic Array Architecture for Matrix Multiplication in CNFET-Memristor Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2023, Hyderabad, India, November 19-22, 2023, pp. 45-49, 2023, IEEE, 979-8-3503-8119-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Ali Ghorbani, Mehdi Dolatshahi, Sayed Mohammad Ali Zanjani, Behrang Barekatain |
A new low-power Dynamic-GDI full adder in CNFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 83, pp. 46-59, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Mehdi Takbiri, Keivan Navi, Reza Faghih Mirzaee |
Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 10553-10565, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Rongmei Chen, Lin Chen, Jie Liang, Yuanqing Cheng, Souhir Elloumi, Jaehyun Lee, Kangwei Xu, Vihar P. Georgiev, Kai Ni 0004, Peter Debacker, Asen Asenov, Aida Todri-Sanial |
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(4), pp. 432-439, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Huawei Li 0001, Xiaowei Li 0001 |
Taming Process Variations in CNFET for Efficient Last-Level Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 30(4), pp. 418-431, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Aiswarya Satheesh, Kilari Pragnaa, Sanjay Vidhyadharan |
High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 41(8), pp. 4649-4670, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Mostafa Parvizi, Rana Haratian |
A High-Frequency Multi-Mode Universal Filter for GHz Applications in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(16), pp. 2250288:1-2250288:14, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 123(1), pp. 357-373, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Samaneh Goldani Gigasari, Mohammad Mirzaei, Hamidreza Uoosefian |
A Novel Highly-Efficient Inexact Full Adder Cell for Motion and Edge Detection Systems of Image Processing in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 18(4), pp. 74:1-74:20, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Cheng Chu, Dawen Xu 0002, Ying Wang 0001, Fan Chen 0001 |
Canopy: A CNFET-based Process Variation Aware Systolic DNN Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022, pp. 24:1-24:6, 2022, ACM, 978-1-4503-9354-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Zahra Heshmatpour, Lihong Zhang, Howard M. Heys |
Multi-Objective Variation-Aware Sizing for Analog CNFET Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 23rd International Symposium on Quality Electronic Design, ISQED 2022, Santa Clara, CA, USA, April 6-7, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9466-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Zahra Heshmatpour, Lihong Zhang, Howard M. Heys |
Robust CNFET Circuit Sizing Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022, Hsinchu, Taiwan, April 18-21, 2022, pp. 1-4, 2022, IEEE, 978-1-6654-0921-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Panasa Srikanth, B. Srinivasu |
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers, pp. 420-434, 2022, Springer, 978-3-031-21513-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Jihad Mohamad Jaam, Bilal N. Owaydat, Somaya Ali Al-Máadeed, Abdallah Kassem, Ali Massoud Haidar 0001 |
Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 115951-115961, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani |
Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(7), pp. 3523-3535, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan |
CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(8), pp. 4089-4105, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Hamidreza Uoosefian, Keivan Navi, Reza Faghih Mirzaee, Mehdi Hosseinzadeh 0001 |
Two Novel Current-Mode CNFET-Based Full Adders Using ULPD as Voltage Regulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 30(6), pp. 2150101:1-2150101:28, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Zahra Zareei, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, Yavar Safaei Mehrabani |
Design of efficient approximate 1-bit Full Adder cells using CNFET technology applicable in motion detector systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 108, pp. 104962, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 113, pp. 105105, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Abhay S. Vidhyadharan, Sanjay Vidhyadharan |
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 107, pp. 104961, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Dawen Xu 0002, Zhuangyu Feng, Cheng Liu 0008, Li Li, Ying Wang 0001, Yuanqing Cheng, Huawei Li 0001, Xiaowei Li 0001 |
Taming Process Variations in CNFET for Efficient Last Level Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2108.05023, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
23 | Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri |
CNFET-based design of efficient ternary half adder and 1-trit multiplier circuits using dynamic logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2110.02223, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
23 | Daniel Etiemble |
Comments on "High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 220015-220016, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Akbar Doostaregan, Adib Abrishamifar |
Evaluating a Methodology for Designing CNFET-Based Ternary Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 39(10), pp. 5039-5058, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Amin Avan, Mojtaba Maleknejad, Keivan Navi |
High-speed energy efficient process, voltage and temperature tolerant hybrid multi-threshold 4: 2 compressor design in CNFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 14(3), pp. 357-368, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Sandeep Garg, Tarun Kumar Gupta, Amit Kumar Pandey |
A 1-bit full adder using CNFET based dual chirality high speed domino logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 48(1), pp. 115-133, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Ahmad M. El-Hajj, Abdallah Kassem, Lina A. Nimri, Ali M. Haidar 0001 |
CNFET-based designs of Ternary Half-Adder using a novel "decoder-less" ternary multiplexer based on unary operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 96, pp. 104698, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Trapti Sharma, Laxmi Kumre |
CNFET based design of unbalanced ternary circuits using efficient shifting literals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 104, pp. 104869, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Ahmad M. El-Hajj, Ali M. Haidar 0001, Abdallah Kassem |
A Novel CNFET-Based Ternary to Binary Converter Design in Data Transmission. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 32nd International Conference on Microelectronics, ICM 2020, Aqaba, Jordan, December 14-17, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-9664-0. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Lan Wei |
Reducing Impact of CNFET Process Imperfections on Shape of Activation Function by Using Connection Pruning and Approximate Neuron Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 21st International Symposium on Quality Electronic Design, ISQED 2020, Santa Clara, CA, USA, March 25-26, 2020, pp. 279-284, 2020, IEEE, 978-1-7281-4207-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Ramzi A. Jaber, Abdallah Kassem, Ahmad M. El-Hajj, Lina A. Nimri, Ali Massoud Haidar 0001 |
High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 93871-93886, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Muhammad Ali 0006, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske |
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(3), pp. 573-586, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Akbar Doostaregan, Adib Abrishamifar |
A New Method for Design of CNFET-Based Quaternary Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 38(6), pp. 2588-2606, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Sepehr Tabrizchi, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh |
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 13(2), pp. 193-202, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Samane Firouzi, Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy |
High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 77, pp. 205-216, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Seyyed Ashkan Ebrahimi, Mohammad Reza Reshadinezhad, Ali Bohlooli |
A new design method for imperfection-immune CNFET-based circuit design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 85, pp. 62-71, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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23 | Soumitra Pal 0002, Vivek Gupta 0006, Aminul Islam 0002 |
Design of CNFET based power- and variability-aware nonvolatile RRAM cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 86, pp. 7-14, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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23 | Maryam Toulabinejad, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh |
Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 90, pp. 267-277, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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23 | Dawen Xu 0002, Li Li, Ying Wang 0001, Cheng Liu 0008, Huawei Li 0001 |
Exploring emerging CNFET for efficient last level cache design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019, pp. 426-431, 2019, ACM, 978-1-4503-6007-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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23 | Li Jiang 0002, Tianjian Li, Naifeng Jing, Nam Sung Kim, Minyi Guo, Xiaoyao Liang |
CNFET-Based High Throughput SIMD Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7), pp. 1331-1344, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Chetan Vudadha, Sai Phaneendra Parlapalli, M. B. Srinivas |
Energy efficient design of CNFET-based multi-digit ternary adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 75, pp. 75-86, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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23 | Sepehr Tabrizchi, Fazel Sharifi, Abdel-Hameed A. Badawy |
Energy Efficient Tri-State CNFET Ternary Logic Gates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1806.07570, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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23 | A. Nagalakshmi, Ch. Sirisha, D. N. Madhusudana Rao |
Hybrid CMOS-CNFET based NP dynamic Carry Look Ahead Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1805.04074, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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23 | Srinithya Nagiri, Sananya Majumder, Riya, Aminul Islam |
Design of low power RRAM cell using CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAIT ![In: 2018 4th International Conference on Recent Advances in Information Technology (RAIT), Dhanbad, India, March 15-17, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-3038-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Lan Wei |
Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET Circuits and to Improve by Using Approximate Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018, pp. 27-32, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Lan Wei |
Using approximate circuits to counter process imperfections in CNFET based circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4260-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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23 | Zhengyang He, Kai Ren 0003, Jiayan Chen, Xinyi Dai, Zhao Pan 0001, Yuejun Zhang |
Design of Delayed Ternary PUF Circuit Based on CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCC ![In: 24th Asia-Pacific Conference on Communications, APCC 2018, Ningbo, China, November 12-14, 2018, pp. 503-507, 2018, IEEE, 978-1-5386-6928-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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23 | Mokhtar Mohammadi Ghanatghestani, Behnam Ghavami, Honeya Salehpour |
A CNFET full adder cell design for high-speed arithmetic units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Turkish J. Electr. Eng. Comput. Sci. ![In: Turkish J. Electr. Eng. Comput. Sci. 25, pp. 2399-2409, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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23 | Yavar Safaei Mehrabani, Mohammad Hossein Shafiabadi |
A novel high-performance and reliable multi-threshold CNFET full adder cell design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 7(1), pp. 15-25, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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23 | Mohan Krishna Gopi Krishna, Arman Roohi, Ramtin Zand, Ronald F. DeMara |
Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 11(3), pp. 274-279, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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23 | Fazel Sharifi, Atiyeh Panahi, Mohammad Hossein Moaiyeri, Keivan Navi |
High Performance CNFET-based Ternary Full Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1701.00307, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
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23 | Omid Khorgami, Alireza Saberkari, Javad Bagheri, Seyed Mohsen Hosseini-Golgoo, Eduard Alarcón-Cot |
Extracting a closed-form I-V equation and noise analysis for CNFET in analog/RF applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NEWCAS ![In: 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, June 25-28, 2017, pp. 229-232, 2017, IEEE, 978-1-5090-4991-2. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Zizhao Liu, Tao Pan, Song Jia, Uan Wang |
Design of a novel ternary SRAM sense amplifier using CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 207-210, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Yaopeng Kang, Pengjun Wang, Yuejun Zhang, Gang Li |
Design of ternary pulsed reversible counter based on CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, pp. 375-378, 2017, IEEE, 978-1-5090-6625-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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23 | Sushma Srivastava, Surendra S. Rathod |
Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 136-143, 2017, Springer, 978-981-10-7469-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 24(11), pp. 3268-3281, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Atiyeh Panahi, Fazel Sharifi, Mohammad Hossein Moaiyeri, Keivan Navi |
CNFET-based approximate ternary adders for energy-efficient image processing applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 47, pp. 454-465, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Tianjian Li, Feng Xie, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang 0002 |
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(7), pp. 1192-1205, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Kaship Sheikh, Shu-Jen Han, Lan Wei |
CNFET With Process Imperfection: Impact on Circuit-Level Yield and Device Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12), pp. 2209-2221, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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23 | Tianjian Li, Li Jiang 0002, Naifeng Jing, Nam Sung Kim, Xiaoyao Liang |
CNFET-based high throughput register file architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016, pp. 662-669, 2016, IEEE Computer Society, 978-1-5090-5142-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Chetan Vudadha, P. Sai Phaneendra, M. B. Srinivas |
An Efficient Design Methodology for CNFET Based Ternary Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iNIS ![In: IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2016, Gwalior, India, December 19-21, 2016, pp. 278-283, 2016, IEEE, 978-1-5090-6170-9. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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23 | YoungBae Kim, Qiang Tong, Ken Choi, Yunsik Lee |
Novel 8-T CNFET SRAM cell design for the future ultra-low power microelectronics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2016, Jeju, South Korea, October 23-26, 2016, pp. 243-244, 2016, IEEE, 978-1-5090-3219-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
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23 | Tianjian Li, Li Jiang 0002, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty |
Defect tolerance for CNFET-based SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016, pp. 1-9, 2016, IEEE, 978-1-4673-8773-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Reza Faghih Mirzaee, Mohammad Eshghi |
A novel low-energy CNFET-based full adder cell using pass-transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 5(4), pp. 193-201, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 34(3), pp. 739-759, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 34(3), pp. 761, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Mohammad Eshghi |
High-Speed, High-Frequency and Low-PDP, CNFET Full Adder Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 24(9), pp. 1550130:1-1550130:24, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Carmen G. Almudéver, Antonio Rubio 0001 |
Variability and reliability analysis of CNFET technology: Impact of manufacturing imperfections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 55(2), pp. 358-366, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang, Li Jiang 0002 |
On microarchitectural modeling for CNFET-based circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 28th IEEE International System-on-Chip Conference, SOCC 2015, Beijing, China, September 8-11, 2015, pp. 356-361, 2015, IEEE, 978-1-4673-9094-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Rishika Sethi, Gaurav Soni |
Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SocProS (1) ![In: Proceedings of Fifth International Conference on Soft Computing for Problem Solving - SocProS 2015, Volume 1, Saharanpur, Uttar Pradesh, India, December 18-20, 2015., pp. 439-451, 2015, Springer, 978-981-10-0447-6. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Feng Xie, Xiaoyao Liang, Qiang Xu 0001, Krishnendu Chakrabarty, Naifeng Jing, Li Jiang 0002 |
Jump test for metallic CNTs in CNFET-based SRAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, pp. 16:1-16:6, 2015, ACM, 978-1-4503-3520-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Mojtaba Maleknejad, Reza Faghih Mirzaee, Keivan Navi, Akbar Dargahi |
A Systematic Approach to Design Boolean Functions using CNFETs and an Array of CNFET capacitors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 23(3), 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Jyoti Sharma, Mohammad Samar Ansari, Jankiballabh Sharma |
Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014, pp. 206-207, 2014, IEEE Computer Society, 978-1-4799-6965-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Shailendra Kumar Tripathi, Mohammad Samar Ansari |
Tunable Active Biquad Filter in ±0.9V 32 Nm CNFET. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: 2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014, pp. 63-67, 2014, IEEE Computer Society, 978-1-4799-6965-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Da Cheng, Fangzhou Wang, Feng Gao, Sandeep K. Gupta 0001 |
Optimal Redundancy Designs for CNFET-Based Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 23rd IEEE Asian Test Symposium, ATS 2014, Hangzhou, China, November 16-19, 2014, pp. 25-32, 2014, IEEE Computer Society, 978-1-4799-6030-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Muhammad Ali 0006, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske |
Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014, Marseille, France, December 7-10, 2014, pp. 774-777, 2014, IEEE, 978-1-4799-4242-8. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Behnam Ghavami, Mohsen Raji, Hossein Pedram, Massoud Pedram |
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 21(5), pp. 887-900, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh |
A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. High Perform. Syst. Archit. ![In: Int. J. High Perform. Syst. Archit. 4(4), pp. 196-203, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Saravana Maruthamuthu |
Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 44(1), pp. 15-19, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Isha Garg, Prakhar Sharma |
Estimation of SNM in latches and subsequent formation of a 10T CNFET bitcell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WISES ![In: Proceedings of the 11th Workshop on Intelligent Solutions in Embedded Systems, WISES 2013, Pilsen, Czech Republic, September 10-11, 2013, pp. 1-5, 2013, IEEE, 978-3-00-042899-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
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