Search results for "Cache-Coherency"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
137	Balachander Krishnamurthy, Craig E. Wills	Proxy Cache Coherency and Replacement - Towards a More Complete Picture.	ICDCS	1999	DBLP DOI BibTeX RDF
97	Sandhya Narayan, Julee Pandya, Prasant Mohapatra, Dipak Ghosal	Analysis of Windowing and Peering Schemes for Cache Coherency in Mobile Devices.	NETWORKING	2005	DBLP DOI BibTeX RDF
89	Yang Zeng, Santosh G. Abraham	Partitioning regular grid applications with irregular boundaries for cache-coherent multiprocessors.	IPPS	1995	DBLP DOI BibTeX RDF	partitioning regular grid applications, irregular boundaries, cache-coherent multiprocessors, regular grid, domain decomposition techniques, message passing multiprocessors, false coherency traffic, cache line, coalescing algorithm, domain decomposition algorithm, Indian Ocean circulation application, KSR1 multiprocessor, coherency traffic, message passing, multiprocessing systems, interprocessor communication
85	John A. Reisner, Tom S. Wailes	A Cache Coherency Protocol for Optically Connected Parallel Computer Systems.	HPCA	1996	DBLP DOI BibTeX RDF	parallel processing, Cache coherency, computer simulation, wavelength division multiplexing, time division multiplexing, optical interconnection networks
83	Jih-Fu Tu	Cache Management for Discrete Processor Architectures.	ISPA	2005	DBLP DOI BibTeX RDF	Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency
83	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
71	Chun-Mok Chung, Jihong Kim 0001, Dohyung Kim	Reducing snoop-energy in shared bus-based mpsocs by filtering useless broadcasts.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	broadcast filtering, low-energy cache coherency, MPSoC
70	Avi Mendelson, Freddy Gabbay	The effect of seance communication on multiprocessing systems.	ACM Trans. Comput. Syst.	2001	DBLP DOI BibTeX RDF	multicache systems, seance communication, performance analysis, cache coherency protocols
67	Kenin Coloma, Alok N. Choudhary, Wei-keng Liao, Lee Ward, Eric Russell, Neil Pundit	Scalable High-level Caching for Parallel I/O.	IPDPS	2004	DBLP DOI BibTeX RDF
63	Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva	Cache coherency communication cost in a NoC-based MPSoC platform.	SBCCI	2007	DBLP DOI BibTeX RDF	cache coherence, MPSoC, NoC, directory
63	Michel Dubois 0001, Faye A. Briggs	Effects of cache coherency in multiprocessors.	ISCA	1982	DBLP BibTeX RDF
59	KyungOh Ohn, Haengrae Cho	Maintaining Cache Coherency for B+ Tree Indexes in a Shared Disks Cluster.	VECPAR	2004	DBLP DOI BibTeX RDF	Cluster and Grid Computing, Data Processing, Parallel and Distributed Computing
58	Hai Wan, Lei Li 0022	Design and Implementation of Semantic Caching Coherency Control Scheme Toward Distributed Environment.	APPT	2005	DBLP DOI BibTeX RDF
56	John P. Sustersic, Ali R. Hurson	A Quality of Service (QoS) Implementation of Internet Cache Coherence.	AINA (1)	2004	DBLP DOI BibTeX RDF
56	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
55	Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, Michael Parkin, Bill Radke, Sanjay Vishin	Exploiting Parallelism in Cache Coherency Protocol Engines.	Euro-Par	1995	DBLP DOI BibTeX RDF
55	Diana Hecht, Krishna M. Kavi, Rhonda Kay Gaede, Constantine Katsinis	Fault-Tolerance Using Cache-Coherent Distributed Shared Memory Systems.	ISPAN	1999	DBLP DOI BibTeX RDF	Backward recovery, Directory-Based Protocols, Checkpointing, Distributed Shared Memory, Conversations, Cache-Coherency, Recovery Blocks
52	Song Gao, Wee Siong Ng, Weining Qian, Aoying Zhou	CC-Buddy: an adaptive framework for maintaining cache coherency using peers.	WWW (Alternate Track Papers & Posters)	2004	DBLP DOI BibTeX RDF	peer-to-peer, cache coherency, dynamic data
52	Amy P. Felty, Frank A. Stomp	Cache Coherency in SCI: Specification and a Sketch of Correctness.	Formal Aspects Comput.	1999	DBLP DOI BibTeX RDF	SCI (Scalable Coherent Interface), Distributed systems, Formal verification, Temporal logic, Cache coherency, IEEE standard
52	Santosh G. Abraham, David E. Hudak	Compile-Time Partitioning of Iterative Parallel Loops to Reduce Cache Coherency Traffic.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	adaptive data partitioning, iterative parallel loops, cache coherency traffic, ADP, communication-reducing back end, machine-specific partitioner, multiprocessor model, programexecution factors, vector notation, global data set, arrayaccesses, underlying system architecture, cache line sizes, hexagonal partitions, parallel programming, parallel machines, program compilers, parallelizing compilers, buffer storage, interprocessor communication, interprocessor communication, communication patterns, parallelprograms
49	Jun Cai, Kian-Lee Tan	Energy-efficient selective cache invalidation.	Wirel. Networks	1999	DBLP DOI BibTeX RDF
47	Cosmin E. Oancea, Alan Mycroft	A Lightweight Model for Software Thread-Level Speculation (TLS).	PACT	2007	DBLP DOI BibTeX RDF
46	Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer	Porting existing cache-oblivious linear algebra HPC modules to larrabee architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	accelerator space-filling curve, openmp, matrix multiplication, cache-oblivious, lu decomposition, manycore
44	Jan Willem van den Brand, Marco Bekooij	Streaming consistency: a model for efficient MPSoC design.	DSD	2007	DBLP DOI BibTeX RDF
44	Freddy Gabbay, Avi Mendelson	Smart: An Advanced Shared-Memory Simulator - Towards a System-Level Simulation Environmen.	MASCOTS	1997	DBLP DOI BibTeX RDF	Multi-cache simulator, Performance analysis, Cache coherency protocols
44	Shigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito	SSM-MP: more scalability in shared-memory multi-processor.	ICCD	1995	DBLP DOI BibTeX RDF	SSM-MP, shared-memory multi-processor, cache refill latency, bus bottle neck problem, MTag, scalability, shared memory systems, cache coherency, memory architecture, multi-processor system
41	Anne Bracy, Kshitij Doshi, Quinn Jacobson	Disintermediated Active Communication.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
41	Karen A. Tomko, Santosh G. Abraham	Data and program restructuring of irregular applications for cache-coherent multiprocessor.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
41	Frédéric Pétrot, Alain Greiner, Pascal Gomez	On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures.	DSD	2006	DBLP DOI BibTeX RDF
41	Haengrae Cho	Performance of Cache Coherency Schemes in a Shared Disks Transaction Environment .	FTDCS	1997	DBLP DOI BibTeX RDF
40	Krishna M. Kavi, Wentong Li, Ali R. Hurson	A Non-blocking Multithreaded Architecture with Support for Speculative Threads.	ICA3PP	2008	DBLP DOI BibTeX RDF	Cache Coherency, Thread Level Speculation, Multithreaded Architectures, Decoupled Architecture
40	Sangho Lee, KyungOh Ohn, Haengrae Cho	Feasibility and Performance Study of a Shared Disks Cluster for Real-Time Processing.	AIS	2004	DBLP DOI BibTeX RDF	Performance evaluation, cluster computing, transaction processing, cache coherency, real-time processing
40	Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde	Reflective-memory multiprocessor.	HICSS (1)	1995	DBLP DOI BibTeX RDF	reflective-memory multiprocessor, hardware-supported data replication, multiple computers, memory semantics, reflective memory implementation, Encore Infinity, spinlocks, cache coherency problems, massive replication, recovery procedure, crashed nodes, reliability, fault tolerant computing, shared memory systems, distributed memory systems, system recovery, cache storage, cached architectures, distributed shared memory multiprocessor
37	Vijay Nagarajan, Rajiv Gupta 0001	Architectural support for shadow memory in multiprocessors.	VEE	2009	DBLP DOI BibTeX RDF	coupled coherence, shadow memory
34	Martti Forsell	Reducing the associativity and size of step caches in CRCW operation.	IPDPS	2006	DBLP DOI BibTeX RDF
34	Arun S. Nair, Aboli Vijayan Pai, Biju K. Raveendran, Geeta Patil	MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache.	DS-RT	2021	DBLP DOI BibTeX RDF
33	Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel	Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.	MICRO	2009	DBLP DOI BibTeX RDF	Nehalem, Shanghai, benchmark, multi-core, coherency
33	Rajdeep Bhowmik, Chaitali Gupta, Madhusudhan Govindaraju, Aneesh Aggarwal	Optimizing XML processing for grid applications using an emulation framework.	IPDPS	2008	DBLP DOI BibTeX RDF
30	Mikhail Mikhailov, Craig E. Wills	Evaluating a new approach to strong web cache consistency with snapshots of collected content.	WWW	2003	DBLP DOI BibTeX RDF	change characteristics, collected content, object relationships, server invalidation, web caching, cache consistency, object composition
30	Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Functional Self-Testing for Bus-Based Symmetric Multiprocessors.	DATE	2008	DBLP DOI BibTeX RDF
26	Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-Hsin S. Lee	Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors.	ASPLOS	2008	DBLP DOI BibTeX RDF	MESI protocol, internal and external snoops, self-modifying code, chip multiprocessors
26	Anant Agarwal, David A. Kranz, Rajeev Barua, Venkat Natarajan	Optimal Tiling for Minimizing Communication in Distributed Shared-Memory Multiprocessors.	Compiler Optimizations for Scalable Parallel Systems Languages	2001	DBLP DOI BibTeX RDF
26	Hiroaki Fujii, Yoshiko Yasuda, Hideya Akashi, Yasuhiro Inagami, Makoto Koga, Osamu Ishihara, Masamori Kashiyama, Hideo Wada, Tsutomu Sumimoto	Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System.	IPPS	1997	DBLP DOI BibTeX RDF
26	Koen Langendoen, Henk L. Muller, Louis O. Hertzberger	Evaluation of Futurebus Hierarchical Caching.	PARLE (1)	1991	DBLP DOI BibTeX RDF
26	Abishek Ramdas, Michael Giardino, Runbin Shi, Adam Turowski, David A. Cock, Gustavo Alonso, Timothy Roscoe	ECI: a Customizable Cache Coherency Stack for Hybrid FPGA-CPU Architectures.	CoRR	2022	DBLP DOI BibTeX RDF
26	Arthur Vianès, Frédéric Pétrot, Frédéric Rousseau 0001	A Case for Second-Level Software Cache Coherency on Many-Core Accelerators.	RSP	2022	DBLP DOI BibTeX RDF
26	Seungwon Min, Sitao Huang, Mohamed El-Hadedy 0001, Jinjun Xiong, Deming Chen, Wen-Mei Hwu	Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device.	CoRR	2019	DBLP BibTeX RDF
26	Seungwon Min, Sitao Huang, Mohamed El-Hadedy 0001, Jinjun Xiong, Deming Chen, Wen-Mei Hwu	Analysis and Optimization of I/O Cache Coherency Strategies for SoC-FPGA Device.	FPL	2019	DBLP DOI BibTeX RDF
26	Jussara Marandola, Stéphane Louise, Loïc Cudennec	Pattern Based Cache Coherency Architecture for Embedded Manycores.	ICCS	2016	DBLP DOI BibTeX RDF
26	Paolo Grani, Robert Hendry, Sandro Bartolini, Keren Bergman	Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects.	ICNC	2015	DBLP DOI BibTeX RDF
26	Julio Pérez Acle, Riccardo Cantoro, Ernesto Sánchez 0001, Matteo Sonza Reorda	On the functional test of the cache coherency logic in multi-core systems.	LASCAS	2015	DBLP DOI BibTeX RDF
26	José L. Abellán, Alberto Ros 0001, Juan Fernández Peinador, Manuel E. Acacio	ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.	ICSAMOS	2013	DBLP DOI BibTeX RDF
26	Omar Hammami, Xinyu Li	NOC based MPSOC directory based cache coherency with OCP-IP protocol.	IDT	2013	DBLP DOI BibTeX RDF
26	José L. Abellán, Alberto Ros 0001, Juan Fernández 0001, Manuel E. Acacio	Efficient Dir0B Cache Coherency for Many-Core CMPs.	ICCS	2013	DBLP DOI BibTeX RDF
26	John Shield, Jean-Philippe Diguet, Guy Gogniat	Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance.	ACM Trans. Reconfigurable Technol. Syst.	2012	DBLP DOI BibTeX RDF
26	Freek Verbeek, Julien Schmaltz	Towards the formal verification of cache coherency at the architectural level.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
26	John Shield, Jean-Philippe Diguet, Guy Gogniat	Asymmetric cache coherency: Improving multicore performance for non-uniform workloads.	ReCoSoC	2011	DBLP DOI BibTeX RDF
26	Hajer Chtioui	Gestion de la cohérence des données dans les systèmes multiprocesseurs sur puce. (Managing cache coherency of shared data in shared memory multiprocessor systems-on-chip).		2011	RDF
26	Daniel Molka, Daniel Hackenberg, Robert Schöne, Matthias S. Müller	Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System.	PACT	2009	DBLP DOI BibTeX RDF
26	Hajer Chtioui, Rabie Ben Atitallah, Smaïl Niar, Jean-Luc Dekeyser, Mohamed Abid	A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC.	DSD	2009	DBLP DOI BibTeX RDF
26	Alberto Ros 0001, Manuel E. Acacio, José M. García 0001	DiCo-CMP: Efficient cache coherency in tiled CMP architectures.	IPDPS	2008	DBLP DOI BibTeX RDF
26	Hui Wang, Sandeep Baldawa, Rama Sangireddy	Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
26	Robert Kunz, Mark Horowitz	The case for simple, visible cache coherency.	MSPC	2008	DBLP DOI BibTeX RDF	SpecOMP2001, shared-memory multiprocessor, FLASH, coherence protocol, cc-NUMA, software optimization, performance bottlenecks
26	Austin Hung, William D. Bishop, Andrew A. Kennings	Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips.	ERSA	2004	DBLP BibTeX RDF
26	José Aguilar 0001, Ernst L. Leiss	A General Adaptive Cache Coherency-Replacement Scheme for Distributed Systems.	IICS	2001	DBLP DOI BibTeX RDF
26	José Aguilar 0001, Ernst L. Leiss	A Web Proxy Cache Coherency and Replacement Approach.	Web Intelligence	2001	DBLP DOI BibTeX RDF
26	Adam Belloum, Bob Hertzberger	Maintaining Web cache coherency.	Inf. Res.	2000	DBLP BibTeX RDF
26	Freddy Gabbay, Avi Mendelson	The "Smart" simulation environment - A tool-set to develop new cache coherency protocols.	J. Syst. Archit.	1999	DBLP DOI BibTeX RDF
26	Jianliang Xu, Xueyan Tang, Dik Lun Lee, Qinglong Hu	Cache Coherency in Location-Dependent Information Services for Mobile Environment.	MDA	1999	DBLP DOI BibTeX RDF
26	Balachander Krishnamurthy, Craig E. Wills	Piggyback Server Invalidation for Proxy Cache Coherency.	Comput. Networks	1998	DBLP DOI BibTeX RDF
26	Haengrae Cho, Jang-Suk Park	Maintaining cache coherency in a multisystem data sharing environment.	J. Syst. Archit.	1998	DBLP DOI BibTeX RDF
26	Hakim Kahlouche, César Viho, Massimo Zendri	An Industrial Experiment in Automatic Generation of Executable Test Suites for a Cache Coherency Protocol.	IWTCS	1998	DBLP BibTeX RDF
26	Fernando de Ferreira Rezende, Victoria Hall	A Cache Coherency Strategy for a Client/Server KBMS.	Datenbank Rundbr.	1997	DBLP BibTeX RDF
26	Jun Cai, Kian-Lee Tan, Beng Chin Ooi	On Incremental Cache Coherency Schemes in Mobile Computing Environments.	ICDE	1997	DBLP DOI BibTeX RDF
26	Andreas Listl, Giannis Bozas	Performance Gains Using Subpages for Cache Coherency Control.	DEXA Workshops	1997	DBLP DOI BibTeX RDF
26	Craig Anderson 0001, Anna R. Karlin	Two Adaptive Hybrid Cache Coherency Protocols.	HPCA	1996	DBLP DOI BibTeX RDF
26	Boris Klots	Cache Coherency in Oracle Parallel Server.	VLDB	1996	DBLP BibTeX RDF
26	John C. Chu, Kwan AuYeung, Patrick W. Dowd	Interaction Of Cache Coherency And Media Access Protocols In The Optically Interconnected Distributed Memory Environment.	Annual Simulation Symposium	1993	DBLP DOI BibTeX RDF
26	Alan L. Cox, Robert J. Fowler	Adaptive Cache Coherency for Detecting Migratory Shared Data.	ISCA	1993	DBLP DOI BibTeX RDF
26	Jen-Tien Yen, Behrooz A. Shirazi, Krishna M. Kavi	A New Cache Coherency and Address Translation Consistency Protocol.	ICPP (1)	1992	DBLP BibTeX RDF
26	Wisam Michael	Directory-based cache coherency protocol for a ring-connected multiprocessor-array.	ISCA	1992	DBLP DOI BibTeX RDF
26	Jack E. Veenstra, Robert J. Fowler	A Performance Evaluation of Optimal Hybrid Cache Coherency Protocols.	ASPLOS	1992	DBLP DOI BibTeX RDF
26	Norman S. Matloff	An argument against scalable cache coherency.	SIGARCH Comput. Archit. News	1991	DBLP DOI BibTeX RDF
26	Susan J. Eggers	Simplicity Versus Accuracy in a Model of Cache Coherency Overhead.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF
26	Gautam Dewan, Prasenjit Biswas	A snooping cache coherency protocol for hierarchically organized multiprocessors.	Microprocessing and Microprogramming	1991	DBLP DOI BibTeX RDF
26	Kanad Ghose, Sreenivas Simhadri	A Cache Coherency Mechanism with Limited Combining Capabilities for MIN-Based Multiprocessors.	ICPP (1)	1991	DBLP BibTeX RDF
26	Bett Koch, Tracy Schunke, Alan Dearle, Francis Vaughan, Chris D. Marlin, Ruth Fazakerley, Chris J. Barter	Cache Coherency and Storage Management in a Persistent Object System.	POS	1990	DBLP BibTeX RDF
26	Susan J. Eggers, Randy H. Katz	Evaluating the Performance of Four Snooping Cache Coherency Protocols.	ISCA	1989	DBLP DOI BibTeX RDF
26	Michel Dubois 0001, Faye A. Briggs	Effects of Cache Coherency in Multiprocessors.	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF
26	Li Zhang 0034, Chris R. Jesshope	On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
26	Victor Melamed, Harry Stuimer, David Wilkins, Lawrence Chang, Kevin Normoyle, Sutikshan Bhutani	Innovative Verification Techniques Used in the Implementation of a Third-Generation 1.1GHz 64b Microprocessor.	FORTE	2002	DBLP DOI BibTeX RDF
26	Paul J. Roy, David B. Noveck, W. J. Bryant	State Management in a Distributed UNIX System.	HICSS (1)	1996	DBLP DOI BibTeX RDF
26	Ásgeir Th. Eiríksson, Kenneth L. McMillan	Using Formal Verification/Analysis Methods on the Critical Path in System Design: A Case Study.	CAV	1995	DBLP DOI BibTeX RDF
26	Paul E. West, Yuval Peress, Gary S. Tyson, Sally A. McKee	Core monitors: monitoring performance in multicore processors.	Conf. Computing Frontiers	2009	DBLP DOI BibTeX RDF	scheduling, debugging, profiling, multicore, cache coherency, performance monitoring, realtime
26	Stéphane Zuckerman, Marc Pérache, William Jalby	Fine Tuning Matrix Multiplications on Multicore.	HiPC	2008	DBLP DOI BibTeX RDF	multicore, cache coherency, BLAS
26	John R. Feehrer, Paul Rotker, Milton Shih, Paul Gingras, Peter Yakutis, Stephen Phillips, John Heath, Sebastian Turullols	Coherency Hub Design for Multi-Node Victoria Falls Server Systems.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	multi-threaded processor cores, multi-node CMT systems, serial interconnects, packet switching, cache coherency
26	Razvan Cheveresan, Matthew Ramsay, Chris Feucht, Ilya Sharapov	Characteristics of workloads used in high performance and technical computing.	ICS	2007	DBLP DOI BibTeX RDF	instruction decomposition, cache coherency, workload characterization, HPC, data locality, software prefetch
26	KyungOh Ohn, Haengrae Cho	Dynamic Affinity Cluster Allocation in a Shared Disks Cluster.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	transaction routing, affinity clustering, load balancing, cluster computing, transaction processing, cache coherency, shared disks
26	Gerrit Saylor, Badriddine Khessib	Large scale Itanium® 2 processor OLTP workload characterization and optimization.	DaMoN	2006	DBLP DOI BibTeX RDF	cache coherency, data partitioning, performance characterization, profile guided optimization, OLTP, software optimization, Itanium, ccNUMA
26	Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, André Seznec	Tarantula: A Vector Extension to the Alpha Architecture.	ISCA	2002	DBLP DOI BibTeX RDF	Power, Microprocessor, Bandwidth, High Performance, Cache Coherency, Virtual Memory, Instruction Set Architecture, Vector Processor