Search results for "Codesign"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
112	Geoffrey A. Frank, Bernard Clark, W. Bernard Schaming, William Kline	Hardware/Software Codesign from the RASSP Perspective.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
83	Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo	PeaCE: A hardware-software codesign environment for multimedia embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	hardware-software cosimulation, embedded systems, design-space exploration, model-based design, Hardware-software codesign
80	Matthew F. Parkinson, Sri Parameswaran	Profiling in the ASP codesign environment.	ISSS	1995	DBLP DOI BibTeX RDF	Automated Synthesis and Partitioning system, Hardware/Software Codesign project, codesign environment, hardware/software codesign methodology, high-level profiling tools, virtual machines, software tools, C, computer architecture, profiling, systems analysis, circuit CAD, workstation, ASP, C code, dedicated hardware, execution profiling
78	Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni	Approach to the Synthesis of HW and SW in Codesign.	CODES	1997	DBLP DOI BibTeX RDF	formal methods, synthesis, codesign
78	Markus Voss, Oliver Hammerschmidt	Implications of Codesign as a Natural Constituent of a Systems Engineering Discipline for Computer Based Systems.	CODES	1996	DBLP DOI BibTeX RDF	Engineering of Computer Based Systems, Hardware/Software- Codesign, Design Theory
67	Markus Voss, Tarek Ben Ismail, Ahmed Amine Jerraya, Karl-Heinz Kapp	Towards a theory for hardware/software codesign.	CODES	1994	DBLP DOI BibTeX RDF	Design Process, System-Level Design, Hardware/Software Codesign, Design Theory
66	Wolfram Hardt, Wolfgang Rosenstiel	Speed-up estimation for HW/SW-systems.	CODES	1996	DBLP DOI BibTeX RDF	HW/SW-systems, ciphering algorithm, codesign tool COD, speed-up estimation, logic design, systems analysis, hardware/software codesign, system performance, partitioning methods
63	Jean Paul Calvez, D. Isidoro	A CoDesign experience with the MCSE methodology.	CODES	1994	DBLP DOI BibTeX RDF
62	Min He, Ming-Che Tsai, Xiaolong Wu, Fei Wang 0005, Ramzi Nasr	Hardware/Software Codesign - Pedagogy for the Industry.	ITNG	2008	DBLP DOI BibTeX RDF	computer engineering curriculum, education, system-level design, Hardware/Software Codesign
62	Steven J. Cunning, T. C. Ewing, J. T. Olson, Jerzy W. Rozenblit, Stephan Schulz 0002	Towards an Integrated, Model-Based Codesign Environment.	ECBS	1999	DBLP DOI BibTeX RDF	CAD environment, Simulation, Modeling, Hardware/Software Codesign
62	Laurent Freund, Michel Israël, Frédéric Rousseau 0001, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat	A codesign experiment in acoustic echo cancellation GMDF.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	communications, codesign, HW/SW partitioning
58	Joachim Falk, Christian Haubelt, Jürgen Teich, Christian Zebelein	SysteMoC: A Data-Flow Programming Language for Codesign.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
58	Jarmo Takala, Pekka Jääskeläinen, Teemu Pitkänen	Codesign Case Study on Transport-Triggered Architectures.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
58	Grant Martin, Frank Schirrmeister, Yosinori Watanabe	Hardware/Software Codesign Across Many Cadence Technologies.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
58	Wanli Chang 0001, Licong Zhang, Debayan Roy, Samarjit Chakraborty	Control/Architecture Codesign for Cyber-Physical Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
58	Soonhoi Ha, Jürgen Teich, Christian Haubelt, Michael Glaß, Tulika Mitra, Rainer Dömer, Petru Eles, Aviral Shrivastava, Andreas Gerstlauer, Shuvra S. Bhattacharyya	Introduction to Hardware/Software Codesign.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
58	Juanjo Noguera, Rosa M. Badia	HW/SW codesign techniques for dynamically reconfigurable architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
57	M. J. van der Westhuizen, R. G. Harley, D. C. Levy, D. R. Woodward	Using EDIF for software generation.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	EDIF, parallel microprocessors, codesign methods, hardware development tools, real-time parallel C code, FPGA, parallel programming, simulated annealing, simulated annealing, software tools, software tool, logic CAD, circuit CAD, C language, scheduling theory, software generation, development systems
56	Frank Vahid, Tony Givargis	Highly-cited ideas in system codesign and synthesis.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	hardware/software codesign, citations, system synthesis
56	D. C. R. Jensen, Jan Madsen, Steen Pedersen	The importance of interfaces: a HW/SW codesign case study.	CODES	1997	DBLP DOI BibTeX RDF	hardware software interface, case study, image sequences, optical flow, image analysis, hardware software codesign, prototype system, optimal solutions, functional modules, system level
56	Youngsoo Shin, Kiyoung Choi	Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign.	CODES	1997	DBLP DOI BibTeX RDF	schedulability, real-time, deadline, Codesign, rate-monotonic scheduling
56	Guy Gogniat, Michel Auguin, Cécile Belleudy	A generic multi-unit architecture for codesign methodologies.	CODES	1997	DBLP DOI BibTeX RDF	codesign, communication synthesis, heterogeneous architecture, target architecture
56	Michael Sheliga, Nelson L. Passos, Edwin Hsing-Mean Sha	Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications.	CODES	1996	DBLP DOI BibTeX RDF	Multi-Dimensional Systems, High Level Synthesis, Hardware/Software Codesign
53	Jeffry T. Russell	Program slicing for codesign.	CODES	2002	DBLP DOI BibTeX RDF
53	Brian Grattan, Greg Stitt, Frank Vahid	Codesign-extended applications.	CODES	2002	DBLP DOI BibTeX RDF	hardware/software cospecification, system-on-a-chip, hardware/software partitioning, platform-based design, configurable logic
53	Peter Green 0001, Paul Rushton, Ronnie Beggs	An example of applying the codesign method MOOSE.	CODES	1994	DBLP DOI BibTeX RDF
51	Lesley Shannon, Paul Chow	Using reconfigurability to achieve real-time profiling for hardware/software codesign.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, profiling, performance measurement, embedded processor, hardware/software codesign, soft processor
51	Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya	Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	hardware/software codesign, Performance estimation, multiprocessor architectures, architecture exploration, system-level simulation
51	Guy Gogniat, Michel Auguin, Luc Bianco, Alain Pegatoquet	A codesign back-end approach for embedded system design.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	HW/SW integration, template architecture, codesign, communications synthesis
51	Vincenza Carchiolo, Michele Malgeri, Giuseppe Mangioni	Hardware/software synthesis of formal specifications in codesign of embedded systems.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	hardware and software synthesis, embedded system, codesign
51	Randall S. Janka, Linda M. Wills	Combining Virtual Benchmarking with Rapid System Prototyping for Real-Time Embedded Multiprocessor Signal Processing System Codesign.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	signal processor, specification and design methodology, middleware, multiprocessor, embedded, rapid prototyping, codesign
48	Hideaki Yanagisawa, Minoru Uehara, Hideki Mori	Server Side C-DASH: Ubiquitous Hardware/Software Codesign Environment.	MDM	2006	DBLP DOI BibTeX RDF
48	Soonhoi Ha, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo	Hardware-Software Codesign of Multimedia Embedded Systems: the PeaCE.	RTCSA	2006	DBLP DOI BibTeX RDF
48	Nattawut Thepayasuwan, Alex Doboli	Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
48	Sergio A. Cuenca, António S. Câmara, Juan Suardíaz Muro, Ana Toledo Moreo	Domain-Specific Codesign for Automated Visual Inspection Systems.	IbPRIA (1)	2005	DBLP DOI BibTeX RDF
48	Juanjo Noguera, Rosa M. Badia	Run-Time HW/SW Codesign for Discrete Event Systems using Dynamically Reconfigurable Architectures.	ISSS	2000	DBLP DOI BibTeX RDF
48		Hardware-Software Codesign.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
46	Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj, Majid Sarrafzadeh	Communication bottleneck in hardware-software partitioning.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, communication, hardware-software codesign
46	JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas	Frequency interleaving as a codesign scheduling paradigm.	CODES	2000	DBLP DOI BibTeX RDF	clock domains, frequency interleaved scheduling, hardware/software codesign, computer system modeling
46	Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou	Using codesign techniques to support analog functionality.	CODES	1999	DBLP DOI BibTeX RDF	design methodologies, analog, hardware/software codesign
46	Frank Vahid, Linus Tauro	An Object-Oriented Communication Library for Hardware-Software CoDesign.	CODES	1997	DBLP DOI BibTeX RDF	Communication, Object-Oriented, C, VHDL, Libraries, Codesign
46	Tarek Ben Ismail, Mohamed Abid, Ahmed Amine Jerraya	COSMOS: a codesign approach for communicating systems.	CODES	1994	DBLP DOI BibTeX RDF	System Design Model, Hardware/Software Codesign, Communication Synthesis
43	Jacopo Panerati, Donatella Sciuto, Giovanni Beltrame	Optimization Strategies in Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Kees Goossens, Martijn Koedam, Andrew Nelson 0001, Shubhendu Sinha, Sven Goossens, Yonghui Li 0002, Gabriela Breaban, Reinier van Kampenhout, Rasool Tavakoli, Juan Valencia, Hadi Ahmadi Balef, Benny Akesson, Sander Stuijk, Marc Geilen, Dip Goswami, Majid Nabi	NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Peter Marwedel, Heiko Falk, Olaf Neugebauer	Memory-Aware Optimization of Embedded Software for Multiple Objectives.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Soonhoi Ha, Hanwoong Jung	HOPES: Programming Platform Approach for Embedded Systems Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Ingo Sander, Axel Jantsch, Seyed-Hosein Attarzadeh-Niaki	ForSyDe: System Design Using a Functional Language and Models of Computation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Shuoxin Lin, Yanzhou Liu 0001, Kyunghun Lee, Lin Li 0029, William Plishker, Shuvra S. Bhattacharyya	The DSPCAD Framework for Modeling and Synthesis of Signal Processing Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Michael Glaß, Jürgen Teich, Martin Lukasiewycz, Felix Reimann	Hybrid Optimization Techniques for System-Level Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Santiago Pagani, Muhammad Shafique 0001, Jörg Henkel	Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power Constraints.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Fernando Herrera, Julio L. Medina, Eugenio Villar	Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design Approach.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Todor P. Stefanov, Andy D. Pimentel, Hristo Nikolov	DAEDALUS: System-Level Design Methodology for Streaming Multiprocessor Embedded Systems on Chips.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Tulika Mitra	Application-Specific Processors.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng	MAPS: A Software Development Environment for Embedded Multicore Applications.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Marilyn Wolf	Embedded Computer Vision.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Chun Jason Xue	Emerging and Nonvolatile Memory.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Gunar Schirner, Andreas Gerstlauer, Rainer Dömer	SCE: System-on-Chip Environment.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Young-Hwan Park, Amin Khajeh, Jun Yong Shin, Fadi J. Kurdahi, Ahmed M. Eltawil, Nikil D. Dutt	Microarchitecture-Level SoC Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Graziano Pravadelli, Davide Quaglia, Sara Vinco, Franco Fummi	Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Santanu Sarma, Nikil D. Dutt	Architecture and Cross-Layer Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Mihai Teodor Lazarescu, Luciano Lavagno	Wireless Sensor Networks.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Mansureh Shahraki Moghaddam, Jae-Min Cho, Kiyoung Choi	Reconfigurable Architectures.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Wolfgang Ecker, Johannes Schreiner	Metamodeling and Code Generation in the Hardware/Software Interface Domain.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Oliver Bringmann 0001, Christoph Gerum, Sebastian Ottlik	Timing Models for Fast Embedded Software Performance Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Klaus Schneider 0001, Jens Brandt 0001	Quartz: A Synchronous Language for Model-Based Design of Reactive Embedded Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Oliver Bringmann 0001, Sebastian Ottlik, Alexander Viehl	Precise Software Timing Simulation Considering Execution Contexts.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Frédéric Pétrot, Luc Michel, Clément Deschamps	Multiprocessor System-on-Chip Prototyping Using Dynamic Binary Translation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Preeti Ranjan Panda	Memory Architectures.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Andy D. Pimentel, Peter van Stralen	Scenario-Based Design Space Exploration.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Haseeb Bokhari, Sri Parameswaran	Network-on-Chip Design.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Tim Kogel	Synopsys Virtual Prototyping for Software Development and Early Architecture Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Haibo Zeng 0001, Prachi Joshi, Daniel Thiele, Jonas Diemer, Philip Axer, Rolf Ernst, Petru Eles	Networked Real-Time Embedded Systems.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Daniel Mueller-Gritschneder, Andreas Gerstlauer	Host-Compiled Simulation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Rainer Dömer, Guantao Liu, Tim Schmidt	Parallel Simulation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Ali Pahlevan, Maurizio Rossi 0001, Pablo García Del Valle, Davide Brunelli, David Atienza	Joint Computing and Electric Systems Optimization for Green Datacenters.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Aviral Shrivastava, Jian Cai 0001	Hardware-Aware Compilation.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Robin Hofmann, Leonie Ahrendts, Rolf Ernst	CPA: Compositional Performance Analysis.	Handbook of Hardware/Software Codesign	2017	DBLP DOI BibTeX RDF
43	Naren Narasimhan, Vinoo Srinivasan, Madhavi Vootukuru, Jeffrey Walrath, Sriram Govindarajan, Ranga Vemuri	Rapid Prototyping of Reconfigurable Coprocessors.	ASAP	1996	DBLP DOI BibTeX RDF	Prototyping, High-level Synthesis, JPEG, Coprocessors, Hardware-Software Co-design, Software Profiling
42	Christian Kreiner, Christian Steger, Egon Teiniker, Reinhold Weiss	A novel codesign approach based on distributed virtual machines.	CODES	2002	DBLP DOI BibTeX RDF	Linux
42	Matthias Meerwein, C. Baumgartner, W. Glauert	Linking codesign and reuse in embedded systems design.	CODES	2000	DBLP DOI BibTeX RDF
42	Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya	A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor.	CODES	1997	DBLP DOI BibTeX RDF	hardware/software co-operation, a computer architecture using FPGA, bus-based reconfigurable co-processor architecture, high-level synthesis and optimization, C compiler to hardware modules
42	Tommy King-Yin Cheung, Graham R. Hellestrand, Prasert Kanthamanon	A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study.	CODES	1996	DBLP DOI BibTeX RDF	Design Transformations, Functional Languages
42	Flemming Høeg, Niels Mellergaard, Jørgen Staunstrup	The priority queue as an example of hardware/software codesign.	CODES	1994	DBLP DOI BibTeX RDF
42	Jens P. Brage, Jan Madsen	A codesign case study in computer graphics.	CODES	1994	DBLP DOI BibTeX RDF
42	Luciano Lavagno, Massimiliano Chiodo, Paolo Giusto, Attila Jurecska, Harry Hsieh, S. Yee, Alberto L. Sangiovanni-Vincentelli, Kei Suzuki	A case study in computer-aided codesign of embedded controllers.	CODES	1994	DBLP DOI BibTeX RDF
42	Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel	A prototyping environment for hardware/software codesign in the COBRA project.	CODES	1994	DBLP DOI BibTeX RDF
41	Ming-Fang Lai, Hung-Ming Chen	An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign.	ISQED	2008	DBLP DOI BibTeX RDF	Chip-Package Codesign, I/O Placement, Power Integrity
41	Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen	Optimal Allocation of I/O Device Parameters in Hardware and Software Codesign Methodology.	EUC	2007	DBLP DOI BibTeX RDF	I/O interface, Hardware/Software Codesign, Device Driver, Programmable controller
41	Kuan Jen Lin, Shih Hao Huang, Shih Wen Chen	A hardware/software codesign approach for programmable IO devices.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	hardware/software codesign, device driver, programmable controller, software optimization
41	Abdenour Azzedine, Jean-Philippe Diguet, Jean Luc Philippe	Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems.	CODES	2002	DBLP DOI BibTeX RDF	HW / SW Codesign, RT scheduling, system design exploration
41	Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell	Fast processor core selection for WLAN modem using mappability estimation.	CODES	2002	DBLP DOI BibTeX RDF	mappability estimation, processor architecture evaluation, codesign, cost function
41	Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya	Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	Design Space Exploration, SDL, Hardware/Software Codesign, Performance Estimation, Multiprocessor Architectures
41	Jie Gong, Daniel Gajski, Smita Bakshi	Model refinement for hardware-software codesign.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	sofware-hardware codesign, functional model, implementation model, model refinement
41	Vincenzo Catania, N. Fiorito, Michele Malgeri, Marco Russo	A soft computing approach to hardware software codesign.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	soft computing approach, partitioning phase, genetic algorithms, genetic algorithms, fuzzy logic, fuzzy logic, logic CAD, computer aided software engineering, hardware/software codesign
37	Jae Young Bang, Daniel Popescu 0001, George Edwards, Nenad Medvidovic, Naveen N. Kulkarni, Girish M. Rama, Srinivas Padmanabhuni	CoDesign: a highly extensible collaborative software modeling framework.	ICSE (2)	2010	DBLP DOI BibTeX RDF
37	Dong-hyun Lee, Keun Lee, Sooyong Park, Mike Hinchey	A Survival Kit: Adaptive Hardware/Software Codesign Life-Cycle Model.	Computer	2009	DBLP DOI BibTeX RDF
37	Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen	Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign.	ASP-DAC	2007	DBLP DOI BibTeX RDF
37	Wei-Kei Mak, C.-L. Lai	On Constrained Pin-Mapping for FPGA-PCB Codesign.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
37	Marco D. Santambrogio, Donatella Sciuto	Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign.	FPL	2006	DBLP DOI BibTeX RDF
37	Shaolei Quan, Chin-Long Wey	A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	CMOS, inductance, RF, LNA