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Publication years (Num. hits)
1975-1983 (15) 1984-1988 (15) 1989-1990 (18) 1991-1992 (16) 1993-1994 (16) 1995-1996 (26) 1997-1998 (25) 1999 (15) 2000 (18) 2001 (19) 2002 (21) 2003 (47) 2004 (28) 2005 (47) 2006 (57) 2007 (50) 2008 (57) 2009 (47) 2010 (40) 2011 (31) 2012 (30) 2013 (28) 2014 (34) 2015 (47) 2016 (57) 2017 (57) 2018 (74) 2019 (53) 2020 (78) 2021 (74) 2022 (75) 2023 (75) 2024 (12)
Publication types (Num. hits)
article(489) book(1) incollection(4) inproceedings(805) phdthesis(3)
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Found 1302 publication records. Showing 1302 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
104Gang Han, Robert H. Klenke, James H. Aylor Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2001 DBLP  DOI  BibTeX  RDF crossbar interconnection networks, simulation, performance evaluation, modeling, Multicomputer systems
97Deng Pan, Yuanyuan Yang 0001 Providing flow based performance guarantees for buffered crossbar switches. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
97Trevor N. Mudge, B. A. Makrucki Probabilistic analysis of a crossbar switch. Search on Bibsonomy ISCA The full citation details ... 1982 DBLP  BibTeX  RDF
93Hongbing Fan, Yu-Liang Wu Crossbar based design schemes for switch boxes and programmable interconnection networks. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF switch matrix, FPGA, routing, interconnection network, layout, crossbar, switch box
86Srinivasan Murali, Giovanni De Micheli An Application-Specific Design Methodology for STbus Crossbar Generation. Search on Bibsonomy DATE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
86Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
86Brian Webb, Ahmed Louri A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF scalability, networks, parallel architectures, hypercubes, wavelength division multiplexing, Optical interconnections, crossbars, multiprocessor interconnection
83Michel N. Victor, Aris K. Silzars, Edward S. Davidson A freespace crossbar for multi-core processors. Search on Bibsonomy ICS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF freespace crossbar, interconnect
76Srinivasan Murali, Luca Benini, Giovanni De Micheli An Application-Specific Design Methodology for On-Chip Crossbar Generation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
76Tad Hogg, Greg Snider Defect-tolerant Logic with Nanoscale Crossbar Circuits. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF fault modeling, nanotechnology, molecular electronics, circuit reliability
76Mohammed A. S. Khalid, Jonathan Rose A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. Search on Bibsonomy FPGA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
73Sheng Lin 0006, Yong-Bin Kim, Fabrizio Lombardi Read-out schemes for a CNTFET-based crossbar memory. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF carbon nanotube field effect transistor, crossbar design, read-out circuit, noise margin
73Deng Pan, Yuanyuan Yang 0001 Localized asynchronous packet scheduling for buffered crossbar switches. Search on Bibsonomy ANCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 100% throughput, buffered crossbar switches, priority encoders, packet scheduling
66Lotfi Mhamdi A Partially Buffered Crossbar packet switching architecture and its scheduling. Search on Bibsonomy ISCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
66Bernhard Quatember Modular crossbar switch for large-scale multiprocessor systems: structure and implementation. Search on Bibsonomy AFIPS National Computer Conference The full citation details ... 1981 DBLP  DOI  BibTeX  RDF
65Haitham S. Hamza, Jitender S. Deogun WDM optical interconnects: a balanced design approach. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF wavelength exchange optical crossbar (WOC), optical interconnects, wavelength division multiplexing (WDM), Clos network, crossbar switch, wavelength converter
63Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Diode-resistor logic, logic-level degradation, nano-crossbar circuit, robust circuit design
63Nikos Chrysos, Giorgos Dimitrakopoulos Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF VOQ crossbar scheduler, backlog-aware, deterministic service guarantees, round-robin arbiters, ASIC design
63Tejpal Singh, Alexander Taubin A Highly Scalable GALS Crossbar Using Token Ring Arbitration. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF crossbar design, scalability, latency, arbitration, token rings
62Mohammed A. S. Khalid, Jonathan Rose A novel and efficient routing architecture for multi-FPGA systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
58Rajat Subhra Chakraborty, Swarup Bhunia A study of asynchronous design methodology for robust CMOS-nano hybrid system design. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF CMOS-nano co-design, dual-rail circuits, logic degradation, nano-scale crossbar, Asynchronous design, robust design, micropipelines
56Deng Pan, Yuanyuan Yang 0001 Localized Independent Packet Scheduling for Buffered Crossbar Switches. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
56Mian Dong, Lin Zhong 0001 Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
56Minje Jun, Sungjoo Yoo, Eui-Young Chung Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
56Daeho Seo, Mithuna Thottethodi Table-lookup based Crossbar Arbitration for Minimal-Routed, 2D Mesh and Torus Networks. Search on Bibsonomy IPDPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
56Byung-Joo Hong, Koon-Shik Cho, Seung-Hyun Kang, Suk-Yoon Lee, Jun Dong Cho On the Configurable Multiprocessor SoC Platform with Crossbar Switch. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
56Ted H. Szymanski, Honglin Wu, Amir Gourgy Power complexity of multiplexer-based optoelectronic crossbar switches. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
56Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen Comparison of synthesized bus and crossbar interconnection architectures. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
56Qiang Duan, Xinghe Li, Linjie Zhang Delay Performance Analysis for the Buffered Crossbar Switch . Search on Bibsonomy AINA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
56Panduka Wijetunga High-performance crossbar design for system-on-chip. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52Jonathan S. Turner Strong performance guarantees for asynchronous buffered crossbar scheduler. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF asynchronous crossbars, crossbar schedulers, routers, switches, performance guarantees
52Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
52Simin He 0001, Shutao Sun, Hong-Tao Guan, Qiang Zheng, Youjian Zhao, Wen Gao 0001 On guaranteed smooth switching for buffered crossbar switches. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF scheduling, smoothness, switches, buffered crossbar
52Dianxun Shuai Crossbar Composite Spring-Nets to Optimize Multi-Agent Systems and Computer Networks. Search on Bibsonomy ICIC (2) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF crossbar composite spring nets, multi-agent system, artificial intelligence, distributed problem solving, elastic nets
52Choudhury A. Al Sayeed, Ashraf Matrawy Guaranteed Maximal Matching for Input Buffered Crossbar Switches. Search on Bibsonomy CNSR The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Guaranteed maximal matching, iSLIP, MWM, scheduling, perfect matching, crossbar switches
52Lotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis A reconfigurable hardware based embedded scheduler for buffered crossbar switches. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF buffered crossbar fabric, scheduling, reconfigurable hardware
52Paul-Peter Sotiriadis Information storage capacity of crossbar switching networks. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF nanotube, network, memory, capacity, information, storage, nanotechnology, switching, device, crossbar, nanowire
51Mark Holland, Scott Hauck Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
51Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
51José Carlos Sancho, José Flich, Antonio Robles, Pedro López 0001, José Duato Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks. Search on Bibsonomy IPDPS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF InfiniBand network, virtual lanes, performance evaluation, routing algorithms, irregular topologies
48Mark Holland, Scott Hauck Improving performance and robustness of domain-specific CPLDs. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF computer-aided design, system-on-a-chip, reconfigurable logic, CPLD, sparse crossbar
48Prashanth Pappu, Jonathan S. Turner, Kenneth Wong Work-conserving distributed schedulers for Terabit routers. Search on Bibsonomy SIGCOMM The full citation details ... 2004 DBLP  DOI  BibTeX  RDF CIOQ switches, crossbar scheduling, high performance routers, distributed scheduling
48Kenneth Prager, Michael Vahey, William Farwell, James Whitney, Jon Lieb A Fault Tolerant Signal Processing Computer. Search on Bibsonomy DSN The full citation details ... 2000 DBLP  DOI  BibTeX  RDF distributed crossbar, Fault detection, voting, single event upset, configurable computing, fault recovery
48Peter G. Harrison, Naresh M. Patel The Representation of Multistage Interconnection Networks in Queuing Models of Parallel Systems Search on Bibsonomy J. ACM The full citation details ... 1990 DBLP  DOI  BibTeX  RDF flow-equivalent server, performance evaluation, Markov process, multistage interconnection network, crossbar switch, closed queuing network, delta network
45Lotfi Mhamdi On the Integration of Unicast and Multicast Cell Scheduling in Buffered Crossbar Switches. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
45Jian Wang, Ted H. Szymanski Power analysis of Input-Queued and Crosspoint-Queued crossbar switches. Search on Bibsonomy CCECE The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
45Rajat Subhra Chakraborty, Swarup Bhunia Micropipeline-Based Asynchronous Design Methodology for Robust System Design Using Nanoscale Crossbar. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Diode-resistor logic, CMOSNano, Asynchronous design
45Alexander Kesselman, Kirill Kogan, Michael Segal 0001 Best Effort and Priority Queuing Policies for Buffered Crossbar Switches. Search on Bibsonomy SIROCCO The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
45Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Chih-Chieh Chou, Cheng-Shang Chang, Duan-Shin Lee, Jay Cheng A Necessary and Sufficient Condition for the Construction of 2-to-1 Optical FIFO Multiplexers by a Single Crossbar Switch and Fiber Delay Lines. Search on Bibsonomy IEEE Trans. Inf. Theory The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Paul-Peter Sotiriadis Information Capacity of Nanowire Crossbar Switching Networks. Search on Bibsonomy IEEE Trans. Inf. Theory The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Yungho Choi, Timothy Mark Pinkston Crossbar Analysis for Optimal Deadlock Recovery Router Architecture. Search on Bibsonomy IPPS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
42Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos A buffered crossbar-based chip interconnection framework supporting quality of service. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar
42Simin He 0001, Shutao Sun, Wei Zhao, Yanfeng Zheng, Wen Gao 0001 Smooth switching problem in buffered crossbar switches. Search on Bibsonomy SIGMETRICS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CICQ, scheduling, smoothness, switch, buffered crossbar
42Yuval Tamir, Hsin-Chou Chi Symmetric Crossbar Arbiters for VLSI Communication Switches. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF VLSI communication switches, symmetric crossbar arbiters, multistage interconnectionnetwork, switch arbitration policy, worst-case latency, circuitsimulation, performance evaluation, VLSI, circuit analysis computing, network simulations, critical path, multiprocessorinterconnection networks, system clock
42Hee Yong Youn, Calvin Ching-Yuen Chen A Comprehensive Performance Evaluation of Crossbar Networks. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF processor acceptanceprobability, rejected request handling, home memory concept, performance evaluation, performance evaluation, parallel architectures, multiprocessor interconnection networks, multiprocessing systems, memory bandwidth, crossbar networks, bus arbitration
41Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr. Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF spin-torque devices, fpga, spintronics
41Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie 0001, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das A novel dimensionally-decomposed router for on-chip communication in 3D architectures. Search on Bibsonomy ISCA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF 3D architecture, 3D integration, network-on-chip (NoC)
41Garrett S. Rose, Mircea R. Stan A programmable majority logic array using molecular scale electronics. Search on Bibsonomy FPGA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Norbert Eicker, Thomas Lippert Scalable Ethernet Clos-Switches. Search on Bibsonomy Euro-Par The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping Wu, Ronny Nitzsche, Guang R. Gao A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture. Search on Bibsonomy IPDPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
41Jiho Chang, JongSu Yi, JunSeong Kim A Switch Wrapper Design for SNA On-Chip-Network. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar A methodology for design, modeling, and analysis of networks-on-chip. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41Ziqian Dong, Roberto Rojas-Cessa Long Round-Trip Time Support with Shared-Memory Crosspoint Buffered Packet Switch. Search on Bibsonomy Hot Interconnects The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
41James R. Heath A systems approach to molecular electronics. Search on Bibsonomy ISLPED The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Prashanth Pappu, Jonathan S. Turner Stress Resistant Scheduling Algorithms for CIOQ Switches. Search on Bibsonomy ICNP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
41Vipul Gupta, Eugen Schenfeld Performance analysis of a synchronous, circuit-switched interconnection cached network. Search on Bibsonomy International Conference on Supercomputing The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
38Gaspar Mora, José Flich, José Duato, Pedro López 0001, Elvira Baydal, Olav Lysne Towards an efficient switch architecture for high-radix switches. Search on Bibsonomy ANCS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF arbiter efficiency, partitioned crossbar, switch organization
38Ravi R. Iyer 0001, Laxmi N. Bhuyan Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF scalable interconnects, shared memory multiprocessors, wormhole routing, execution-driven simulation, Crossbar switches, cache architectures
38Jens Kargaard Madsen, Stephen I. Long A High-Speed Interconnect Network Using Ternary Logic. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high-speed interconnect network, STARI, delay differences, crossbar topology, LSI GaAs chips, MESFET process, multiprocessor interconnection networks, multiprocessor system, buffers, clock skew, ternary logic, ternary logic, point-to-point communication
38Imadeldin O. Mahgoub, Ahmed K. Elmagarmid Performance Analysis of a Generalized Class of M-Level Hierarchical Multiprocessor Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF hierarchical multiprocessor systems, system bandwidth, hierarchically nonuniform reference, local requests, m-level system, crossbar system, performance evaluation, performance analysis, probability, multiprocessing systems, multiprocessorinterconnection networks, memory modules, multiple-bus system
35M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Can Emre Koksal On the Speedup Required to Achieve 100% Throughput for Multicast Over Crossbar Switches. Search on Bibsonomy IWQoS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Hans Eberle, Pedro Javier García, José Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins 0001, Wladek Olesinski High-radix crossbar switches enabled by proximity communication. Search on Bibsonomy SC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
35Shyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai Fast Fair Crossbar Scheduler for On-chip Router. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Michael Rosenblum, Constantine Caramanis, Michel X. Goemans, Vahid Tarokh Approximating fluid schedules in crossbar packet-switches and Banyan networks. Search on Bibsonomy IEEE/ACM Trans. Netw. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF scheduling, graph theory, packet-switching, network calculus, combinatorics
35Shinji Sumimoto, Kazuichi Ooe, Kouichi Kumon, Taisuke Boku, Mitsuhisa Sato, Akira Ukawa A scalable communication layer for multi-dimensional hyper crossbar network using multiple gigabit ethernet. Search on Bibsonomy ICS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Raymond R. Hoare, Zhu Ding, Alex K. Jones Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. Search on Bibsonomy SC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35David N. Abramson, Jordan D. Gray, Christopher M. Twigg, Paul E. Hasler Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35B. Afkal, Ali Afzali-Kusha, Mahmoud El Nokali Efficient power model for crossbar interconnects. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Eryk Laskowski, Marek Tudruj Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches. Search on Bibsonomy FPL The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Eryk Laskowski Program Structuring Heuristics for Parallel Systems Based on Multiple Crossbar Switches. Search on Bibsonomy PPAM The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Tamaree Nalin, Isobe Takashi, Hiroaki Morino, Hitoshi Aida, Tadao Saito A Scalable and High Capacity Router on Multi-Dimension Crossbar Switch Principle. Search on Bibsonomy LCN The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Joydeep Ghosh, Anujan Varma, Naveen Krishnamurthy Distributed control schemes for fast arbitration in large crossbar networks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
32Rahul Ratan, A. Yavuz Oruç Self-Routing Quantum Sparse Crossbar Packet Concentrators. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2011 DBLP  DOI  BibTeX  RDF quantum packet concentrator, quantum switching, self-routing switch, sparse crossbar concentrator, Quantum circuits
32Lotfi Mhamdi, Kees Goossens, Iria Varela Senin Buffered Crossbar Fabrics Based on Networks on Chip. Search on Bibsonomy CNSR The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Buffered crossbar fabric, Scheduling
32Mehdi Baradaran Tahoori BISM: built-in self map for hybrid crossbar nano-architectures. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF crossbar array, emerging nanotechnologies, logic mapping
32Hongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee, Jungbum Heo, Kwangki Ryoo Design of Multimedia SoC Platform with a Crossbar On-Chip Bus for Embedded Systems. Search on Bibsonomy NCM (1) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SoC platform, crossbar, on-chip bus
32Cyriel Minkenberg, François Abel, Peter Müller 0002, Raj Krishnamurthy, Mitchell Gusat, Peter Dill, Ilias Iliadis, Ronald P. Luijten, B. Roe Hemenway, Richard Grzybowski, Enrico Schiattarella Designing a Crossbar Scheduler for HPC Applications. Search on Bibsonomy IEEE Micro The full citation details ... 2006 DBLP  DOI  BibTeX  RDF crossbar scheduler, interconnection network, high-performance computing
32Wenjing Rao, Alex Orailoglu, Ramesh Karri Topology aware mapping of logic functions onto nanowire-based crossbar architectures. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF logic synthesis, PLA, nanoelectronic, crossbar
32José G. Delgado-Frias, Girish B. Ratanpal A VLSI wrapped wave front arbiter for crossbar switches. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2001 DBLP  DOI  BibTeX  RDF interconnection network, crossbar switch, arbiter, network router
32Weiming Guo, A. Yavuz Oruç Regular Sparse Crossbar Concentrators. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF crosspoint complexity, regular sparse crossbar, Bipartite graph, concentrator
32Frank T. Hady, Bernard L. Menezes The Performance of Crossbar-Based Binary Hypercubes. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1995 DBLP  DOI  BibTeX  RDF Binary hypercube, throughput, latency, wormhole routing, crossbar, distributed queue
32Mark A. Franklin VLSI Performance Comparison of Banyan and Crossbar Communications Networks. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1981 DBLP  DOI  BibTeX  RDF space-time product, VLSI, communication networks, Banyan network, multiprocessor networks, crossbar networks
31Yan Pan, Prabhat Kumar 0002, John Kim, Gokhan Memik, Yu Zhang 0034, Alok N. Choudhary Firefly: illuminating future network-on-chip with nanophotonics. Search on Bibsonomy ISCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF interconnection networks, topology, hierarchical network, nanophotonics
31Xiangjie Ma, Xiaozhuo Gu, Lei He 0008, Julong Lan, Baisheng Zhang Performance Study on the MPMS Fabric: A Novel Parallel and Distributed Switching System Architecture. Search on Bibsonomy HPCC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Konstantin Likharev Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31John E. Savage Computing at the Nanoscale. Search on Bibsonomy DFT The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
31Krishnendu Roy, Ramachandran Vaidyanathan, Jerry L. Trahan Input-queued switches with logarithmic delay: necessary conditions and a reconfigurable scheduling algorithm. Search on Bibsonomy ANCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF distributed scheduling algorithm, parallel bipartite matching, reconfigurable mesh, mesh-of-trees, input-queued switch
31Wenjing Rao, Alex Orailoglu, Ramesh Karri Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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