Search results for "DPA-resistant"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
83	Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri	Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
77	Lang Lin, Wayne P. Burleson	Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems.	ISCAS	2008	DBLP DOI BibTeX RDF
77	Konrad J. Kulikowski, Ming Su, Alexander B. Smirnov, Alexander Taubin, Mark G. Karpovsky, Daniel MacDonald	Delay Insensitive Encoding and Power Analysis: A Balancing Act.	ASYNC	2005	DBLP DOI BibTeX RDF
72	Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo	Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware.	DATE	2007	DBLP DOI BibTeX RDF
65	Manfred von Willich	A Technique with an Information-Theoretic Basis for Protecting Secret Data from Differential Power Attacks.	IMACC	2001	DBLP DOI BibTeX RDF
64	Jianping Quan, Guoqiang Bai 0001	A DPA-Resistant Digit-Parallel Modular Multiplier over GF (2m).	ITNG	2009	DBLP DOI BibTeX RDF	Modular multiplier, DPA-resistant, 1-bit masking, ECC, Architecture level
61	Eric Menendez, Ken Mai	A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.	HOST	2008	DBLP DOI BibTeX RDF
54	Vijay Sundaresan, Srividhya Rammohan, Ranga Vemuri	Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
54	Kouichi Itoh, Tetsuya Izu, Masahiko Takenaka	Improving the Randomized Initial Point Countermeasure Against DPA.	ACNS	2006	DBLP DOI BibTeX RDF	RPA, ZVA, Smart card, DPA, Elliptic Curve Cryptosystems (ECC), countermeasure, RIP
54	Emmanuel Prouff, Christophe Giraud 0001, Sébastien Aumônier	Provably Secure S-Box Implementation Based on Fourier Transform.	CHES	2006	DBLP DOI BibTeX RDF	Provably Secure Countermeasure, Symmetric Cryptosystems, FOX, AES, Differential Power Analysis, Fourier Transform, S-Box
53	Benedikt Gierlichs, Lejla Batina, Pim Tuyls, Bart Preneel	Mutual Information Analysis.	CHES	2008	DBLP DOI BibTeX RDF	Differential Side-Channel Analysis (DSCA), DPA-resistant logic, Information Theory, Mutual Information
49	Yi Wang 0016, Jussipekka Leiwo, Thambipillai Srikanthan, Yu Yu	FPGA based DPA-resistant Unified Architecture for Signcryption.	ITNG	2006	DBLP DOI BibTeX RDF
49	Kris Tiri, Ingrid Verbauwhede	A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation.	DATE	2004	DBLP DOI BibTeX RDF
42	Tae-Jun Park, Mun-Kyu Lee, Dowon Hong, Kyoil Chung	A DPA Countermeasure by Randomized Frobenius Decomposition.	WISA	2005	DBLP DOI BibTeX RDF
42	Louis Goubin, Jacques Patarin	DES and Differential Power Analysis (The "Duplication" Method).	CHES	1999	DBLP DOI BibTeX RDF
34	Thomas Popp, Mario Kirschbaum, Stefan Mangard	Practical Attacks on Masked Hardware.	CT-RSA	2009	DBLP DOI BibTeX RDF	DPA-Resistant Masked Logic Styles, MDPL, Prototype Chip, Hardware AES, PDF-Attack, PRNG
34	Thomas Popp, Stefan Mangard, Elisabeth Oswald	Power Analysis Attacks and Countermeasures.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	DPA-resistant logic styles, countermeasures, power analysis attacks
34	Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard	Evaluation of the Masked Logic Style MDPL on a Prototype Chip.	CHES	2007	DBLP DOI BibTeX RDF	DPA-Resistant Logic Styles, Masked Logic, Dual-Rail Precharge Logic, Early Propagation Effect, Improved MDPL, Prototype Chip
31	Yi Wang 0016, Jussipekka Leiwo, Thambipillai Srikanthan, Luo Jianwen	An Efficient Algorithm for DPA-resistent RSA.	APCCAS	2006	DBLP DOI BibTeX RDF
31	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.	DATE	2005	DBLP DOI BibTeX RDF
31	Suresh Chari, Josyula R. Rao, Pankaj Rohatgi	Template Attacks.	CHES	2002	DBLP DOI BibTeX RDF
30	Mohammad Gholamzadeh, Behrooz Khadem	A Hybrid Image Encryption Scheme based on Chaos and a DPA-Resistant Sbox.	CoRR	2023	DBLP DOI BibTeX RDF
30	Ali A. El-Moursy, Abdollah Masoud Darya, Ahmed S. Elwakil, Abhinand Jha, Sohaib Majzoub	Chaotic Clock Driven Cryptographic Chip: Towards a DPA Resistant AES Processor.	IEEE Trans. Emerg. Top. Comput.	2022	DBLP DOI BibTeX RDF
30	Man Wei, Siwei Sun, Zihao Wei, Zheng Gong, Lei Hu	A small first-order DPA resistant AES implementation with no fresh randomness.	Sci. China Inf. Sci.	2022	DBLP DOI BibTeX RDF
30	S. Dinesh Kumar, Zachary Kahleifeh, Himanshu Thapliyal	Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design.	SN Comput. Sci.	2021	DBLP DOI BibTeX RDF
30	Ehsan Panahifar, Alireza Hassanzadeh	DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
30	Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang	A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.	ISCAS	2020	DBLP DOI BibTeX RDF
30	S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad	EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card.	IEEE Trans. Emerg. Top. Comput.	2019	DBLP DOI BibTeX RDF
30	Youle Xu, Qichun Wang	Searching for Highly Nonlinear DPA-Resistant Balanced Boolean Functions in the Rotation Symmetric Class.	ISIT	2019	DBLP DOI BibTeX RDF
30	Saman Kaedi, Mohammad-Ali Doostari, Mohammad Bagher Ghaznavi Ghoushchi	Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices.	IET Comput. Digit. Tech.	2018	DBLP DOI BibTeX RDF
30	S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad	FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
30	Himanshu Thapliyal, T. S. S. Varun, S. Dinesh Kumar	Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices.	ISVLSI	2017	DBLP DOI BibTeX RDF
30	Rei Ueno, Naofumi Homma, Takafumi Aoki	Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation.	COSADE	2017	DBLP DOI BibTeX RDF
30	James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee	DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer.	ISCAS	2017	DBLP DOI BibTeX RDF
30	S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad	FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices.	ICRC	2016	DBLP DOI BibTeX RDF
30	Matthew A. Morrison, Nagarajan Ranganathan, Jay Ligatti	Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2015	DBLP DOI BibTeX RDF
30	Linghao Zhu, Cheng Wu, Linyin Wu, Junyu Wang, Hao Min	A DPA-resistant crypto engine for UHF RFID tag.	Int. J. Embed. Syst.	2015	DBLP DOI BibTeX RDF
30	Xiao Pang, Jing Wang, Chenxu Wang, Xinsheng Wang	A DPA resistant dual rail Préchargé logic cell.	ASICON	2015	DBLP DOI BibTeX RDF
30	Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai	A DPA-resistant self-timed three-phase dual-rail pre-charge logic family.	HOST	2015	DBLP DOI BibTeX RDF
30	Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta 0001	A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2014	DBLP DOI BibTeX RDF
30	Yi Wang 0016, Yajun Ha	A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2014	DBLP DOI BibTeX RDF
30	Massimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti	Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.	IEEE Trans. Circuits Syst. I Regul. Pap.	2014	DBLP DOI BibTeX RDF
30	Stjepan Picek, Lejla Batina, Domagoj Jakobovic	Evolving DPA-Resistant Boolean Functions.	PPSN	2014	DBLP DOI BibTeX RDF
30	Jungmin Park, Akhilesh Tyagi	Towards Making Private Circuits Practical: DPA Resistant Private Circuits.	ISVLSI	2014	DBLP DOI BibTeX RDF
30	Erica Tena-Sánchez, Javier Castro-Ramirez, Antonio J. Acosta 0001	Low-Power Differential Logic Gates for DPA Resistant Circuits.	DSD	2014	DBLP DOI BibTeX RDF
30	Mehrdad Khatir, Leyla Nazhandali	Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit.	ISQED	2014	DBLP DOI BibTeX RDF
30	Suvadeep Hajra, Chester Rebeiro, Shivam Bhasin, Gaurav Bajaj, Sahil Sharma, Sylvain Guilley, Debdeep Mukhopadhyay	DRECON: DPA Resistant Encryption by Construction.	AFRICACRYPT	2014	DBLP DOI BibTeX RDF
30	Partha De, Kunal Banerjee 0001, Chittaranjan A. Mandal, Debdeep Mukhopadhyay	Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.	DSD	2013	DBLP DOI BibTeX RDF
30	Begül Bilgin, Joan Daemen, Ventzislav Nikov, Svetla Nikova, Vincent Rijmen, Gilles Van Assche	Efficient and First-Order DPA Resistant Implementations of Keccak.	CARDIS	2013	DBLP DOI BibTeX RDF
30	Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti	A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.	MIXDES	2013	DBLP BibTeX RDF
30	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
30	Lakshmi Narasimhan Ramakrishnan, Manoj Chakkaravarthy, Antarpreet Singh Manchanda, Mike Borowczak, Ranga Vemuri	SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits.	HOST	2012	DBLP DOI BibTeX RDF
30	Hsing-Ping Fu, Ju-Hung Hsiao, Po-Chun Liu, Hsie-Chia Chang, Chen-Yi Lee	A low cost DPA-resistant 8-bit AES core based on ring oscillators.	VLSI-DAT	2012	DBLP DOI BibTeX RDF
30	Yang Li 0001, Kazuo Sakiyama, Shin-ichi Kawamura, Kazuo Ohta	Power Analysis against a DPA-Resistant S-Box Implementation Based on the Fourier Transform.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2011	DBLP DOI BibTeX RDF
30	Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee	A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence.	ESSCIRC	2011	DBLP DOI BibTeX RDF
30	Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto	Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.	ISCAS	2011	DBLP DOI BibTeX RDF
30	Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino	Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL.	HOST	2011	DBLP DOI BibTeX RDF
30	Xiaoyi Duan, Ronglei Hu, Xiu Ying Li	Research and Implementation of DPA-resistant SMS4 Block Cipher.	CIS	2011	DBLP DOI BibTeX RDF
30	Alessandro Cevrero, Francesco Regazzoni 0001, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici	Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.	DAC	2011	DBLP DOI BibTeX RDF
30	Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto	A Design Methodology for a DPA-Resistant Circuit with RSL Techniques.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2010	DBLP DOI BibTeX RDF
30	Jens-Peter Kaps, Rajesh Velegalati	DPA Resistant AES on FPGA Using Partial DDL.	FCCM	2010	DBLP DOI BibTeX RDF
30	Yingxi Lu, Keanhong Boey, Philip Hodgers, Máire O'Neill	Lightweight DPA resistant solution on FPGA to counteract power models.	FPT	2010	DBLP DOI BibTeX RDF
30	Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh	A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.	CHES	2009	DBLP DOI BibTeX RDF
30	Francesco Regazzoni 0001, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne	A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions.	CHES	2009	DBLP DOI BibTeX RDF
30	Yang Li 0001, Kazuo Sakiyama, Shin-ichi Kawamura, Yuichi Komano, Kazuo Ohta	Security Evaluation of a DPA-Resistant S-Box Based on the Fourier Transform.	ICICS	2009	DBLP DOI BibTeX RDF
30	Mario Kirschbaum, Thomas Popp	Evaluation of a DPA-Resistant Prototype Chip.	ACSAC	2009	DBLP DOI BibTeX RDF
30	Mehrdad Khatir, Amir Moradi 0001	Secure Adiabatic Logic: a Low-Energy DPA-Resistant Logic Style.	IACR Cryptol. ePrint Arch.	2008	DBLP BibTeX RDF
30	Amir Moradi 0001, Thomas Eisenbarth 0001, Axel Poschmann, Carsten Rolfes, Christof Paar, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh	Information Leakage of Flip-Flops in DPA-Resistant Logic Styles.	IACR Cryptol. ePrint Arch.	2008	DBLP BibTeX RDF
30	Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad Taghi Manzuri Shalmani	On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices.	CSICC	2008	DBLP DOI BibTeX RDF
30	Matteo Giaconia, Marco Macchetti, Francesco Regazzoni 0001, Kai Schramm	Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes.	VLSI Design	2007	DBLP DOI BibTeX RDF
30	Frédéric Amiel, Christophe Clavier, Michael Tunstall	Fault Analysis of DPA-Resistant Algorithms.	FDTC	2006	DBLP DOI BibTeX RDF
30	Thomas Popp, Stefan Mangard	Implementation aspects of the DPA-resistant logic style MDPL.	ISCAS	2006	DBLP DOI BibTeX RDF
30	Yoo-Jin Baek, Mi-Jung Noh	DPA-Resistant Finite Field Multipliers and Secure AES Design.	ISPEC	2006	DBLP DOI BibTeX RDF
30	Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti	A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.	PATMOS	2004	DBLP DOI BibTeX RDF	chipcards, cryptography, Differential power analysis, DPA, power analysis, countermeasures
30	Thomas S. Messerges	Using Second-Order Power Analysis to Attack DPA Resistant Software.	CHES	2000	DBLP DOI BibTeX RDF
19	Stefan Tillich, Johann Großschädl	Power Analysis Resistant AES Implementation with Instruction Set Extensions.	CHES	2007	DBLP DOI BibTeX RDF	embedded RISC processor, SPARC V8 architecture, SCA resistance, Advanced Encryption Standard, power analysis, instruction set extensions