Search results for "FPGA-Test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
24	Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	The gigahertz FPGA: design consideration and applications.	FPGA	2004	DBLP DOI BibTeX RDF
21	Shahin Toutounchi, Andrew Lai	FPGA Test and Coverage.	ITC	2002	DBLP DOI BibTeX RDF
18	Mehdi Baradaran Tahoori, Subhasish Mitra	Techniques and algorithms for fault grading of FPGA interconnect test configurations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
18	Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin Toutounchi, Edward J. McCluskey	Fault Grading FPGA Interconnect Test Configurations.	ITC	2002	DBLP DOI BibTeX RDF
17	Aiwu Ruan, Shi Kang, Yu Wang, Xiao Han, Zujian Zhu, Yongbo Liao, Peng Li	A Built-In Self-Test (BIST) system with non-intrusive TPG and ORA for FPGA test and diagnosis.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
14	Alessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca	Revisiting Application-Dependent Test for FPGA Devices.	ETS	2011	DBLP DOI BibTeX RDF	Application-Dependent test, FPGA test
14	Alireza Rohani, Hamid R. Zarandi	A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs.	ReConFig	2009	DBLP DOI BibTeX RDF	Dependability, FPGA-Test
14	Abderrahim Doumar, Hideo Ito	Testing approach within FPGA-based fault tolerant systems.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	FPGA-based fault-tolerant systems, FPGA test strategy, configurable logic blocks, functional phase, on-chip configuration data shifting, shifting process control, test application, test observation, fault tolerance management logic, fault tolerance cost, chip functionality, delay overhead, Xilinx FPGA, fault tolerance, field programmable gate arrays, delays, integrated circuit testing, integrated logic circuits, testing time, user data, test phase
14	Miron Abramovici, Charles E. Stroud, Brandon Skaggs, John Marty Emmert	Improving On-Line BIST-Based Diagnosis for Roving STARs.	IOLTW	2000	DBLP DOI BibTeX RDF	on-line testing and diagnosis, FPGA test and diagnosis
12	Rafael Romón Sagredo, Erik Börjeson, Ali Mirani, Magnus Karlsson 0001, Per Larsson-Edefors	Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs.	NorCAS	2022	DBLP DOI BibTeX RDF
12	Xianjian Zheng, Fan Zhang, Lei Chen 0010, Zhiping Wen 0001, Yuanfu Zhao, Xuewu Li	A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm (Abstract Only).	FPGA	2015	DBLP DOI BibTeX RDF
12	Kai Yang, Yanqing Zhao, Jianguo Yang, Xiaoyong Xue, Yinyin Lin, Jun-Soo Bae	Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform.	ASICON	2015	DBLP DOI BibTeX RDF
12	T. Du, Aiwu Ruan, P. Li, Bairui Jie	A bitstream readback based FPGA test and diagnosis system.	ISIC	2014	DBLP DOI BibTeX RDF
12	Jorge H. Meza Escobar, Jörg Sachße, Steffen Ostendorff, Heinz-Dietrich Wuttke	ISA configurability of an FPGA test-processor used for board-level interconnection testing.	LATW	2013	DBLP DOI BibTeX RDF
12	Martin Rozkovec, Jiri Jenícek, Ondrej Novák	An evaluation of the application dependent FPGA test method.	DDECS	2012	DBLP DOI BibTeX RDF
12	Muhammad Aqeel Wahlah, Kees Goossens	A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip.	DSD	2011	DBLP DOI BibTeX RDF
12	Xiaoyan Jiang, Yujun Bao	Application of SignalTap II Logic Analyzer in the FPGA Test.	DBTA	2010	DBLP DOI BibTeX RDF
12	David Fang, John Teifel, Rajit Manohar	A High-Performance Asynchronous FPGA: Test Results.	FCCM	2005	DBLP DOI BibTeX RDF
12	Stuart McCracken, Zeljko Zilic	FPGA test time reduction through a novel interconnect testing scheme.	FPGA	2002	DBLP DOI BibTeX RDF
11	Erik Chmelar	Minimizing the number of test configurations for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
10	Marco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano	Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers.	DFT	2006	DBLP DOI BibTeX RDF
10	Kuan Zhou, John F. McDonald 0001	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
10	Jong-Ru Guo, Chao You, Peter F. Curran, Michael Chu, Kuan Zhou, Jiedong Diao, A. George, Russell P. Kraft, John F. McDonald 0001	The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	10 GHz, 1:4 DEMUX, 4:1 MUX, FPGA, SiGe
8	Rohini Krishnan, José Pineda de Gyvez, Harry J. M. Veendrick	Encoded-Low Swing Technique for Ultra Low Power Interconnect.	FPL	2003	DBLP DOI BibTeX RDF