Search results for "FSM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
129	Chunduri Rama Mohan, Partha Pratim Chakrabarti	A new approach for factorizing FSM's.	ICCAD	1994	DBLP DOI BibTeX RDF
110	Lin Yuan, Gang Qu 0001, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli	FSM re-engineering and its application in low power state encoding.	ASP-DAC	2005	DBLP DOI BibTeX RDF
109	Anzhela Yu. Matrosova, Sergey Ostanin	Self-Checking FSM Design with Observing only FSM Outputs.	IOLTW	2000	DBLP DOI BibTeX RDF	Self-checking design, unidirectional fault, PLA description, multilevel synthesis, FSM
93	Lin Yuan, Gang Qu 0001	Information Hiding in Finite State Machine.	Information Hiding	2004	DBLP DOI BibTeX RDF
92	Lin Yuan, Gang Qu 0001, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli	An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
92	Michael Affenzeller, Franz Pichler, Rudolf Mittelmann	On CAST.FSM Computation of Hierarchical Multi-layer Networks of Automata.	EUROCAST	2001	DBLP DOI BibTeX RDF
92	Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das	Synthesis of Testable Finite State Machine Through Decomposition.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	emitability, FSM state encoding, decomposition, reachability, degree-of-freedom
91	Chunduri Rama Mohan, Partha Pratim Chakrabarti	Combined optimization of area and testability during state assignment of PLA-based FSM's.	VLSI Design	1995	DBLP DOI BibTeX RDF	combined optimization, testability optimisation, PLA-based FSM, EARTH algorithm, single cross-point faults, redundancy checker, fault diagnosis, logic testing, redundancy, finite state machines, integrated circuit testing, design for testability, fault model, logic CAD, programmable logic arrays, circuit layout CAD, circuit optimisation, integrated circuit layout, state assignment, state assignment, minimisation of switching nets, single stuck-at faults, area minimization
83	José C. Monteiro 0001, Arlindo L. Oliveira	Implicit FSM decomposition applied to low-power design.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
73	Valeri Solovjev	Refined CPLD Macrocell Architecture for the Effective FSM Implementation.	EUROMICRO	1999	DBLP DOI BibTeX RDF
72	Ioan Tabus, Jorma Rissanen, Jaakko Astola	Adaptive L-Predictors Based on Finite State Machine Context Selection.	ICIP (1)	1997	DBLP DOI BibTeX RDF	adaptive L-predictors, finite state machine context selection, adaptive nonlinear predictors, FSM context modeller, adaptive design, FSM-context L-predictor, image coding, lossless compression, gray level images
65	Sezer Gören 0001, F. Joel Ferguson	Test sequence generation for controller verification and test with high coverage.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	finite state machine, Fault coverage, black box testing, X-machine
65	Richard Raimi, Ramin Hojati, Kedar S. Namjoshi	Environment modeling and language universality.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	language universality, model checking, abstraction, environment modeling
65	Franco Fummi, U. Rovati, Donatella Sciuto	Functional design for testability of control-dominated architectures.	ACM Trans. Design Autom. Electr. Syst.	1997	DBLP DOI BibTeX RDF	interacting FSMs, functional testing
65	Chien-Nan Jimmy Liu, Jing-Yang Jou	An Efficient Functional Coverage Test for HDL Descriptions at RTL.	ICCD	1999	DBLP DOI BibTeX RDF	verification, coverage, FSM, HDL
64	Cao Cao, Bengt Oelmann	Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design.	DSD	2004	DBLP DOI BibTeX RDF
56	Valeri Solovjev	Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines.	DSD	2001	DBLP DOI BibTeX RDF
56	José C. Monteiro 0001, Arlindo L. Oliveira	Finite State Machine Decomposition For Low Power.	DAC	1998	DBLP DOI BibTeX RDF	system-on-chip test, testing embedded core, intellectual property test
55	Nina Yevtushenko 0001, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli	Compositionally Progressive Solutions of Synchronous FSM Equations.	Discret. Event Dyn. Syst.	2008	DBLP DOI BibTeX RDF	Language equations, Progressive solutions, Synchronous composition, Finite state machines
55	Khaled El-Fakih, Nina Yevtushenko 0001	Progressive Solutions to FSM Equations.	CIAA	2008	DBLP DOI BibTeX RDF
55	Dohyung Kim 0007, Soonhoi Ha	Static analysis and automatic code synthesis of flexible FSM model.	ASP-DAC	2005	DBLP DOI BibTeX RDF
55	Alexandre Petrenko, Nina Yevtushenko 0001	Conformance Tests as Checking Experiments for Partial Nondeterministic FSM.	FATES	2005	DBLP DOI BibTeX RDF
55	Dominik Stoffel, Markus Wedler, Peter Warkentin, Wolfgang Kunz	Structural FSM traversal.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
55	Richard J. Busman	FSM - a fullscreen manager.	APL	1987	DBLP DOI BibTeX RDF	APL
54	Biplab K. Sikdar, Samir Roy, Debesh K. Das	A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	emitability, FSM state encoding, reachability, degree-of-freedom
54	Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee	Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.	ACM Trans. Design Autom. Electr. Syst.	1998	DBLP DOI BibTeX RDF	binary decision, encoding density, multi-phase FSM, product machine, sequential hardware equivalence, diagram, steady states
46	Minh D. Nguyen, Max Thalmaier, Markus Wedler, Jörg Bormann, Dominik Stoffel, Wolfgang Kunz	Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
46	Hermann Kopetz, Christian El Salloum, Bernhard Huber, Roman Obermaisser	Periodic Finite-State Machines.	ISORC	2007	DBLP DOI BibTeX RDF
46	Ali Habibi, Haja Moinudeen, Sofiène Tahar	Generating finite state machines from SystemC.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
46	ChangRyul Yun, YoungHwan Bae, HanJin Cho, KyoungSon Jhang	Automatic Synthesis of Interface Circuits from Simplified IP Interface Protocols.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
46	Shuo Chen 0001, Zbigniew Kalbarczyk, Jun Xu 0003, Ravishankar K. Iyer	A Data-Driven Finite State Machine Model for Analyzing Security Vulnerabilities.	DSN	2003	DBLP DOI BibTeX RDF	data analysis, security vulnerabilities, finite state machine modeling
46	Roman Goot, Ilya Levin, Sergei Ostanin	Fault Latencies of Concurrent Checking FSMs.	DSD	2002	DBLP DOI BibTeX RDF
46	Petros Drineas, Yiorgos Makris	Non-Intrusive Design of Concurrently Self-Testable FSMs.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
46	Lilia Kashirova, Olga Tveretina	Entropy-Based Design of Low Power FSMs.	EUROMICRO	1998	DBLP DOI BibTeX RDF
46	Aziz Salah, Rabeb Mizouni, Rachida Dssouli, Benoit Parreaux	Formal Composition of Distributed Scenarios.	FORTE	2004	DBLP DOI BibTeX RDF	Scenario-based approach, Scenario composition, Distributed systems, Formal specification, Use case, FSM
46	Wolfgang Grieskamp, Yuri Gurevich, Wolfram Schulte, Margus Veanes	Generating finite state machines from abstract state machines.	ISSTA	2002	DBLP DOI BibTeX RDF	finite state machine, test case generation, FSM, abstract state machine, executable specification, ASM
45	Johannes Feiner	The fluid software metadata framework (FSM).	EICS	2010	DBLP DOI BibTeX RDF	usability issues, framework, metrics, visualisation, development tools, web interface, software repositories
45	Xi Wang 0017, Liang Guo, Huaikou Miao	An Approach to Transforming UML Model to FSM Model for Automatic Testing.	CSSE (2)	2008	DBLP DOI BibTeX RDF
45	SukKeong Goh, Mohan Baruwal Chhetri, Ryszard Kowalczyk	JADE-FSM-Engine: A Deployment Tool for Flexible Agent Behaviours in JADE.	IAT	2007	DBLP DOI BibTeX RDF
45	Zhong-sheng Qian, Huaikou Miao, Shengbo Chen	Towards Modeling Web Navigation Using FSM and Z.	IITA	2007	DBLP DOI BibTeX RDF
45	Man-Yun Su, Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou	FSM-based transaction-level functional coverage for interface compliance verification.	ASP-DAC	2006	DBLP DOI BibTeX RDF
45	Nina Yevtushenko 0001, Svetlana Zharikova, Maria Vetrova	Multi Component Digital Circuit Optimization by Solving FSM Equations.	DSD	2003	DBLP DOI BibTeX RDF
45	Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka	A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
45	Chunduri Rama Mohan, Partha Pratim Chakrabarti	EARTH: combined state assignment of PLA-based FSM's targeting area and testability.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
45	Thomas Müller-Wipperfürth	On the Integration of CAST.FSM into the VLSI Design Process.	CAST	1994	DBLP DOI BibTeX RDF
45	Thomas Müller-Wipperfürth, Josef Scharinger, Franz Pichler	FSM Shift Register Realization for Improved Testability.	EUROCAST	1993	DBLP DOI BibTeX RDF
45	Alfred Spalt	Implementation of Finite-Memory Machines within CAST: FSM.	EUROCAST	1989	DBLP DOI BibTeX RDF
45	Silvia Mara Abrahão, Geert Poels, Oscar Pastor 0001	Assessing the Reproducibility and Accuracy of Functional Size Measurement Methods through Experimentation.	ISESE	2004	DBLP DOI BibTeX RDF	FSM methods, IFPUG Function Point Analysis, OO-Method Function Points, Empirical Validation
45	Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske	Low Power Design of FSMs by State Assignment and Disabling Self-Loops.	EUROMICRO	1997	DBLP DOI BibTeX RDF	FSM synthesis, encoding constraints, low power design, clock gating, state assignment
44	Samir Roy, Biplab K. Sikdar	Power Conscious BIST Design for Sequential Circuits Using ghost-FSM.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Ghost-FSM, power conscious BIST, built-in self-test, multi-objective genetic algorithm, state assignment
37	Luigi Buglione, Juan Jose Cuadrado-Gallego, José Antonio Gutiérrez de Mesa	Project Sizing and Estimating: A Case Study Using PSU, IFPUG and COSMIC.	IWSM/Metrikon/Mensura	2008	DBLP DOI BibTeX RDF	Project Size Unit (PSU), Scope Management, Estimation, Case Study, Non-Functional Requirements, Function Points
37	Tiziano Villa, Svetlana Zharikova, Nina Yevtushenko 0001, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	A new algorithm for the largest compositionally progressive solution of synchronous language equations.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	progressive solutions, unknown component problem, finite automata, sequential synthesis
37	Anurag Tiwari, Karen A. Tomko	Enhanced reliability of finite-state machines in FPGA through efficient fault detection and correction.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
37	Iouliia Skliarova	Self-correction of FPGA-Based Control Units.	ICESS	2005	DBLP DOI BibTeX RDF	Self-correcting finite state machines, specification in VHDL, Hamming codes
37	Yujun Zhang, Zhongcheng Li	Formal Description of Mobile IPv6 Protocol.	FORTE	2005	DBLP DOI BibTeX RDF
37	Malcolm Benjamin Dias, Bernard F. Buxton	Enforcing a Shape Correspondence between Two Views of a 3D Non-rigid Object.	CIARP	2003	DBLP DOI BibTeX RDF
37	Samir Roy, Ujjwal Maulik, Biplab K. Sikdar	Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines.	VLSI Design	2003	DBLP DOI BibTeX RDF
37	Petros Drineas, Yiorgos Makris	SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs.	VLSI Design	2003	DBLP DOI BibTeX RDF
37	Priyank Kalla, Maciej J. Ciesielski	A comprehensive approach to the partial scan problem using implicitstate enumeration.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
37	Jürgen Teich, Markus Köster	(Self-)reconfigurable Finite State Machines: Theory and Implementation.	DATE	2002	DBLP DOI BibTeX RDF
37	Timothy Sherwood, Brad Calder	Automated design of finite state machine predictors for customized processors.	ISCA	2001	DBLP DOI BibTeX RDF
37	Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen	A Buffer-Oriented Methodology for Microarchitecture Validation.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	processor validation, superscalar microarchitecture, design validation
37	Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth	A synthesis for testability scheme for finite state machines using clock control.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
37	Alain Girault, Bilung Lee, Edward A. Lee	Hierarchical finite state machines with multiple concurrency models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
37	Bilung Lee, Edward A. Lee	Hierarchical Concurrent Finite State Machines in Ptolemy.	ACSD	1998	DBLP DOI BibTeX RDF	concurrency, finite state machine, heterogeneity, hierarchy
37	Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda	Cellular automata for deterministic sequential test pattern generation.	VTS	1997	DBLP DOI BibTeX RDF	deterministic sequential test pattern generation, cellular automaton identification, hardware structure, area occupation, ASIC testing, evolutionary algorithm, cellular automata, BIST, fault coverage, stuck-at faults, FSM, deterministic automata
37	Gilbert Babin, François Lustman, Peretz Shoval	Specification and Design of Transactions in Information Systems: A Formal Approach.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	conventional information systems development, manual checking, transformational paradigm, ADISSA notation, transaction-oriented refinement, structured systems analysis, hierarchical set, formal specification, formal specification, data integrity, finite state machine, systems analysis, transaction processing, requirements specifications, finite automata, FSM, structured programming, formal approach
36	Benfano Soewito, Lucas Vespa, Atul Mahajan, Ning Weng, Haibo Wang 0005	Self-addressable memory-based FSM: a scalable intrusion detection engine.	IEEE Netw.	2009	DBLP DOI BibTeX RDF
36	Eleftheria Athanasopoulou, Christoforos N. Hadjicostis	Bounds on FSM Switching Activity.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	Low power design, Markov models, Hamming distance, State assignment, Switching activity
36	Hrushikesha Mohanty, Jitesh Mulchandani, Deepak Chenthati, R. K. Shyamasundar	Modeling Web Services with FSM Modules.	Asia International Conference on Modelling and Simulation	2007	DBLP DOI BibTeX RDF
36	Valery Salauyou, Tomasz Grzes	FSM State Assignment Methods for Low-Power Design.	CISIM	2007	DBLP DOI BibTeX RDF
36	Lech Józwiak, Aleksander Slusarczyk, Dominik Gawlowski	Multi-objective Optimal FSM State Assignment.	DSD	2006	DBLP DOI BibTeX RDF
36	Xunmei Gu, Guoxin Song, Qingyi Li	An Improved FSM Method for Web-based Applications.	CIMCA/IAWTIC	2006	DBLP DOI BibTeX RDF
36	Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk	An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods.	DSD	2004	DBLP DOI BibTeX RDF
36	Eleftheria Athanasopoulou, Christoforos N. Hadjicostis	Upper and lower bounds on FSM switching activity.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
36	Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz	GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.	VLSI Design	2003	DBLP DOI BibTeX RDF
36	Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo	FSM Decomposition for Low Power in FPGA.	FPL	2002	DBLP DOI BibTeX RDF
36	Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi	Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model.	CODES	2002	DBLP DOI BibTeX RDF
36	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	Bisimulation relation, complete-1-distinguishability, finite state machine equivalence, sequential logic synthesis, equivalence checking
36	Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou	Automatic Functional Vector Generation Using the Interacting FSM Model.	ISQED	2001	DBLP DOI BibTeX RDF
36	Jun-Jang Jeng, Wang-Chuan Tsai	Designing An FSM Architectural Framework for Service-Based Applications.	COMPSAC	2000	DBLP DOI BibTeX RDF
36	Sandra Camargo Pinto Ferraz Fabbri, José Carlos Maldonado, Paulo César Masiero, Márcio Eduardo Delamaro	Proteum/FSM: A Tool to Support Finite State Machine Validation Based on Mutation Testing.	SCCC	1999	DBLP DOI BibTeX RDF	Software Testing, Tools, Finite State Machines, Reactive Systems, Mutation Testing
36	Samary Baranov	CAD System for ASM and FSM Synthesis.	FPL	1998	DBLP DOI BibTeX RDF
36	A. Tuagi	Entropic bounds on FSM switching.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
36	Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi	Automatic state space decomposition for approximate FSM traversal based on circuit analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
36	Pranav Ashar, Aarti Gupta, Sharad Malik	Using complete-1-distinguishability for FSM equivalence checking.	ICCAD	1996	DBLP DOI BibTeX RDF	sequential logic synthesis and verification, finite state machine equivalence, bisimulation relation, 1-distinguishability, 1-equivalence, formal verification
36	Thomas Müller-Wipperfürth	Linking CAST.FSM to Practical Applications.	EUROCAST	1991	DBLP DOI BibTeX RDF
36	Martin Geiger	CAST.FSM Applied to VLSI Synthesis: Experimental Results and Requirements for Industrial Use.	EUROCAST	1991	DBLP DOI BibTeX RDF
36	Oktay Türetken, Özden Özcan Top, Baris Özkan, Onur Demirörs	The Impact of Individual Assumptions on Functional Size Measurement.	IWSM/Metrikon/Mensura	2008	DBLP DOI BibTeX RDF	COSMIC FSM, IFPUG FPA, MkII FPA, Functional Size Measurement
36	Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth	Synthesis for Testability by Two-Clock Control.	VLSI Design	1997	DBLP DOI BibTeX RDF	two-clock control scheme, split coding system, FSM benchmark, timing, finite state machine, sequential circuit, encoding, logic synthesis, Hamiltonian cycle, synthesis for testability, state transition graph
36	Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja	An optimized testable architecture for finite state machines.	VTS	1995	DBLP DOI BibTeX RDF	optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence
36	Jason W. Horihan, Yung-Hsiang Lu	Improving FSM evolution with progressive fitness functions.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	genetic inference, evolution, finite state machine, fitness, FSM, fitness function, evolutionary design, automated design
35	Önder Eren, Baris Özkan, Onur Demirörs	PL FSM: An Approach and a Tool for the Application of FSM in SPL Environments.	EUROMICRO-SEAA	2015	DBLP DOI BibTeX RDF
35	Zafar Hasan, Maciej J. Ciesielski	FSM Decomposition and Functional Verification of FSM Networks.	VLSI Design	1995	DBLP DOI BibTeX RDF
35	Alexandre Petrenko, Nina Yevtushenko 0001	Testing from Partial Deterministic FSM Specifications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	partially specified FSM, weak conformance testing, test generation, Finite State Machine, fault detection, checking experiment, state identification
35	M. Tuan Tu, Eberhard Wolff, Winfried Lamersdorf	Genetic Algorithms for Automated Negotiations: A FSM-Based Application.	DEXA Workshops	2000	DBLP DOI BibTeX RDF	FSM based application approach, electronic commerce applications, GA principles, negotiating agents, genetic algorithms, electronic commerce, finite state machines, automated negotiations, negotiation strategy
35	Gitanjali Swamy, Robert K. Brayton, Vigyan Singhal	Incremental methods for FSM traversal.	ICCD	1995	DBLP DOI BibTeX RDF	FSM traversal, formal verification, formal verification, finite state machines, finite state machine, logic design, directed graphs, logic CAD, incremental algorithms, digital systems, reachable states, incremental methods
28	Guy-Vincent Jourdan, Hasan Ural, Hüsnü Yenigün, Dong Zhu	Using a SAT solver to generate checking sequences.	ISCIS	2009	DBLP DOI BibTeX RDF
28	Baris Özkan, Onur Demirörs	Formalization Studies in Functional Size Measurement: How Do They Help?	IWSM/Mensura	2009	DBLP DOI BibTeX RDF	Software Functional Size Measurement, Functional Size Measurement Methods, Formalization, Software Models
28	John R. Rankin, Sandra Sampayo Vargas	FPS Extensions Modelling ESGs.	ACHI	2009	DBLP DOI BibTeX RDF