Search results for "Fanout"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
128	Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng	Simple tree-construction heuristics for the fanout problem .	ICCD	1995	DBLP DOI BibTeX RDF	tree-construction heuristics, fanout problem, fanout delay, buffer fanout trees, technology mapped network, gate-transformation, LT-tree construction technique, delays, combinational circuits, trees (mathematics), critical paths, logical functions
121	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using MTCMOS and multi-Vt techniques.	ISLPED	2006	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
121	Irith Pomeranz, Zvi Kohavi	The minimum test set problem for circuits with nonreconvergent fanout.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	minimum test set size problem, nonreconvergent fanout circuits, restricted fanout circuits, Labeling algorithms
117	Kanwar Jit Singh, Alberto L. Sangiovanni-Vincentelli	A Heuristic Algorithm for the Fanout Problem.	DAC	1990	DBLP DOI BibTeX RDF
113	David S. Kung 0001	A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
109	Shiy Xu, E. Edirisuriya	A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF	Fanout branch, Reconvergence, Testability, Testable Design, Fanout
106	John P. Hayes	Enumeration of Fanout-Free Boolean Functions.	J. ACM	1976	DBLP DOI BibTeX RDF
97	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using multiple threshold voltage inverters.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
94	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
82	Satish Verma, Wei Tsang Ooi	Controlling Gossip Protocol Infection Pattern Using Adaptive Fanout.	ICDCS	2005	DBLP DOI BibTeX RDF
82	Rajeev Murgai	Efficient global fanout optimization algorithms.	ASP-DAC	2001	DBLP DOI BibTeX RDF
82	Pasquale Cocchini, Massoud Pedram	Fanout optimization using bipolar LT-trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
82	Rajeev Murgai	On the global fanout optimization problem.	ICCAD	1999	DBLP DOI BibTeX RDF
78	Tsung-Lin Lee, Chun-Yao Wang	Recognition of Fanout-free Functions.	ASP-DAC	2007	DBLP DOI BibTeX RDF	state of the art method, fanout free functions, equivalent function, Boolean function, factoring, logic minimization
70	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	transition delay and path delay faults, statistical delay fault analysis, fault detectabilities, fault coverage, random patterns
70	Yang Wang 0014, Hung Q. Ngo 0001, Xiaohong Jiang 0001	Strictly Nonblocking Function-Cast d-Ary Multi-Log Networks under Fanout and Crosstalk Constraints.	ICC	2008	DBLP DOI BibTeX RDF
70	Peyman Rezvani, Massoud Pedram	A fanout optimization algorithm based on the effort delay model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
66	Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen, Beyin Chen	Fanout fault analysis for digital logic circuits.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	fanout fault analysis, digital logic circuits, combinational benchmark circuits, sequential benchmark circuits, target faults, fault diagnosis, logic testing, test generation, sequential circuits, combinational circuits, fault simulation, fault collapsing
62	Zaifu Zhang, Robert D. McLeod, Gregory E. Bridges	Statistical estimation of delay fault detectabilities and fault grading.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	delay fault detectabilities, fault grading, STAFAN, transition observabilities, fanout stems, fanout free region, gate line transition controllabilities, VLSI, fault diagnosis, logic testing, logic testing, statistical analysis, fault coverage, benchmark circuits, statistical estimation
59	Qiushuang Zhang, Ian G. Harris	Partial BIST insertion to eliminate data correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
59	Qiushuang Zhang, Ian G. Harris	Partial BIST insertion to eliminate data correlation.	ICCAD	1999	DBLP DOI BibTeX RDF
59	Qinghua Liu, Malgorzata Marek-Sadowska	Wire length prediction-based technology mapping and fanout optimization.	ISPD	2005	DBLP DOI BibTeX RDF	prediction, congestion, wire length
59	Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.	ITC	2002	DBLP DOI BibTeX RDF
59	Matthew M. Ziegler, Mircea Stan	Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
59	Abdel Aziz Farrag, Robert J. Dawson, Qi Yao	On Designing Fault-Tolerant Extensions With Optimal Fanout For Complete Bipartite Networks.	PARLE	1992	DBLP DOI BibTeX RDF
55	Xinmiao Zhang, Keshab K. Parhi	High-speed architectures for parallel long BCH encoders.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BCH, critical loop, iteration bound, parallel processing, encoder, linear feedback shift register, retiming, unfolding, fanout, generator polynomial
54	Haikun Zhu, Yi Zhu 0002, Chung-Kuan Cheng, David M. Harris	An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization.	ASP-DAC	2007	DBLP DOI BibTeX RDF	64 bit, interconnect-centric approach, fanout splitting, cell order optimization, logarithmic cyclic shifter design, demultiplexers, shifting path, nonshifting paths, accumulated wire load, switching probabilities, integer linear programming
54	Man-Fai Yu, Wayne Wei-Ming Dai	Single-layer fanout routing and routability analysis for Ball Grid Arrays.	ICCAD	1995	DBLP DOI BibTeX RDF	package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability
47	Balakrishnan Krishnamurthy	A Dynamic Programming Approach to the Test Point Insertion Problem.	DAC	1987	DBLP DOI BibTeX RDF
47	Anand Pappu, Alyssa B. Apsel	Demonstration of latency reduction in electrical interconnections using optical fanout.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Nikolai Ryzhenko, Oleg Venger	A practical repeater insertion flow.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	physical design, buffer insertion, fanout optimization, topology generation
43	Tsutomu Sasao, Kozo Kinoshita	On the Number of Fanout-Free Functions and Unate Cascade Functions.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	disjunctive networks, enumeration of equivalence classes, enumeration of switching functions, fanout-free function, Cascade, threshold function, unate function
43	Edward A. Bender, Jon T. Butler	Asymptotic Aproximations for the Number of Fanout-Free Functions.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	fanout-free networks, function enumeration, switching functions, cascades, Asymptotic approximations, combinatorial logic
35	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
35	Zhong-Zhen Wu, Shih-Chieh Chang	Multiple wire reconnections based on implication flow graph.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG)
35	H. V. Jagadish, Beng Chin Ooi, Kian-Lee Tan, Quang Hieu Vu, Rong Zhang 0002	Speeding up search in peer-to-peer networks with a multi-way tree structure.	SIGMOD Conference	2006	DBLP DOI BibTeX RDF	multi-way tree structure, peer-to-peer, system architecture
35	Xinmiao Zhang, Keshab K. Parhi	High-Speed Architectures for Parallel Long BCH Encoders.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
35	Miroslav N. Velev	Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors.	DATE	2004	DBLP DOI BibTeX RDF
35	Aiguo Lu, Guenter Stenz, Frank M. Johannes	Technology Mapping for Minimizing Gate and Routing Area.	DATE	1998	DBLP DOI BibTeX RDF	Routing, Technology Mapping, Area Optimization
35	Michael G. McNamer, H. Troy Nagle	ITA: An algorithm for IDDQ testability analysis.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	integrated circuit testing, testability analysis, I DDQ testing, leakage faults
35	Rajendra V. Boppana, Rajesh Boppana, Suresh Chalasani	Designing SANs to Support Low-Fanout Multicasts.	HiPC	2003	DBLP DOI BibTeX RDF
35	I-Min Liu, Adnan Aziz	Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing.	ICCD	2000	DBLP DOI BibTeX RDF
35	Wen-Ben Jone, Patrick H. Madden	Multiple fault testing using minimal single fault test set for fanout-free circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
35	Uwe Hinsberger, Reiner Kolla	A cell-based approach to performance optimization of fanout-free circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
31	Narendra K. Singhal, Laxman H. Sahasrabuddhe, Biswanath Mukherjee	Optimal multicasting of multiple light-trees of different bandwidth granularities in a WDM mesh network with sparse splitting capabilities.	IEEE/ACM Trans. Netw.	2006	DBLP DOI BibTeX RDF	light-tree, mixed integar linear program (MILP), optical crossconnect, optical crossconnect (OXC), splitter fanout, optimization, multicasting, optical network, mesh network, wavelength-division multiplexing (WDM), lightpath, grooming
31	Glenn Jennings	Accurate ternary-valued compiled logic simulation of complex logic networks by OTDD composition.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	circuit diagrams, ternary-valued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletely-specified functions
31	Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell	Statistical methods for delay fault coverage analysis.	VLSI Design	1995	DBLP DOI BibTeX RDF	delay fault coverage analysis, true value simulation, multi-value logic system, implicit random path sampling procedure, linear-time estimate, fault coverage estimates, longest path theorem, fanout branches, fault diagnosis, logic testing, delays, probability, statistical analysis, observabilities, multivalued logic, propagation delay, detection probabilities, statistical techniques, transition probabilities
31	Joydeep Ghosh, Sajal K. Das 0001, Ajita John	Concurrent Processing of Linearly Ordered Data Structures on Hypercube Multicomputers.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	concurrentprocessing, linearly ordered data structures, concurrentmanipulation, augmented binomial search tree, pruned binomial tree, arbitrary processor node, consecutive nodes, nonoverlappingprocessor lists, intermediate-levelimage processing algorithms, dictionary operations, low-level image processingalgorithms, Gray code embedding, distributed memorymulticomputers, parallel algorithms, parallel programming, broadcast, hypercube networks, trees (mathematics), distributed memory systems, search problems, merge, tree data structures, search trees, k-ary n-cubes, concurrent data structure, hypercube multicomputers, local information, fanout, hypercube systems
23	Adam Silberstein, Jeff Terrace, Brian F. Cooper, Raghu Ramakrishnan 0001	Feeding frenzy: selectively materializing users' event feeds.	SIGMOD Conference	2010	DBLP DOI BibTeX RDF	social networks, view maintenance
23	Michael Scheutzow, Martin Reisslein, Martin Maier 0001, Patrick Seeling	Multicast Capacity of Packet-Switched Ring WDM Networks.	IEEE Trans. Inf. Theory	2008	DBLP DOI BibTeX RDF
23	Gregory V. Chockler, Roie Melamed, Yoav Tock, Roman Vitenberg	Constructing scalable overlays for pub-sub with many topics.	PODC	2007	DBLP DOI BibTeX RDF	peer-to-peer, overlay networks, optimization problems, application-level multicast, pub/sub
23	Stephen J. Hegner	The complexity of embedded axiomatization for a class of closed database views.	Ann. Math. Artif. Intell.	2006	DBLP DOI BibTeX RDF	complexity, database, view
23	Michael Scheutzow, Patrick Seeling, Martin Maier 0001, Martin Reisslein	Multicast capacity of packet-switched ring WDM networks.	INFOCOM	2005	DBLP DOI BibTeX RDF
23	Miroslav N. Velev	Efficient translation of boolean formulas to CNF in formal verification of microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
23	Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu	Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
23	Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On per-test fault diagnosis using the X-fault model.	ICCAD	2004	DBLP DOI BibTeX RDF
23	Shrirang K. Karandikar, Sachin S. Sapatnekar	Logical effort based technology mapping.	ICCAD	2004	DBLP DOI BibTeX RDF
23	Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal	Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test.	ISVLSI	2003	DBLP DOI BibTeX RDF
23	Randy Huang, John Wawrzynek, André DeHon	Stochastic, spatial routing for hypergraphs, trees, and meshes.	FPGA	2003	DBLP DOI BibTeX RDF	spatial routing, FPGA, reconfigurable computing, detail routing
23	Guy G. Lemieux, David M. Lewis	Circuit design of routing switches.	FPGA	2002	DBLP DOI BibTeX RDF
23	Alexandre F. Tenca, Syed Ubaid Hussaini	A Design of Radix-2 On-line Division Using LSA Organization.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
23	Jason Cong, Kenneth Yan	Synthesis for FPGAs with embedded memory blocks.	FPGA	2000	DBLP DOI BibTeX RDF
23	Haluk Konuk	Voltage- and current-based fault simulation for interconnect open defects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
23	Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu 0001	Logic Transformation for Low Power Synthesis.	DATE	1999	DBLP DOI BibTeX RDF
23	Priyank Kalla, Maciej J. Ciesielski	Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence.	DATE	1999	DBLP DOI BibTeX RDF
23	Anurag Acharya 0001, Huican Zhu, Kai Shen	Adaptive Algorithms for Cache-Efficient Trie Search.	ALENEX	1999	DBLP DOI BibTeX RDF
23	Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury	A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis.	VLSI Design	1999	DBLP DOI BibTeX RDF	spice verification, primary-path, secondary-path, timing analysis, assertion, assertibility
23	Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell	A Complete Characterization of Path Delay Faults through Stuck-at Faults.	VLSI Design	1999	DBLP DOI BibTeX RDF
23	S. Turgis, Daniel Auvergne	A novel macromodel for power estimation in CMOS structures.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	Daniel R. Brasen, Gabriele Saucier	Using cone structures for circuit partitioning into FPGA packages.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance	A Novel Predictable Segmented FPGA Routing Architecture.	FPGA	1998	DBLP DOI BibTeX RDF	FPGA, routing, programmable logic
23	Jason Cong, Songjie Xu	Technology Mapping for FPGAs with Embedded Memory Blocks.	FPGA	1998	DBLP DOI BibTeX RDF
23	Dirk Stroobandt, Jan Van Campenhout	Hierarchical Test Generation with Built-In Fault Diagnosis.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	Hierarchical Test Pattern Generation, Fault Diagnosis, Test Compaction
23	Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage	RC interconnect synthesis-a moment fitting approach.	ICCAD	1994	DBLP DOI BibTeX RDF
23	Fadi Maamari, Janusz Rajski	The dynamic reduction of fault simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj	Switch-level timing simulation of bipolar ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
23	Warren H. Debany Jr., Carlos R. P. Hartmann	Bounds on the sizes of irredundant test sets and sequences for combinational logic networks.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	Digital logic testing, irredundant tests, test complexity, test counting
23	Jwu E. Chen, Chung-Len Lee 0001, Wen-Zen Shen	Checkpoints in irredundant two-level combinational circuits.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF
23	Sujit Dey, Franc Brglez, Gershon Kedem	Corolla Based Circuit Partitioning and Resynthesis.	DAC	1990	DBLP DOI BibTeX RDF
23	Sreejit Chakravarty	On the complexity of computing tests for CMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
23	Danny C. C. Ko, Melvin A. Breuer	The design of self-checking multi-output combinational circuits.	AFIPS National Computer Conference	1977	DBLP DOI BibTeX RDF
23	Esfandiar Esmaieli, Ali Peiravi, Yasser Sedaghat	An Effective Fanout-Based Method for Improving Error Propagation Probability Estimation in Combinational Circuits.	IEEE Access	2024	DBLP DOI BibTeX RDF
23	Dewmini Sudara Marakkalage, Giovanni De Micheli	Fanout-Bounded Logic Synthesis for Emerging Technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2024	DBLP DOI BibTeX RDF
23	Stephen A. Fenner, Rabins Wosti	Implementing the quantum fanout operation with simple pairwise interactions.	Quantum Inf. Comput.	2023	DBLP DOI BibTeX RDF
23	Dewmini Sudara Marakkalage, Giovanni De Micheli	Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach.	DATE	2023	DBLP DOI BibTeX RDF
23	Haiyun Li, Jixin Zhang, Ning Xu 0006, Mingyu Liu	FanoutNet: A Neuralized PCB Fanout Automation Method Using Deep Reinforcement Learning.	AAAI	2023	DBLP DOI BibTeX RDF
23	Raja Swaminathan, Michael J. Schulte, Brett Wilkerson, Gabriel H. Loh, Alan Smith, Norman James	AMD InstinctTM MI250X Accelerator enabled by Elevated Fanout Bridge Advanced Packaging Architecture.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
23	Masanori Takahashi, Tsubasa Sasaki, Ryuichi Sugizaki, Yoshihiro Arashitani	4-Core Fiber Narrow Pitch Fanout Comprised of Tapered High-Δ MCF.	OFC	2023	DBLP DOI BibTeX RDF
23	Xuliang Zhu, Ruofei Tang, Lei Chen 0002, Xing Li, Xin Huang, Mingxuan Yuan, Weihua Sheng, Jianliang Xu	A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting.	DAC	2023	DBLP DOI BibTeX RDF
23	Jim Plusquellic	Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA.	Cryptogr.	2022	DBLP DOI BibTeX RDF
23	Stephen A. Fenner, Rabins Wosti	Implementing the fanout operation with simple pairwise interactions.	CoRR	2022	DBLP DOI BibTeX RDF
23	Nafis Irtija, Eirini-Eleni Tsiropoulou, Cyrus Minwalla, Jim Plusquellic	True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF.	HOST	2022	DBLP DOI BibTeX RDF
23	M. Rahimi, M. B. Ghaznavi-Ghoushchi	A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
23	Andrew Y. Guo, Abhinav Deshpande, Su-Kuan Chu, Zachary Eldredge, Przemyslaw Bienias, Dhruv Devulapalli, Yuan Su, Andrew M. Childs, Alexey V. Gorshkov	Implementing a Fast Unbounded Quantum Fanout Gate Using Power-Law Interactions.	CoRR	2020	DBLP BibTeX RDF
23	V. I. Kopp, J. Park, J. Singer, Dan Neugroschl, Andy Gillooly	Low Return Loss Multicore Fiber-Fanout Assembly for SDM and Sensing Applications.	OFC	2020	DBLP BibTeX RDF
23	Maxim Ladnushkin	Flip-flops fanout splitting in scan designs.	ITC	2020	DBLP DOI BibTeX RDF
23	Shungeng Zhang, Qingyang Wang 0001, Yasuhiko Kanemasa, Jianshu Liu, Calton Pu	DoubleFaceAD: A New Datastore Driver Architecture to Optimize Fanout Query Performance.	Middleware	2020	DBLP DOI BibTeX RDF
23	He-Teng Zhang, Jie-Hong R. Jiang	SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies.	DAC	2020	DBLP DOI BibTeX RDF
23	Md. Adnan Zaman, Srinivas Katkoori	Minimizing Performance and Energy Overheads Due to Fanout In Memristor based Logic Implementations.	VLSI-SoC	2018	DBLP DOI BibTeX RDF
23	Md. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori	Optimizing Performance and Energy Overheads Due to Fanout in In-Memory Computing Systems.	VLSI-SoC (Selected Papers)	2018	DBLP DOI BibTeX RDF