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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 105 occurrences of 78 keywords
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Results
Found 120 publication records. Showing 120 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
116 | Michael Theobald, Steven M. Nowick |
An Implicit Method for Hazard-Free Two-Level Logic Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 58-69, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
hazard-free, two-level, dynamic-hazard-free prime implicants, asynchronous, BDD, logic minimization, implicit |
105 | Steven M. Nowick, Charles W. O'Donnell |
On the Existence of Hazard-Free Multi-Level Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada, pp. 109-120, 2003, IEEE Computer Society, 0-7695-1898-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
88 | Kurt Keutzer, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli |
Synthesis for testability techniques for asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12), pp. 1569-1577, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
82 | Bill Lin 0001, Srinivas Devadas |
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8), pp. 974-985, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
77 | Michael Theobald, Steven M. Nowick |
Fast heuristic and exact algorithms for two-level hazard-free logic minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(11), pp. 1130-1147, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
68 | Adit D. Singh, Gefu Xu |
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 349-357, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Hazard-Free, Test, Delay, Transition |
68 | J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren |
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 749-754, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
exact minimization, two-level minimization, hazard free logic, divide and conquer, asynchronous logic |
68 | Ajay Khoche, Erik Brunvand |
Critical hazard free test generation for asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 203-209, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
self-timed control circuits, critical hazard-free tests, six-valued algebra, macro-module library, partial scan based DFT environment, unbounded delay model, asynchronous circuits, asynchronous circuits, D-algorithm |
68 | U. K. Bhattacharyya, Idranil Sen Gupta, S. Shyama Nath, P. Dutta |
PLA based synthesis and testing of hazard free logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 121-124, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions |
65 | Feng Shi |
Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 640-645, 2008, IEEE Computer Society, 978-1-4244-2657-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
65 | Steven M. Nowick, David L. Dill |
Exact two-level minimization of hazard-free logic with multiple-input changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8), pp. 986-997, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
63 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 171-176, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions |
58 | Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick |
Algorithms for the optimal state assignment of asynchronous state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 59-75, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimal state assignment, asynchronous state machines, state codes, race-free state assignment, hazard-free state assignment, input encoding problem, sum-of-products implementations, finite state machines, asynchronous circuits, state assignment, minimisation of switching nets, hazards and race conditions, asynchronous sequential logic |
55 | Chris J. Myers, Hans M. Jacobson |
Efficient Exact Two-Level Hazard-Free Logic Minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 64-73, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
55 | Tam-Anh Chu |
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 61-84, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
52 | Hans M. Jacobson, Chris J. Myers |
Efficient algorithms for exact two-level hazard-free logic minimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11), pp. 1269-1283, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
45 | Robert M. Fuhrer, Bill Lin 0001, Steven M. Nowick |
Symbolic hazard-free minimization and encoding of asynchronous finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 604-611, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimal state assignment, asynchronous state machines, hazards, sequential synthesis, sequential optimization |
45 | Bill Lin 0001, Srinivas Devadas |
Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 542-549, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
43 | Tatsuo Higuchi 0001, Michitaka Kameyama |
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(12), pp. 1212-1221, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting |
42 | Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger |
On Hazard-free Patterns for Fine-delay Fault Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 213-222, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
42 | Kenneth Y. Yun, David L. Dill |
Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2), pp. 101-117, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
42 | Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev |
Hazard-free implementation of speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9), pp. 749-771, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
42 | Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli |
Synthesis of hazard-free asynchronous circuits with bounded wire delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 61-86, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
42 | Cho W. Moon, Paul R. Stephan, Robert K. Brayton |
Specification, synthesis, and verification of hazard-free asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 7(1-2), pp. 85-100, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
40 | Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin 0001 |
Externally hazard-free implementations of asynchronous control circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8), pp. 835-848, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev |
Design and Analysis of Dual-Rail Circuits for Security Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(4), pp. 449-460, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Alternating spacer protocol, dual-rail encoding, hazard-free design, cryptography, power analysis, design automation, hardware security |
38 | Wen Ching Wu, Chung-Len Lee 0001, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir |
Oscillation Ring Delay Test for High Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 16(1-2), pp. 147-155, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
oscillation ring testing, sensitized path, robust path dealy fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines, stuck at fault, delay fault testing, gate delay fault |
38 | Hon Fung Li, P. N. Lam |
A protocol extraction strategy for control point insertion in design for test of transition signaling circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 178-183, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
protocol extraction strategy, control point insertion, transition signaling circuits, hazard-free test, safe behaviors, gap detection, gap matching, single input pad, protocols, logic testing, design for testability, asynchronous circuits, asynchronous circuits, design for test, test length, area overhead |
38 | Imtiaz P. Shaik, Michael L. Bushnell |
A graph approach to DFT hardware placement for robust delay fault BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 177-182, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
graph heuristic, DFT hardware placement, robust delay fault BIST, ULSI circuit, built-in self-testing model, design for testability hardware, hazard free structure, graph theory, logic testing, delays, built-in self test, integrated circuit testing, design for testability, fault location, digital integrated circuits, ULSI |
38 | Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng |
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12), pp. 1514-1521, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
38 | Sunil D. Sherlekar, P. S. Subramanian |
Conditionally robust two-pattern tests and CMOS design for testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3), pp. 325-332, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
35 | Sobeeh Almukhaizim, Yiorgos Makris |
Concurrent Error Detection in Asynchronous Burst-Mode Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1272-1277, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
30 | Eric Senn, Bertrand Y. Zavidovique |
Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 22(3), pp. 197-215, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau |
Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 185-188, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
28 | Kenneth Y. Yun, David L. Dill |
Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2), pp. 118-132, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
26 | Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton |
Generalized Sensitization using Fault Tuples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 297-303, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiple path sensitization, hazard-free test, fault model, Fault simulation, robust test |
26 | Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, Pei-Chuan Yeh |
Estimation and bounding of energy consumption in burst-mode control circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 26-33, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
statistical energy estimation, hazard-free logic, N-valued simulation, low power design, asynchronous circuits |
25 | Kenneth Y. Yun, Bill Lin 0001, David L. Dill, Srinivas Devadas |
BDD-based synthesis of extended burst-mode controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9), pp. 782-792, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
25 | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
On variable clock methods for path delay testing of sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11), pp. 1237-1249, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
25 | Teresa H.-Y. Meng, Robert W. Brodersen, David G. Messerschmitt |
Automatic synthesis of asynchronous circuits from high-level specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(11), pp. 1185-1205, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
22 | Sobeeh Almukhaizim, Yiorgos Makris |
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(6), pp. 785-798, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
asynchronous burst-mode machines, error-detecting codes, Concurrent error detection, Berger code |
17 | Christian Ikenmeyer, Balagopal Komarath, Nitin Saurabh |
Karchmer-Wigderson Games for Hazard-Free Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCS ![In: 14th Innovations in Theoretical Computer Science Conference, ITCS 2023, January 10-13, 2023, MIT, Cambridge, Massachusetts, USA., pp. 74:1-74:25, 2023, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-263-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
17 | Johannes Bund, Christoph Lenzen 0001, Moti Medina |
Small Hazard-Free Transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCS ![In: 13th Innovations in Theoretical Computer Science Conference, ITCS 2022, January 31 - February 3, 2022, Berkeley, CA, USA., pp. 32:1-32:24, 2022, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 978-3-95977-217-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
17 | Johannes Bund |
Hazard-free clock synchronization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2022 |
RDF |
|
17 | Stasys Jukna |
Notes on Hazard-Free Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIAM J. Discret. Math. ![In: SIAM J. Discret. Math. 35(2), pp. 770-787, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Christian Ikenmeyer, Balagopal Komarath, Nitin Saurabh |
Karchmer-Wigderson Games for Hazard-free Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR21, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
17 | Christian Ikenmeyer, Balagopal Komarath, Nitin Saurabh |
Karchmer-Wigderson Games for Hazard-free Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2107.05128, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
17 | Alexander Kushnerov, Moti Medina, Alexandre Yakovlev |
Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021, Beijing, China, September 7-10, 2021, pp. 17-24, 2021, IEEE, 978-1-7281-4132-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
17 | Stasys Jukna |
Notes on Hazard-Free Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. Colloquium Comput. Complex. ![In: Electron. Colloquium Comput. Complex. TR20, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
17 | Stasys Jukna |
Notes on Hazard-Free Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2012.10976, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
17 | Ankit Shah, Raman Nayyar, Arani Sinha |
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 37(4), pp. 7-13, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
17 | Christian Ikenmeyer, Balagopal Komarath, Christoph Lenzen 0001, Vladimir Lysikov, Andrey Mokhov, Karteek Sreenivasaiah |
On the Complexity of Hazard-free Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 66(4), pp. 25:1-25:20, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
17 | Ankit Shah, Raman Nayyar, Arani Sinha |
Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-1170-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
17 | Johannes Bund, Christoph Lenzen 0001, Moti Medina |
Small Hazard-free Transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1811.12369, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
17 | Christian Ikenmeyer, Balagopal Komarath, Christoph Lenzen 0001, Vladimir Lysikov, Andrey Mokhov, Karteek Sreenivasaiah |
On the complexity of hazard-free circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 50th Annual ACM SIGACT Symposium on Theory of Computing, STOC 2018, Los Angeles, CA, USA, June 25-29, 2018, pp. 878-889, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
17 | Christian Ikenmeyer, Balagopal Komarath, Christoph Lenzen 0001, Vladimir Lysikov, Andrey Mokhov, Karteek Sreenivasaiah |
On the complexity of hazard-free circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1711.01904, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
17 | Sobeeh Almukhaizim, Ozgur Sinanoglu |
Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 5(4), pp. 306-315, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
17 | Cuong Pham-Quoc, Anh-Vu Dinh-Duc |
Hazard-free Muller Gates for Implementing Asynchronous Circuits on Xilinx FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Fifth IEEE International Symposium on Electronic Design, Test & Applications, DELTA 2010, Ho Chi Minh City, Vietnam, January 13-15, 2010, pp. 289-292, 2010, IEEE Computer Society, 978-0-7695-3978-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
17 | Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci |
Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2009, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci |
Reply to "Comments on Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes". ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2009, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Kiran K. Gunnam, Gwan S. Choi, Mark B. Yeary |
Comments on "Techniques and Architectures for Hazard-Free Semi-Parallel Decoding of LDPC Codes". ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURASIP J. Embed. Syst. ![In: EURASIP J. Embed. Syst. 2009, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Mohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi |
A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece, pp. 61-66, 2009, IEEE Computer Society, 978-0-7695-3782-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal |
Output Hazard-Free Transition Delay Fault Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA, pp. 97-102, 2009, IEEE Computer Society, 978-0-7695-3598-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Bassam Jamil Mohd, Adnan Aziz, Earl E. Swartzlander Jr. |
The hazard-free superscalar pipeline fast fourier transform algorithm and architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 194-199, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz |
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC (Selected Papers) ![In: VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA, pp. 1-22, 2007, Springer, 978-0-387-93845-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Wayne D. Grover |
Globally optimal distributed synchronous batch reconfiguration for efficient hazard-free dynamic provisioning: How an entire network can "think globally and act locally". ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRCN ![In: 6th International Workshop on Design and Reliable Communication Networks, DRCN 2007, La Rochelle, France, October 7-10, 2007, pp. 1-8, 2007, IEEE, 978-1-4244-3824-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Lei Zhang 0033, Zhiping Yu, Xiangqing He |
Hazard Free Sawtooth Oscillator and Its Application in Ultra Low Current Monitoring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 252-255, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Eric Senn, Pietro Perona |
Hazard-free self-timed design: methodology and application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. Comput. Aided Eng. ![In: Integr. Comput. Aided Eng. 7(3), pp. 229-242, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan |
Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000, San Jose, California, USA, November 5-9, 2000, pp. 303-310, 2000, IEEE Computer Society, 0-7803-6448-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | J. W. J. M. Rutten, Michel R. C. M. Berkelaar |
Efficient exact and heuristic minimization of hazard-free logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 152-159, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
17 | Martijn De Boer, A. Gröpl, Jürgen Hesser, Reinhard Männer |
Latency- and hazard-free volume memory architecture for direct volume rendering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Graph. ![In: Comput. Graph. 21(2), pp. 179-187, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Kuan-Jen Lin, Chi-Wen Kuo, Chen-Shang Lin |
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 46(11), pp. 1246-1263, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
hazard-freeness, characteristic graph, exact optimization, Asynchronous circuit, signal transition graph |
17 | Jennifer E. Walter, Jennifer L. Welch |
Hazard-Free Connection Release. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDPTA ![In: Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 1997, June 30 - July 3, 1997, Las Vegas, Nevada, USA, pp. 1668-1672, 1997, CSREA Press, 0-9648666-8-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP BibTeX RDF |
|
17 | Martijn De Boer, A. Gröpl, Jürgen Hesser, Reinhard Männer |
Latency- and Hazard-Free Volume Memory Ar chitecture for Direct Volume Rendering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Workshop on Graphics Hardware ![In: EGGH96: Eurographics Workshop on Graphics Hardware 1996, pp. 109-119, 1996, The Eurographics Association. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Prabhakar Kudva, Ganesh Gopalakrishnan, Hans M. Jacobson, Steven M. Nowick |
Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 77-82, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Michael Theobald, Steven M. Nowick, Tao Wu |
Espresso-HF: A Heuristic Hazard-Free Minimizer for Two-Level Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 33st Conference on Design Automation, Las Vegas, Nevada, USA, Las Vegas Convention Center, June 3-7, 1996., pp. 71-76, 1996, ACM Press, 0-89791-779-0. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
17 | Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev |
On hazard-free implementation of speed-independent circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995, 1995, ACM, 0-89791-766-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Milton H. Sawasaki, Chantal Ykman-Couvreur, Bill Lin 0001 |
Externally Hazard-Free Implementations of Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995., pp. 718-724, 1995, ACM Press, 0-89791-725-1. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Md. Mozammel Huq Azad Khan |
An Algorithm for Hazard-Free Minimization of Incompletely Specified Switching Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Process. Lett. ![In: Inf. Process. Lett. 52(1), pp. 23-29, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Radhakrishna Nagalla, Graham R. Hellestrand |
Signal Transition Graph Constraints for Synthesis of Hazard-Free Asynchronous Circuits with Unbounded-Gate Delays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Formal Methods Syst. Des. ![In: Formal Methods Syst. Des. 5(3), pp. 245-273, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin |
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EDAC-ETC-EUROASIC ![In: EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, pp. 178-183, 1994, IEEE Computer Society, 0-8186-5410-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Enric Pastor, Jordi Cortadella |
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, pp. 250-254, 1993, IEEE Computer Society / ACM, 0-8186-4490-7. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Tam Anh Chu |
On the Specification and Synthesis of Hazard-free Asynchronous Control Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 1495-1498, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
17 | Alexandre Yakovlev |
Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 21-24, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
17 | Meng-Lin Yu, P. A. Subrahmanyam |
Hazard-Free Asynchronous Circuit Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asynchronous Design Methodologies ![In: Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993, pp. 87-105, 1993, North-Holland, 0-444-81599-6. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
17 | Michael J. Bryan, Srinivas Devadas, Kurt Keutzer |
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6), pp. 800-803, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Steven M. Nowick, David L. Dill |
Exact two-level minimization of hazard-free logic with multiple-input changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1992 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1992, Santa Clara, CA, USA, November 8-12, 1992. Digest of Technical Papers, pp. 626-630, 1992, IEEE Computer Society / ACM, 0-8186-3010-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Tam-Anh Chu |
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 407-413, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
17 | Cho W. Moon, Paul R. Stephan, Robert K. Brayton |
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 322-325, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Luciano Lavagno, Kurt Keutzer, Alberto L. Sangiovanni-Vincentelli |
Algorithms for Synthesis of Hazard-Free Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 28th Design Automation Conference, San Francisco, California, USA, June 17-21, 1991., pp. 302-308, 1991, ACM, 0-89791395-7. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
17 | Eskil Kjelkerud, Owe Thessén |
Generation of hazard free tests using the D-algorithm in a timing accurate system for logic and deductive fault simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 16th Design Automation Conference, DAC '79, San Diego, California, USA, June 25-27, 1979, pp. 180-184, 1979, ACM. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP BibTeX RDF |
|
17 | Jon G. Bredeson |
On Multiple Input Change Hazard-Free Combinatorial Switching Circuits without Feedback ![Search on Bibsonomy](Pics/bibsonomy.png) |
SWAT ![In: 14th Annual Symposium on Switching and Automata Theory, Iowa City, Iowa, USA, October 15-17, 1973, pp. 56-63, 1973, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
17 | David A. Huffman |
The Design and Use of Hazard-Free Switching Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 4(1), pp. 47-62, 1957. The full citation details ...](Pics/full.jpeg) |
1957 |
DBLP DOI BibTeX RDF |
|
15 | A. P. Shanthi, L. Karthik Singaram, Ranjani Parthasarathi |
Evolution of Asynchronous Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Evolvable Hardware ![In: 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June - 1 July 2005, Washington, DC, USA, pp. 93-96, 2005, IEEE Computer Society, 0-7695-2399-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Robert M. Senger, Eric D. Marsman, Gordy A. Carichner, Sundus Kubba, Michael S. McCorquodale, Richard B. Brown |
Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Jung-Lin Yang, Hsu-Ching Tien, Chia-Ming Hsu, Sung-Min Lin |
High-Level Synthesis for Self-Timed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1410-1413, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
13 | Nikolai Starodoubtsev, Sergei Bystrov |
Behavior and Synthesis of Two-Input Gate Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA, pp. 190-200, 2005, IEEE Computer Society, 0-7695-2305-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
13 | Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang |
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005, pp. 56-61, 2005, ACM. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
burst-mode, automatic synthesis, hazard, asynchronous logic, speed-independent |
13 | Ivan Blunno, Luciano Lavagno |
Designing an asynchronous microcontroller using Pipefitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(7), pp. 696-699, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov, Alexandre Yakovlev |
Improving the Security of Dual-Rail Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11-13, 2004. Proceedings, pp. 282-297, 2004, Springer, 3-540-22666-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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