Search results for "LVDS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
149	Magnus Eckersand, Fredrik Franzon, Ken Filliter	Using At-Speed BIST to Test LVDS Serializer/Deserializer Function.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	LVDS, BIST, differential, At-speed
83	Carlos Zamarreño-Ramos, Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	LVDS interface for AER links with burst mode operation capability.	ISCAS	2008	DBLP DOI BibTeX RDF
83	Ming-Dou Ker, Chien-Hua Wu	Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications.	ISCAS	2006	DBLP DOI BibTeX RDF
66	Feng Zhang 0014, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu	A High Speed CMOS Transmitter and Rail-to-Rail Receiver.	DELTA	2008	DBLP DOI BibTeX RDF	LVDS rail-to-rail
63	Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona	LVDS Serial AER Link performance.	ISCAS	2007	DBLP DOI BibTeX RDF
63	Gunjan Mandal, Pradip Mandal	Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
63	Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo	Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
47	Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang	DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance.	J. Intell. Robotic Syst.	2008	DBLP DOI BibTeX RDF	M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint
44	Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu	LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.	ASP-DAC	2008	DBLP DOI BibTeX RDF
44	Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni	Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
39	Nidhir Kumar, Senthil N. Velu, Rajan Verma	Gateway to Chips: High Speed I/O Signalling and Interface.	VLSI Design	2008	DBLP DOI BibTeX RDF
39	Donald M. Chiarulli, Jason D. Bakos, Joel R. Martin, Steven P. Levitan	Area, power, and pin efficient bus transceiver using multi-bit-differential signaling.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
27	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
27	Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt	Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities.	VTS	2005	DBLP DOI BibTeX RDF	RapidIO, Source-Synchronous, LVDS, Differential, ATE, Non-determinism
27	G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman	Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models.	VLSI Design	2005	DBLP DOI BibTeX RDF	LVDS, DPbasic, Monotonic, IBIS
24	Nanditha Maragowdanahalli Shivalingaiah, Vijaya Prakash Anamanahalli Mariyappa	Performance Analysis of FinFET-Based LVDS I/O Receiver Architecture.	SN Comput. Sci.	2023	DBLP DOI BibTeX RDF
24	Akihiko Tsukahara, Sung-Gwi Cho, Keita Tanaka, Akihiko Homma, Yoshinori Uchikawa	Design and Trial Production FPGA based Stochastic Resonance Circuit Using LVDS and an Examination for Surface EMG Measurement.	SICE	2023	DBLP DOI BibTeX RDF
24	Alexandros D. Bechrakis Triantafyllos, Alexandra P. Mavropoulou, Anargyros T. Baklezos, Christos N. Capsalis, Christos D. Nikolopoulos	Towards the Prediction of SpaceWire Radiated Emissions Employing an LVDS Signal Emulator.	IEEE Access	2021	DBLP DOI BibTeX RDF
24	Jinrong Li, Jue Wang, Xu Cheng 0002, Yicheng Zeng, Xiaoyang Zeng	A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process.	ASICON	2021	DBLP DOI BibTeX RDF
24	Christos D. Nikolopoulos, Anargyros T. Baklezos, Stylianos Tsatalas, Christos N. Capsalis	Verification of Radiated Emissions Modeling for SpaceWire/LVDS Links Routed on CFRP Ground.	IEEE Trans. Aerosp. Electron. Syst.	2020	DBLP DOI BibTeX RDF
24	Seng Siong Lee, Lini Lee, Fabian Wai Lee Kung, Ahmed Saad, Harikrishnan Ramiah, Gim Heng Tan	A Low Power High Precision Trim-Less Envelope Detector for Fail-Safe Circuit in LVDS Receiver.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
24	Liang Xie 0004, Shunle Guo, Zhaoxi Li, Xiangliang Jin	A High Speed Rail-to-Rail Operational Amplifier with Constant-gm for LVDS Receiver.	ICCT	2020	DBLP DOI BibTeX RDF
24	Ning Qiao, Giacomo Indiveri	A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems.	CoRR	2019	DBLP BibTeX RDF
24	Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici	JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS.	PRIME	2019	DBLP DOI BibTeX RDF
24	Niraj Kumar Jha, Dishank Yadav, Anuj Maheshwari, Mrigank Sharad	Radiation Hardened High-Speed LVDS compliant Transceiver.	CONIELECOMP	2019	DBLP DOI BibTeX RDF
24	Pengfei Lang, Qingfeng Shi, Zebing Xie, Hongtao Zheng, Yan Zhao	Research on Intelligent Estimation Model of BER for High-Speed Image Transmission Based on LVDS Interface.	ADHIP (2)	2019	DBLP DOI BibTeX RDF
24	Seng Siong Lee, Lini Lee, Wai Lee Kung, Ahmed Saad, Gim Heng Tan	A fully integrated and high precision 350 mV amplitude regulated LVDS transmitter compensating PVT variations.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
24	Hanyang Xu, Jian Wang 0036, Jinmei Lai	Design of a power efficient self-adaptive LVDS driver.	IEICE Electron. Express	2018	DBLP DOI BibTeX RDF
24	Durga Prasanth Kumar Gavara, G. Shekar	Design of LVDS Transmitter with SLVDS mode for Low Power Applications in 55nm CMOS Technology.	ICACCI	2018	DBLP DOI BibTeX RDF
24	Srikanth Jagannathan, Kumar Abhishek, Nihaar N. Mahatme, Ender Yilmaz	Design of aging aware 5 Gbps LVDS transmitter for automotive applications.	IRPS	2018	DBLP DOI BibTeX RDF
24	Ning Qiao, Giacomo Indiveri	A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems.	ASYNC	2018	DBLP DOI BibTeX RDF
24	Gianluca Traversi, Francesco De Canio, Valentino Liberali, Alberto Stabile	Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition.	ISCAS	2018	DBLP DOI BibTeX RDF
24	Jayshree, G. Seetharaman	Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay.	AHS	2018	DBLP DOI BibTeX RDF
24	Wei Fan, Zhelu Li, Jianxiong Xi, Lenian He, Kexu Sun, Ning Xie	A 1.2 Gbps failsafe low jitter LVDS transmitter-receiver applied in CMOS image sensor.	MOCAST	2018	DBLP DOI BibTeX RDF
24	Syed Arsalan Jawed, Ali Asghar, Khubaib Khan, Shahbaz Abbasi, Muhammad Naveed 0004, Yasir Siddiqi, Waqas Siddiqi	A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control.	Int. J. Circuit Theory Appl.	2017	DBLP DOI BibTeX RDF
24	Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco	On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.	IEEE Trans. Biomed. Circuits Syst.	2017	DBLP DOI BibTeX RDF
24	Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco	Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.	ISCAS	2017	DBLP DOI BibTeX RDF
24	Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco	Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.	ISCAS	2017	DBLP DOI BibTeX RDF
24	Munish Malik, Ajay Kumar, H. S. Jatana	Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process.	VDAT	2017	DBLP DOI BibTeX RDF
24	Gianluca Traversi, Francesco De Canio, Valentino Liberali, Alberto Stabile	Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories.	MOCAST	2017	DBLP DOI BibTeX RDF
24	Jayshree, Seema Verma, Amitabh Chatterjee	A methodology for designing LVDS interface system.	ISED	2016	DBLP DOI BibTeX RDF
24	Luis Sanchez, Giancarlo Patino, Víctor Murray, James Lyke	Reduced power consumption in the FPGA-based Universal Link for LVDS communications.	LASCAS	2016	DBLP DOI BibTeX RDF
24	Giacomo Alberto Graceffa, Umberto Gatti, Cristiano Calligaro	A 400 Mbps radiation hardened by design LVDS compliant driver and receiver.	ICECS	2016	DBLP DOI BibTeX RDF
24	Yuan Su, Fan Ye 0001, Junyan Ren	A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
24	Luis Sanchez, Giancarlo Patino, Víctor Murray, James Lyke	Hardware implementation of a FPGA-based universal link for LVDS communications.	LASCAS	2015	DBLP DOI BibTeX RDF
24	Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye 0001, Junyan Ren	LVDS transmitter with optimized high power-efficiency 8: 1 MUX.	ASICON	2015	DBLP DOI BibTeX RDF
24	Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh	Methodology for optimizing ESD protection for high speed LVDS based I/Os.	VDAT	2015	DBLP DOI BibTeX RDF
24	Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim	An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
24	Sultan A. Alqarni, Ahmed K. Kamal	LVDS receiver with 7mW consumption at 1.5 Gbps.	ICM	2014	DBLP DOI BibTeX RDF
24	Benjamín T. Reyes, German Paulina, Lucas Tealdi, Emanuel Labat, Raul M. Sanchez, Pablo Sergio Mandolesi, Mario Rafael Hueda	A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system.	LASCAS	2014	DBLP DOI BibTeX RDF
24	Taras Iakymchuk, Alfredo Rosado, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno	An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links.	ISCAS	2014	DBLP DOI BibTeX RDF
24	Seng Siong Lee, Ahmed Saad, Lini Lee, Wai Lee Kung	On-chip slew-rate control for low-voltage differential signalling (LVDS) driver.	ISPACS	2014	DBLP DOI BibTeX RDF
24	Tadeusz Satlawa, Aleksandra Drozd, Piotr Kmon	Design of the ultrafast LVDS I/O interface in 40 nm CMOS process.	MIXDES	2014	DBLP DOI BibTeX RDF
24	Carlos Zamarreño-Ramos, Raghavendra Kulkarni, José Silva-Martínez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings.	IEEE Trans. Biomed. Circuits Syst.	2013	DBLP DOI BibTeX RDF
24	Song-Nien Tang, Chien-Ju Lee, Guo-Zua Wu	Soft-IP core design of LVDS receivers for multichannel ultrasound imaging applications.	ISCE	2013	DBLP DOI BibTeX RDF
24	Xiangyang Li	Implementation and Transmission Error Handling of Multi-channel LVDS.	EIDWT	2013	DBLP DOI BibTeX RDF
24	Vijaya Sankara Rao Pasupureddi, Nachiket V. Desai, Pradip Mandal	A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination.	Circuits Syst. Signal Process.	2012	DBLP DOI BibTeX RDF
24	Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	A 0.35~µm Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links.	IEEE Trans. Biomed. Circuits Syst.	2012	DBLP DOI BibTeX RDF
24	Hazem Wael Marar, Khaldoon Abugharbieh, Abdel-Karim Al-Tamimi	A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver.	ICECS	2012	DBLP DOI BibTeX RDF
24	Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links.	IEEE Trans. Circuits Syst. I Regul. Pap.	2011	DBLP DOI BibTeX RDF
24	Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park	A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration.	IEICE Trans. Electron.	2010	DBLP DOI BibTeX RDF
24	Khaldoon Abugharbieh, Shoba Krishnan, Jitendra Mohan, Varadarajan Devnath, Ivan Duzevik	An Ultralow-Power 10-Gbits/s LVDS Output Driver.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
24	Armin Tajalli, Yusuf Leblebici	A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
24	Seung-Jin Park, Young Hun Seo, Hong-June Park, Jae-Yoon Sim	A Distortion-Free General Purpose LVDS Driver.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
24	Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu	Design of an All-Digital LVDS Driver.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
24	Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco	OTA-C Oscillator with Low Frequency Variations for On-chip Clock Generation in Serial LVDS-AER Links.	ISCAS	2009	DBLP DOI BibTeX RDF
24	Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho	Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's.	IEICE Trans. Electron.	2008	DBLP DOI BibTeX RDF
24	Peng Chu, Zhiping Wen 0001, Lixin Yu	A Novel Low-Voltage Low-Power LVDS Driver.	IMECS	2007	DBLP BibTeX RDF
24	Vladimir Bratov, Jeb Binkley, Vladimir Katzman, John Choma	Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2006	DBLP DOI BibTeX RDF
24	Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, Jin-Fon Huang	Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
24	Panduka Wijetunga	A 10.0Gb/s all-active LVDS receiver in 0.18µm CMOS technology.	IEICE Electron. Express	2006	DBLP DOI BibTeX RDF
24	Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona	A LVDS Serial AER Link.	ICECS	2006	DBLP DOI BibTeX RDF
24	Chung-Yuan Chen, Tai-Ping Sun	A Novel CMOS Mini-LVDS Receiver for Flat-Plane Application.	ICECS	2006	DBLP DOI BibTeX RDF
24	Jyh-Shin Pan, Tse-Hsiang Hsu, Hao-Cheng Chen, Jong-Woei Chen, Bing-Yu Hsieh, Hong-Ching Chen, Wei-Hsuan Tu, Chi-Ming Chang, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan-Cheng Hsiao, Chuan Liu, Lily Huang, Chia-Hua Chou, Chang-Long Wu, Meng-Hsueh Lin, Shang-Ping Chen, Brian Liu, Heng-Shou Hsu, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Sean Chien, Kuan-Hua Chao, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Yih-Shin Weng, Ming-Shiam Tsai, Kun-Hung Hsieh, Kuang-Jung Chang, Jin-Chuan Hsu, Hsiu-Chen Peng, Alex Ho	Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY.	ISSCC	2006	DBLP DOI BibTeX RDF
24	Chung-Yuan Chen, Jia-Hong Wang, Tai-Ping Sun	A Novel Mini-LVDS Receiver in 0.35-um CMOS.	SoCC	2006	DBLP DOI BibTeX RDF
24	Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson	Low-voltage low-power LVDS drivers.	IEEE J. Solid State Circuits	2005	DBLP DOI BibTeX RDF
24	Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho	Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC.	ESSCIRC	2004	DBLP DOI BibTeX RDF
24	Gunjan Mandal, Pradip Mandal	Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation.	ISCAS (1)	2004	DBLP BibTeX RDF
24	Mehdi Bathaee, Zed Mostoufi, Hamid Ghezelayagh, Anahita Afkham	A 2.0 GHz 4 Mb pseudo-SRAM with on-chip BIST for refresh in 0.18u CMOS technology with LVDS output data bus drivers.	ICECS	2002	DBLP DOI BibTeX RDF
24	Andrea Boni, Andrea Pierazzi, Davide Vecchi	LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
24	Magnus Eckersand, Fredrik Franzon, Ken Filliter	Using at-speed BIST to test LVDS serializer/deserializer function.	ETW	2001	DBLP DOI BibTeX RDF
24	Andrea Diermeier	Interfacing between LVDS and ECL.	Microprocess. Microsystems	1998	DBLP DOI BibTeX RDF
19	Cameron D. Patterson, Steven W. Ellingson, Brian S. Martin, K. Deshpande, John H. Simonetti, Michael Kavic, Sean E. Cutchin	Searching for Transient Pulses with the ETA Radio Telescope.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Direct sampling radio telescope array, FPGA cluster computing, RFI mitigation, signal dedispersion
19	Boo-Young Choi, Jung-Won Han, Sung Min Park 0001, Kang-Yeob Park, Wonseok Oh 0003, J.-C. Choi	A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Hans Kristian Otnes Berge, Philipp Häfliger	High-Speed Serial AER on FPGA.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Adnan Gundel, William N. Carr	A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range.	ISCAS	2007	DBLP DOI BibTeX RDF
19	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
19	Jay Abraham, Guruprasad Rao	Qualification and Integration of Complex I/O in SoC Design Flows.	DATE	2004	DBLP DOI BibTeX RDF
19	Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino	Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.	ISLPED	2004	DBLP DOI BibTeX RDF	LCD displays, digital display interfaces, low-power bus encoding
19	Mohamed M. Hafed, Antonio H. Chan, Geoffrey D. Duerden, Bardia Pishdad, Clarence Tam, Sébastien Laberge, Gordon W. Roberts	A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing.	ITC	2004	DBLP DOI BibTeX RDF
19	Stephen J. Bellis, William P. Marnane	A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System.	FPL	2000	DBLP DOI BibTeX RDF
19	Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano	MEMOnet : Network interface plugged into a memory slot.	CLUSTER	2000	DBLP DOI BibTeX RDF