Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
149 | Magnus Eckersand, Fredrik Franzon, Ken Filliter |
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(2), pp. 171-177, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
LVDS, BIST, differential, At-speed |
83 | Carlos Zamarreño-Ramos, Rafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco |
LVDS interface for AER links with burst mode operation capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 644-647, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
83 | Ming-Dou Ker, Chien-Hua Wu |
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
66 | Feng Zhang 0014, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu |
A High Speed CMOS Transmitter and Rail-to-Rail Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 67-70, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
LVDS rail-to-rail |
63 | Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona |
LVDS Serial AER Link performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1537-1540, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
63 | Gunjan Mandal, Pradip Mandal |
Low-power LVDS receiver for 1.3Gbps physical layer (PHY) interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2180-2183, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
63 | Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo |
Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 702-705, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang |
DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Intell. Robotic Syst. ![In: J. Intell. Robotic Syst. 53(3), pp. 247-261, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint |
44 | Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu |
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 97-98, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Fabio Sousa, Volker Mauer, Neimar Duarte, Ricardo P. Jasinski, Volnei A. Pedroni |
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 1088-1091, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | Nidhir Kumar, Senthil N. Velu, Rajan Verma |
Gateway to Chips: High Speed I/O Signalling and Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 3-4, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Donald M. Chiarulli, Jason D. Bakos, Joel R. Martin, Steven P. Levitan |
Area, power, and pin efficient bus transceiver using multi-bit-differential signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1662-1665, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Rashed Zafar Bhatti, Monty Denneau, Jeff Draper |
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 198-203, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection |
27 | Darren Aaberge, Ken Mockler, Dieu Van Dinh, Raoul Belleau, Tim Donovan, Reid Hewlitt |
Meeting the Test Challenges of the 1 Gbps Parallel RapidIO Interface with New Automatic Test Equipment Capabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 75-84, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
RapidIO, Source-Synchronous, LVDS, Differential, ATE, Non-determinism |
27 | G. N. Nandakumar, Nirav Patel, Raghunatha Reddy, Makeshwar Kothandaraman |
Application of Douglas-Peucker Algorithm to Generate Compact but Accurate IBIS Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 757-761, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
LVDS, DPbasic, Monotonic, IBIS |
24 | Nanditha Maragowdanahalli Shivalingaiah, Vijaya Prakash Anamanahalli Mariyappa |
Performance Analysis of FinFET-Based LVDS I/O Receiver Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SN Comput. Sci. ![In: SN Comput. Sci. 4(2), pp. 145, March 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Akihiko Tsukahara, Sung-Gwi Cho, Keita Tanaka, Akihiko Homma, Yoshinori Uchikawa |
Design and Trial Production FPGA based Stochastic Resonance Circuit Using LVDS and an Examination for Surface EMG Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SICE ![In: 62nd Annual Conference of the Society of Instrument and Control Engineers, SICE 2023, Tsu, Japan, September 6-9, 2023, pp. 345-350, 2023, IEEE, 978-4-9077-6480-7. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
24 | Alexandros D. Bechrakis Triantafyllos, Alexandra P. Mavropoulou, Anargyros T. Baklezos, Christos N. Capsalis, Christos D. Nikolopoulos |
Towards the Prediction of SpaceWire Radiated Emissions Employing an LVDS Signal Emulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 34090-34097, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Jinrong Li, Jue Wang, Xu Cheng 0002, Yicheng Zeng, Xiaoyang Zeng |
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021, pp. 1-4, 2021, IEEE, 978-1-6654-3867-4. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Christos D. Nikolopoulos, Anargyros T. Baklezos, Stylianos Tsatalas, Christos N. Capsalis |
Verification of Radiated Emissions Modeling for SpaceWire/LVDS Links Routed on CFRP Ground. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Aerosp. Electron. Syst. ![In: IEEE Trans. Aerosp. Electron. Syst. 56(1), pp. 393-402, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Seng Siong Lee, Lini Lee, Fabian Wai Lee Kung, Ahmed Saad, Harikrishnan Ramiah, Gim Heng Tan |
A Low Power High Precision Trim-Less Envelope Detector for Fail-Safe Circuit in LVDS Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 67-II(10), pp. 1770-1774, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Liang Xie 0004, Shunle Guo, Zhaoxi Li, Xiangliang Jin |
A High Speed Rail-to-Rail Operational Amplifier with Constant-gm for LVDS Receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCT ![In: 20th IEEE International Conference on Communication Technology, ICCT 2020, Nanning, China, October 28-31, 2020, pp. 1044-1048, 2020, IEEE, 978-1-7281-8141-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
24 | Ning Qiao, Giacomo Indiveri |
A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1908.06532, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
24 | Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici |
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIME ![In: 15th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2019, Lausanne, Switzerland, July 15-18, 2019, pp. 101-104, 2019, IEEE, 978-1-7281-3549-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Niraj Kumar Jha, Dishank Yadav, Anuj Maheshwari, Mrigank Sharad |
Radiation Hardened High-Speed LVDS compliant Transceiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: International Conference on Electronics, Communications and Computers, CONIELECOMP 2019, Cholula, Mexico, February 27 - March 1, 2019, pp. 55-59, 2019, IEEE, 978-1-7281-1145-2. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Pengfei Lang, Qingfeng Shi, Zebing Xie, Hongtao Zheng, Yan Zhao |
Research on Intelligent Estimation Model of BER for High-Speed Image Transmission Based on LVDS Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADHIP (2) ![In: Advanced Hybrid Information Processing - Third EAI International Conference, ADHIP 2019, Nanjing, China, September 21-22, 2019, Proceedings, Part II, pp. 72-81, 2019, Springer, 978-3-030-36404-5. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Seng Siong Lee, Lini Lee, Wai Lee Kung, Ahmed Saad, Gim Heng Tan |
A fully integrated and high precision 350 mV amplitude regulated LVDS transmitter compensating PVT variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 81, pp. 192-199, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Hanyang Xu, Jian Wang 0036, Jinmei Lai |
Design of a power efficient self-adaptive LVDS driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(5), pp. 20171276, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Durga Prasanth Kumar Gavara, G. Shekar |
Design of LVDS Transmitter with SLVDS mode for Low Power Applications in 55nm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICACCI ![In: 2018 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2018, Bangalore, India, September 19-22, 2018, pp. 808-812, 2018, IEEE, 978-1-5386-5314-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Srikanth Jagannathan, Kumar Abhishek, Nihaar N. Mahatme, Ender Yilmaz |
Design of aging aware 5 Gbps LVDS transmitter for automotive applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRPS ![In: IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018, pp. 5, 2018, IEEE, 978-1-5386-5479-8. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Ning Qiao, Giacomo Indiveri |
A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018, pp. 93-101, 2018, IEEE Computer Society, 978-1-5386-5883-3. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Gianluca Traversi, Francesco De Canio, Valentino Liberali, Alberto Stabile |
Characterization of an LVDS Link in 28 nm CMOS for Multi-Purpose Pattern Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2018, 27-30 May 2018, Florence, Italy, pp. 1-4, 2018, IEEE, 978-1-5386-4881-0. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Jayshree, G. Seetharaman |
Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: 2018 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2018, Edinburgh, United Kingdom, August 6-9, 2018, pp. 204-209, 2018, IEEE, 978-1-5386-7753-7. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Wei Fan, Zhelu Li, Jianxiong Xi, Lenian He, Kexu Sun, Ning Xie |
A 1.2 Gbps failsafe low jitter LVDS transmitter-receiver applied in CMOS image sensor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 7th International Conference on Modern Circuits and Systems Technologies, MOCAST 2018, Thessaloniki, Greece, May 7-9, 2018, pp. 1-4, 2018, IEEE, 978-1-5386-4788-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
24 | Syed Arsalan Jawed, Ali Asghar, Khubaib Khan, Shahbaz Abbasi, Muhammad Naveed 0004, Yasir Siddiqi, Waqas Siddiqi |
A configurable 2-Gbps LVDS transceiver in 150-nm CMOS with pre-emphasis, equalization, and slew rate control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 45(10), pp. 1369-1381, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco |
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 11(5), pp. 1133-1147, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco |
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco |
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Munish Malik, Ajay Kumar, H. S. Jatana |
Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers, pp. 667-678, 2017, Springer, 978-981-10-7469-1. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Gianluca Traversi, Francesco De Canio, Valentino Liberali, Alberto Stabile |
Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOCAST ![In: 6th International Conference on Modern Circuits and Systems Technologies, MOCAST 2017, Thessaloniki, Greece, May 4-6, 2017, pp. 1-4, 2017, IEEE, 978-1-5090-4386-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Jayshree, Seema Verma, Amitabh Chatterjee |
A methodology for designing LVDS interface system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISED ![In: Sixth International Symposium on Embedded Computing and System Design, ISED 2016, Patna, India, December 15-17, 2016, pp. 284-288, 2016, IEEE, 978-1-5090-2541-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Luis Sanchez, Giancarlo Patino, Víctor Murray, James Lyke |
Reduced power consumption in the FPGA-based Universal Link for LVDS communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 7th Latin American Symposium on Circuits & Systems, LASCAS 2016, Florianopolis, Brazil, February 28 - March 2, 2016, pp. 283-286, 2016, IEEE, 978-1-4673-7835-2. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Giacomo Alberto Graceffa, Umberto Gatti, Cristiano Calligaro |
A 400 Mbps radiation hardened by design LVDS compliant driver and receiver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, December 11-14, 2016, pp. 109-112, 2016, IEEE, 978-1-5090-6113-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Yuan Su, Fan Ye 0001, Junyan Ren |
A high power-efficient LVDS output driver with adjustable feed-forward capacitor compensation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 12(11), pp. 20150368, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Luis Sanchez, Giancarlo Patino, Víctor Murray, James Lyke |
Hardware implementation of a FPGA-based universal link for LVDS communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8332-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Yuan Su, Yimin Wu, Qiang Zhang, Xuerong Zhou, Fan Ye 0001, Junyan Ren |
LVDS transmitter with optimized high power-efficiency 8: 1 MUX. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASICON ![In: 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8483-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh |
Methodology for optimizing ESD protection for high speed LVDS based I/Os. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VDAT ![In: 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015, pp. 1-5, 2015, IEEE Computer Society, 978-1-4799-1743-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Kyeong-Min Kim, Sewook Hwang, Junyoung Song, Chulwoo Kim |
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(10), pp. 2156-2163, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Sultan A. Alqarni, Ahmed K. Kamal |
LVDS receiver with 7mW consumption at 1.5 Gbps. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 26th International Conference on Microelectronics, ICM 2014, Doha, Qatar, December 14-17, 2014, pp. 204-207, 2014, IEEE, 978-1-4799-8153-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Benjamín T. Reyes, German Paulina, Lucas Tealdi, Emanuel Labat, Raul M. Sanchez, Pablo Sergio Mandolesi, Mario Rafael Hueda |
A 1.6Gb/s CMOS LVDS transmitter with a programmable pre-emphasis system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, February 25-28, 2014, pp. 1-4, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Taras Iakymchuk, Alfredo Rosado, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno |
An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014, pp. 1556-1559, 2014, IEEE, 978-1-4799-3431-7. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Seng Siong Lee, Ahmed Saad, Lini Lee, Wai Lee Kung |
On-chip slew-rate control for low-voltage differential signalling (LVDS) driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2014, Kuching, Sarawak, Malaysia, December 1-4, 2014, pp. 99-101, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Tadeusz Satlawa, Aleksandra Drozd, Piotr Kmon |
Design of the ultrafast LVDS I/O interface in 40 nm CMOS process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2014, Lviv, Ukraine, June 19-21, 2014, pp. 200-204, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Carlos Zamarreño-Ramos, Raghavendra Kulkarni, José Silva-Martínez, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco |
A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 7(5), pp. 722-731, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Song-Nien Tang, Chien-Ju Lee, Guo-Zua Wu |
Soft-IP core design of LVDS receivers for multichannel ultrasound imaging applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCE ![In: IEEE International Symposium on Consumer Electronics, ISCE 2013, Hsinchu City, Taiwan, June 3-6, 2013, pp. 233-234, 2013, IEEE, 978-1-4673-6198-9. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Xiangyang Li |
Implementation and Transmission Error Handling of Multi-channel LVDS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIDWT ![In: 2013 Fourth International Conference on Emerging Intelligent Data and Web Technologies, Xi'an, Shaanxi, China, September 9-11, 2013, pp. 466-470, 2013, IEEE Computer Society, 978-0-7695-5044-2. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Vijaya Sankara Rao Pasupureddi, Nachiket V. Desai, Pradip Mandal |
A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 31(1), pp. 31-49, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco |
A 0.35~µm Sub-ns Wake-up Time ON-OFF Switchable LVDS Driver-Receiver Chip I/O Pad Pair for Rate-Dependent Power Saving in AER Bit-Serial Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Biomed. Circuits Syst. ![In: IEEE Trans. Biomed. Circuits Syst. 6(5), pp. 486-497, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Hazem Wael Marar, Khaldoon Abugharbieh, Abdel-Karim Al-Tamimi |
A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012, pp. 240-243, 2012, IEEE, 978-1-4673-1261-5. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco |
An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11), pp. 2647-2660, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
24 | Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park |
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 93-C(1), pp. 132-135, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Khaldoon Abugharbieh, Shoba Krishnan, Jitendra Mohan, Varadarajan Devnath, Ivan Duzevik |
An Ultralow-Power 10-Gbits/s LVDS Output Driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1), pp. 262-269, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
24 | Armin Tajalli, Yusuf Leblebici |
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 44(2), pp. 538-548, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Seung-Jin Park, Young Hun Seo, Hong-June Park, Jae-Yoon Sim |
A Distortion-Free General Purpose LVDS Driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 92-C(2), pp. 278-280, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu |
Design of an All-Digital LVDS Driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8), pp. 1635-1644, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco |
OTA-C Oscillator with Low Frequency Variations for On-chip Clock Generation in Serial LVDS-AER Links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2009), 24-17 May 2009, Taipei, Taiwan, pp. 2657-2660, 2009, IEEE, 978-1-4244-3827-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho |
Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 91-C(1), pp. 72-80, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
24 | Peng Chu, Zhiping Wen 0001, Lixin Yu |
A Novel Low-Voltage Low-Power LVDS Driver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMECS ![In: Proceedings of the International MultiConference of Engineers and Computer Scientists 2007, IMECS 2007, March 21-23, 2007, Hong Kong, China, pp. 1646-1649, 2007, Newswood Limited, 978-988-98671-4-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
24 | Vladimir Bratov, Jeb Binkley, Vladimir Katzman, John Choma |
Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(10), pp. 2101-2108, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Chua-Chin Wang, Ching-Li Lee, Chun-Yang Hsiao, Jin-Fon Huang |
Clock-and-Data Recovery Design for LVDS Transceiver Used in LCD Panels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 53-II(11), pp. 1318-1322, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Panduka Wijetunga |
A 10.0Gb/s all-active LVDS receiver in 0.18µm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 3(10), pp. 216-220, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Lourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, Rafael Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona |
A LVDS Serial AER Link. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 938-941, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Chung-Yuan Chen, Tai-Ping Sun |
A Novel CMOS Mini-LVDS Receiver for Flat-Plane Application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006, pp. 260-263, 2006, IEEE, 1-4244-0395-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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24 | Jyh-Shin Pan, Tse-Hsiang Hsu, Hao-Cheng Chen, Jong-Woei Chen, Bing-Yu Hsieh, Hong-Ching Chen, Wei-Hsuan Tu, Chi-Ming Chang, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan-Cheng Hsiao, Chuan Liu, Lily Huang, Chia-Hua Chou, Chang-Long Wu, Meng-Hsueh Lin, Shang-Ping Chen, Brian Liu, Heng-Shou Hsu, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Sean Chien, Kuan-Hua Chao, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Yih-Shin Weng, Ming-Shiam Tsai, Kun-Hung Hsieh, Kuang-Jung Chang, Jin-Chuan Hsu, Hsiu-Chen Peng, Alex Ho |
Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006, pp. 1022-1031, 2006, IEEE, 1-4244-0079-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Chung-Yuan Chen, Jia-Hong Wang, Tai-Ping Sun |
A Novel Mini-LVDS Receiver in 0.35-um CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: 2006 IEEE International SOC Conference, Austin, Texas, USA, September 24-27, 2006, pp. 65-68, 2006, IEEE, 0-7803-9781-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
24 | Mingdeng Chen, Jose Silva-Martinez, Michael Nix, Moises E. Robinson |
Low-voltage low-power LVDS drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 40(2), pp. 472-479, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
24 | Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho |
Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ESSCIRC ![In: 33rd European Solid-State Circuits Conference, ESSCIRC 2004, Leuven, Belgium, September 21-23, 2004, pp. 319-322, 2004, IEEE. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
24 | Gunjan Mandal, Pradip Mandal |
Low power LVDS transmitter with low common mode variation for 1GB/s-per pin operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 1120-1123, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
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24 | Mehdi Bathaee, Zed Mostoufi, Hamid Ghezelayagh, Anahita Afkham |
A 2.0 GHz 4 Mb pseudo-SRAM with on-chip BIST for refresh in 0.18u CMOS technology with LVDS output data bus drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2002 9th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2002, Dubrovnik, Croatia, September 15-18, 2002, pp. 839-841, 2002, IEEE, 0-7803-7596-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
24 | Andrea Boni, Andrea Pierazzi, Davide Vecchi |
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 36(4), pp. 706-711, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Magnus Eckersand, Fredrik Franzon, Ken Filliter |
Using at-speed BIST to test LVDS serializer/deserializer function. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001, pp. 140-145, 2001, IEEE Computer Society, 0-7695-1017-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | Andrea Diermeier |
Interfacing between LVDS and ECL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 21(5), pp. 337-342, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Cameron D. Patterson, Steven W. Ellingson, Brian S. Martin, K. Deshpande, John H. Simonetti, Michael Kavic, Sean E. Cutchin |
Searching for Transient Pulses with the ETA Radio Telescope. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(4), pp. 20:1-20:19, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Direct sampling radio telescope array, FPGA cluster computing, RFI mitigation, signal dedispersion |
19 | Boo-Young Choi, Jung-Won Han, Sung Min Park 0001, Kang-Yeob Park, Wonseok Oh 0003, J.-C. Choi |
A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 181-184, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Hans Kristian Otnes Berge, Philipp Häfliger |
High-Speed Serial AER on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 857-860, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Adnan Gundel, William N. Carr |
A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3111-3114, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Vinita V. Deodhar, Jeffrey A. Davis |
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 592-597, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jay Abraham, Guruprasad Rao |
Qualification and Integration of Complex I/O in SoC Design Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 286-293, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Sabino Salerno, Alberto Bocca, Enrico Macii, Massimo Poncino |
Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004, pp. 206-211, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
LCD displays, digital display interfaces, low-power bus encoding |
19 | Mohamed M. Hafed, Antonio H. Chan, Geoffrey D. Duerden, Bardia Pishdad, Clarence Tam, Sébastien Laberge, Gordon W. Roberts |
A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 728-737, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Stephen J. Bellis, William P. Marnane |
A CORDIC Arctangent FPGA Implementation for a High-Speed 3D-Camera System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, The Roadmap to Reconfigurable Computing, 10th International Workshop, FPL 2000, Villach, Austria, August 27-30, 2000, Proceedings, pp. 485-494, 2000, Springer, 3-540-67899-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano |
MEMOnet : Network interface plugged into a memory slot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: 2000 IEEE International Conference on Cluster Computing (CLUSTER 2000), November 28th - December 1st, 2000, Technische Universität Chemnitz, Saxony, Germany, pp. 17-16, 2000, IEEE Computer Society, 0-7695-0896-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|