Search results for "MCML"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
182	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	MOS current mode circuits: analysis, design, and variability.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
117	Francesco Regazzoni 0001, Thomas Eisenbarth 0001, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne	Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.	Trans. Comput. Sci.	2009	DBLP DOI BibTeX RDF
117	Francesco Regazzoni 0001, Stéphane Badel, Thomas Eisenbarth 0001, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne	A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.	ICSAMOS	2007	DBLP DOI BibTeX RDF
109	Tin Wai Kwan, Maitham Shams	Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic.	ASYNC	2005	DBLP DOI BibTeX RDF
109	Mohab Anis, Mohamed I. Elmasry	Self-timed MOS current mode logic for digital applications.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
91	Tin Wai Kwan, Maitham Shams	Design of Multi-GHz Asynchronous Pipelined Circuits in MOS Current-Mode Logic.	VLSI Design	2005	DBLP DOI BibTeX RDF
81	Massimo Alioto, Gaetano Palumbo	Power-delay optimization in MCML tapered buffers.	ISCAS	2008	DBLP DOI BibTeX RDF
81	Dinh Hung Dang, Yvon Savaria, Mohamad Sawan	A novel approach for implementing ultra-high speed flash ADC using MCML circuits.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
67	Osman Musa Abdulkarim, Maitham Shams	A symmetric mos current-mode logic universal gate for high speed applications.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	MCML, SCL, VLSI, ASIC
67	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Design and optimization of MOS current mode logic for parameter variations.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	MCML, optimization, design, automation, variation, technology scaling
63	Roberto Pereira-Arroyo, Pablo Alvarado-Moya, Wolfgang H. Krautschneider	Design of a MCML Gate Library Applying Multiobjective Optimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
63	Hung Tien Bui	Dual-Path and Diode-Tracking Active Inductors for MCML Gates.	CCECE	2006	DBLP DOI BibTeX RDF
55	Shahnam Khabiri, Maitham Shams	A mathematical programming approach to designing MOS current-mode logic circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
55	Jason M. Musicer, Jan M. Rabaey	MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments.	ISLPED	2000	DBLP DOI BibTeX RDF	CORDIC, digital logic, current mode logic, low-energy design
52	Tetsuo Endoh, Masashi Kamiyanagi	Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch.	IEICE Trans. Electron.	2009	DBLP DOI BibTeX RDF
49	Mahta Haghi, Jeff Draper	The effect of design parameters on single-event upset sensitivity of MOS current mode logic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mos current mode logic (mcml), single event upset (seu), design parameters, radiation hardening
44	Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer	Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
44	Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli	Analysis and design of MCML gates with hysteresis.	ISCAS	2006	DBLP DOI BibTeX RDF
44	Massimo Alioto, Gaetano Palumbo	Nanometer MCML gates: models and design considerations.	ISCAS	2006	DBLP DOI BibTeX RDF
44	Shahnam Khabiri, Maitham Shams	An MCML four-bit ripple-carry adder design in 1 GHz range.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
44	Hung Tien Bui, Yvon Savaria	10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.	IWSOC	2004	DBLP DOI BibTeX RDF
36	Yung-Pin Cheng, Han-Shu Chen	SoftMon: programmable software monitoring with minimum overhead by helper-threading.	SAC	2008	DBLP DOI BibTeX RDF	multi-core CPU, monitoring, SMP, dynamic program analysis, helper threading
36	Zeynep Toprak Deniz, Yusuf Leblebici	Low-power current mode logic for improved DPA-resistance in embedded systems.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
36	Matthias Beyer, Winfried Dulz, Fenhua Zhen	Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov Chains.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
26	Hongru Wang 0003, Zezhong Wang 0007, Wai Chung Kwan, Kam-Fai Wong	MCML: A Novel Memory-based Contrastive Meta-Learning Method for Few Shot Slot Tagging.	IJCNLP (1)	2023	DBLP DOI BibTeX RDF
26	Kristopher Brown, Yasheng Maimaiti, Kai Trepte, Thomas Bligaard, Johannes Voss	MCML: Combining physical constraints with experimental data for a multi-purpose meta-generalized gradient approximation.	J. Comput. Chem.	2021	DBLP DOI BibTeX RDF
26	Hongru Wang 0003, Zezhong Wang 0007, Gabriel Pui Cheong Fung, Kam-Fai Wong	MCML: A Novel Memory-based Contrastive Meta-Learning Method for Few Shot Slot Tagging.	CoRR	2021	DBLP BibTeX RDF
26	Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo	A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML.	ISCAS	2021	DBLP DOI BibTeX RDF
26	Mahdi Yektaei, M. B. Ghaznavi-Ghoushchi	PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications.	IEEE Trans. Very Large Scale Integr. Syst.	2020	DBLP DOI BibTeX RDF
26	Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo	Delay models and design guidelines for MCML gates with resistor or PMOS load.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
26	Gaetano Palumbo, Giuseppe Scotti	A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
26	Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo	A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
26	Muhammad Usman 0024, Wenxi Wang, Marko Vasic, Kaiyuan Wang, Haris Vikalo, Sarfraz Khurshid	A study of the learnability of relational properties: model counting meets machine learning (MCML).	PLDI	2020	DBLP DOI BibTeX RDF
26	K. P. Sai Pradeep, S. Suresh Kumar	Design and development of high performance MOS current mode logic (MCML) processor for fast and power efficient computing.	Clust. Comput.	2019	DBLP DOI BibTeX RDF
26	Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti	A Novel Very Low Voltage Topology to implement MCML XOR Gates.	PRIME	2018	DBLP DOI BibTeX RDF
26	Neeta Pandey, Kirti Gupta, Bharat Choudhary	MCML Dynamic Register Design.	MWSCAS	2018	DBLP DOI BibTeX RDF
26	Tianshuo Zhao, Leonard MacEachern	A High Resolution MCML-based Time-to-Digital Converter Implementation.	MWSCAS	2018	DBLP DOI BibTeX RDF
26	Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo	A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering.	ICECS	2018	DBLP DOI BibTeX RDF
26	Neeta Pandey, Kirti Gupta, Bharat Choudhary	New Proposal for MCML Based Three-Input Logic Implementation.	VLSI Design	2016	DBLP DOI BibTeX RDF
26	Bruno Canal, Cicero S. Nunes, Renato P. Ribas, Eric E. Fabris	MCML Gate Design for Standard Cell Library.	SBCCI	2015	DBLP DOI BibTeX RDF
26	Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Engin Ipek, Eby G. Friedman	Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime.	ICCD	2015	DBLP DOI BibTeX RDF
26	Ruiping Cao, Jianping Hu	Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits.	J. Electr. Comput. Eng.	2014	DBLP DOI BibTeX RDF
26	Sara Neshani, Seyed Javad Azhari	A Low-Power Low-voltage 6-Bit 1.33 GS/S Fully MCML All NMOS Flash ADC without a Front-End T/H.	J. Circuits Syst. Comput.	2013	DBLP DOI BibTeX RDF
26	Jianping Hu, Haiyan Ni, Yinshui Xia	High-Speed Low-Power MCML Nanometer Circuits with Near-Threshold Computing.	J. Comput.	2013	DBLP BibTeX RDF
26	Giuseppe Caruso	A delay model valid in all the regions of operation of the MOS transistor for the energy-efficient design of MCML gates.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
26	Alessandro Cevrero, Francesco Regazzoni 0001, Micheal Schwander, Stéphane Badel, Paolo Ienne, Yusuf Leblebici	Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.	DAC	2011	DBLP DOI BibTeX RDF
26	Francesco Cannillo, Christofer Toumazou, Tor Sverre Lande	Nanopower Subthreshold MCML in Submicrometer CMOS Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2009	DBLP DOI BibTeX RDF
26	Yavuz Delican, Avni Morgül	High performance 16-bit MCML multiplier.	ECCTD	2009	DBLP DOI BibTeX RDF
26	Massimo Alioto, Yusuf Leblebici	Analysis and Design of Ultra-low Power Subthreshold MCML Gates.	ISCAS	2009	DBLP DOI BibTeX RDF
26	Massimo Alioto, Gaetano Palumbo	Power-Aware Design of Nanometer MCML Tapered Buffers.	IEEE Trans. Circuits Syst. II Express Briefs	2008	DBLP DOI BibTeX RDF
26	Giuseppe Caruso, Alessio Macchiarella	Optimum design of two-level MCML gates.	ICECS	2008	DBLP DOI BibTeX RDF
26	Giuseppe Caruso, Alessio Macchiarella	A design methodology for low-power MCML ring oscillators.	ECCTD	2007	DBLP DOI BibTeX RDF
26	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Low-power multi-threshold MCML: Analysis, design, and variability.	Microelectron. J.	2006	DBLP DOI BibTeX RDF
26	Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli	Exploiting Hysteresys in MCML Circuits.	IEEE Trans. Circuits Syst. II Express Briefs	2006	DBLP DOI BibTeX RDF
26	Massimo Alioto, Rosario Mita, Gaetano Palumbo	A Design Methodology for High-Speed Low-Power MCML Frequency Dividers.	ICECS	2006	DBLP DOI BibTeX RDF
26	Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici	Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.	ISCAS	2006	DBLP DOI BibTeX RDF
26	Hyun-Sook Chung, Yillbyung Lee	MCML: motion capture markup language for integration of heterogeneous motion capture data.	Comput. Stand. Interfaces	2004	DBLP DOI BibTeX RDF
26	Elizabeth J. Brauer, Yusuf Leblebici	Low noise MCML prefix adders using 0.18 µm CMOS technology.	Circuits, Signals, and Systems	2004	DBLP BibTeX RDF
26	Venkat Srinivasan, Dong Sam Ha, Jos Sulistyo	Gigahertz-range MCML multiplier architectures.	ISCAS (2)	2004	DBLP BibTeX RDF
26	Shahnam Khabiri, Maitham Shams	Implementation of MCML universal logic gate for 10 GHz-range in 0.13 µm CMOS technology.	ISCAS (2)	2004	DBLP BibTeX RDF
26	Hung Tien Bui, Yvon Savaria	Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.	ISCAS (4)	2004	DBLP BibTeX RDF
26	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	Analysis and design of low-power multi-threshold MCML.	SoCC	2004	DBLP DOI BibTeX RDF
26	Jochen Schimmelpfennig, Frank Kurth	MCML - Music Contents Markup Language.	ISMIR	2000	DBLP BibTeX RDF
18	Francesco Regazzoni 0001, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne	A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions.	CHES	2009	DBLP DOI BibTeX RDF
18	Stéphane Badel, Yusuf Leblebici	Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Vinaye Armoogum, K. M. S. Soyjaudah, A. Jugurnauth, Nawaz Mohamudally 0001, Terence C. Fogarty	Adjacent Channel Interference for DVB-T at UHF Bands in the South of Mauritius for Summer Season.	AICT	2007	DBLP DOI BibTeX RDF	Carrier to Noise ratio, Channel Interference, COFDM, Field Strength, Power Ratio, Bit Error Rate, Path Loss, PAL, DVB-T, DTT
18	Kuan Zhou, Yifei Luo, Sizhong Chen, Allen Drake, John F. McDonald 0001, Tong Zhang 0002	Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Giuseppe Caruso	Design of MOS current mode logic gates - computing the limits of voltage swing and bias current.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
18	Matthias Beyer, Winfried Dulz	Scenario-Based Statistical Testing of Quality of Service Requirements.	Scenarios: Models, Transformations and Tools	2003	DBLP DOI BibTeX RDF	Markov Chain Usage Model, QoS, Software Testing, Automatic Test Generation, TTCN-3, MSC, UML Sequence Diagram
18	Winfried Dulz, Fenhua Zhen	MaTeLo - Statistical Usage Testing by Annotated Sequence Diagrams, Markov Chains and TTCN-3.	QSIC	2003	DBLP DOI BibTeX RDF