The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for NoC with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1992-2003 (34) 2004 (54) 2005 (102) 2006 (133) 2007 (193) 2008 (189) 2009 (153) 2010 (156) 2011 (170) 2012 (153) 2013 (176) 2014 (149) 2015 (162) 2016 (138) 2017 (138) 2018 (132) 2019 (107) 2020 (100) 2021 (87) 2022 (74) 2023 (68) 2024 (6)
Publication types (Num. hits)
article(678) book(1) incollection(23) inproceedings(1948) phdthesis(24)
Venues (Conferences, Journals, ...)
NOCS(129) DATE(124) ISCAS(72) DSD(67) DAC(63) ISVLSI(53) SBCCI(53) CoRR(49) IEEE Trans. Very Large Scale I...(41) SOCC(39) ASP-DAC(37) IEEE Trans. Comput. Aided Des....(37) Microprocess. Microsystems(37) CODES+ISSS(35) NoCArc@MICRO(34) ICCD(33) More (+10 of total 510)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 1003 occurrences of 375 keywords

Results
Found 2678 publication records. Showing 2674 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
116Jinwen Xi, Peixin Zhong A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF network-on-chip, SystemC, energy model
111Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
107Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny The Power of Priority: NoC Based Distributed Cache Coherency. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
95Avinoam Kolodny Networks on chips: keeping up with Rent's rule and Moore's law. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF routing, timing, interconnect, power, on-chip network, wires
95Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar A methodology for design, modeling, and analysis of networks-on-chip. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
86Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
78Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Designing application-specific networks on chips with floorplan information. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF networks on chips, topology, floorplan, deadlock-free routing
73Mike Brugge, Mohammed A. S. Khalid Design and evaluation of a parameterizable NoC router for FPGAs (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, architecture, system-on-chip, network-on-chip, design space exploration, router
73Thuan Le, Mohammed Khalid NoC prototyping on FPGAs: A case study using an image processing benchmark. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
73Lazaros Papadopoulos, Dimitrios Soudris System-Level Application-Specific NoC Design for Network and Multimedia Applications. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
72Jia Li 0022, Qiang Xu 0001, Yu Hu 0001, Xiaowei Li 0001 Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction. Search on Bibsonomy DELTA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF NoC channel utilization, test wrapper, interleaved test scheduling
64Julien Delorme An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture. Search on Bibsonomy PATMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
64Shan Tang, Qiang Xu 0001 A multi-core debug platform for NoC-based systems. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
63Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
63Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. Search on Bibsonomy PDP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
61Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer 0001, Mazin S. Yousif, Chita R. Das Performance and power optimization through data compression in Network-on-Chip architectures. Search on Bibsonomy HPCA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
61Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
61Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li 0018, Li-Shiuan Peh Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
61Xin Wang, Tapani Ahonen, Jari Nurmi Applying CDMA Technique to Network-on-Chip. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
61Prabhat Avasare, Vincent Nollet, Jean-Yves Mignolet, Diederik Verkest, Henk Corporaal Centralized end-to-end flow control in a best-effort network-on-chip. Search on Bibsonomy EMSOFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF run-time communication management, network-on-chip
61Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani A Network on Chip Architecture and Design Methodology. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF System on Chip, IP, Platform based design, On-chip communication
59Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
59Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
58Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano 3-D NoC on Inductive Wireless Interconnect. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
58Vasilis F. Pavlidis, Eby G. Friedman Physical Analysis of NoC Topologies for 3-D Integrated Systems. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
55Jeremy Chan, Sri Parameswaran NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
55Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
55Chang Wu, Yubai Li, Song Chai, Zhongming Yang Lottery Router: A Customized Arbitral Priority NOC Router. Search on Bibsonomy CSSE (3) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
55José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne On the Potential of NoC Virtualization for Multicore Chips. Search on Bibsonomy CISIS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
55Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit Fast, Accurate and Detailed NoC Simulations. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Théodore Marescaux, Erik Brockmeyer, Henk Corporaal The Impact of Higher Communication Layers on NoC Supported MP-SoCs. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris Application - specific NoC platform design based on System Level Optimization. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Graham Schelle, Jeff Fifield, Dirk Grunwald A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Balasubramanian Sethuraman, Ranga Vemuri A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
55Érika F. Cota, Chunsheng Liu Constraint-Driven Test Scheduling for NoC-Based Systems. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
55Edith Beigné, Pascal Vivet Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture. Search on Bibsonomy ASYNC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
55Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF architecture, Systems-on-chip, mapping, networks on chip, synthesis
55Wooyoung Jang, David Z. Pan Application-aware NoC design for efficient SDRAM access. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF QoS, memory, flow control, router, NoC, on-chip communication
54Pavel Ghosh, Arunabha Sen Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints. Search on Bibsonomy SAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding
52Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri Modeling networking issues of network-on-chip: a coloured petri nets approach. Search on Bibsonomy SimuTools The full citation details ... 2009 DBLP  DOI  BibTeX  RDF modeling, network-on-chip, coloured petri nets
52Vasilis F. Pavlidis, Eby G. Friedman 3-D Topologies for Networks-on-Chip. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Martin Schoeberl A Time-Triggered Network-on-Chip. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Mahmut T. Kandemir, Ozcan Ozturk 0001, Vijay Degalahal Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod Linear-programming-based techniques for synthesis of network-on-chip architectures. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli Mapping and configuration methods for multi-use-case networks on chips. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF guaranteed throughput, multiple application platforms, systems on chips, networks on chips, reconfiguration, dynamic, use-cases, voltage scaling, frequency scaling, best effort
52Mário P. Véstias, Horácio C. Neto Area and performance optimization of a generic network-on-chip architecture. Search on Bibsonomy SBCCI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA, system-on-chip, network-on-chip
52Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
52Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen An event-based monitoring service for networks on chip. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF monitoring, debugging, Networks-on-Chip
52Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha A Power and Performance Model for Network-on-Chip Architectures. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
52Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde Operating-system controlled network on chip. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF operating system, network on chip, MP-SoC
52Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF application-specific designs, low-power, NOC, SOC
51Shouyi Yin, Leibo Liu, Shaojun Wei Buffer planning for application-specific networks-on-chip design. Search on Bibsonomy Sci. China Ser. F Inf. Sci. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF buffer planning, optimization, design automation, networks-on-chip (NoC)
51Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra Low power nanoscale buffer management for network on chip routers. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF nanoscale technology noc, soc, noc, router, dynamic power management
47Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson Challenges and Promising Results in NoC Prototyping Using FPGAs. Search on Bibsonomy IEEE Micro The full citation details ... 2007 DBLP  DOI  BibTeX  RDF FPGAs, interconnection network, network on chip, computer systems organization, computer system implementation
47Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi Using the inter- and intra-switch regularity in NoC switch testing. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Ewerson Carvalho, Ney Calazans, Fernando Moraes 0001 Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Mehdi Modarressi, Hamid Sarbazi-Azad Power-aware mapping for reconfigurable NoC architectures. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi An Analytical Model for Reliability Evaluation of NoC Architectures. Search on Bibsonomy IOLTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua An Analytical Performance Model for the Spidergon NoC. Search on Bibsonomy AINA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. Search on Bibsonomy ICSAMOS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF crosstalk avoidance codes, interconnect energy, networks on chip, crosstalk, wormhole switching
47Rickard Holsmark, Maurizio Palesi, Shashi Kumar Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Application Specific Routing, Networks on Chip, Routing Algorithms, Deadlock, Wormhole Switching
47Krishnan Srinivasan, Karam S. Chatha Layout aware design of mesh based NoC architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF network-on-chip, automated design, mesh topology
47Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten NoC monitoring: impact on the design flow. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Catherine H. Gebotys, Robert J. Gebotys A Framework for Security on NoC Technologies. Search on Bibsonomy ISVLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Mahmut T. Kandemir, Ozcan Ozturk 0001, Sai Prashanth Muralidhara Dynamic thread and data mapping for NoC based CMPs. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF mapping, dynamic, CMP, thread, NoC, data
47Itamar Cohen, Ori Rottenstreich, Isaac Keslassy Statistical Approach to NoC Design. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF T-Plot, NoC, statistical approach, capacity allocation, traffic matrices
47Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan A temperature-aware virtual submesh allocation scheme for noc-based manycore chips. Search on Bibsonomy SPAA The full citation details ... 2008 DBLP  DOI  BibTeX  RDF manycore chips, submesh allocation, algorithm, noc, temperature
47Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva Cache coherency communication cost in a NoC-based MPSoC platform. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF cache coherence, MPSoC, NoC, directory
47Daniel Barcelos, Eduardo Wenzel Brião, Flávio Rech Wagner A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs. Search on Bibsonomy SBCCI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF energy, MPSoC, NoC, task migration, memory organization
47Samuel Evain, Jean-Philippe Diguet Efficient space-time noc path allocation based on mutual exclusion and pre-reservation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF guarantied traffic, path allocation, NOC, CAD tool
46Mohammad Reza Kakoee, Igor Loi, Luca Benini A new physical routing approach for robust bundled signaling on NoC links. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing
46Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano A data protection unit for NoC-based architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF multiprocessor system-on-chip (MPSoC), security, embedded systems, data protection, network-on-chip (NoC)
45Ahmed Al-Maashri, Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Narayanan Vijaykrishnan Influence of Stacked 3D Memory/Cache Architectures on GPUs. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Abbas Sheibanyrad, Frédéric Pétrot Asynchronous 3D-NoCs Making Use of Serialized Vertical Links. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Axel Jantsch, Matthew Grange, Dinesh Pamunuwa The Promises and Limitations of 3-D Integration. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli 3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Shan Yan, Bill Lin 0001 Design of Application-Specific 3D Networks-on-Chip Architectures. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Brett Stanley Feero, Partha Pratim Pande Three-Dimensional Networks-on-Chip: Performance Evaluation. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Erik Jan Marinissen Testing 3D Stacked ICs Containing Through-Silicon Vias. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Chuan Seng Tan Three-Dimensional Integration of Integrated Circuits - an Introduction. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
45Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson Design and Computer Aided Design of 3DIC. Search on Bibsonomy 3D Integration for NoC-based SoC Architectures The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
43Vincenzo Rana, Donatella Sciuto A novel design framework for the design of reconfigurable systems based on NoCs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF network-on-chip, reconfigurable computing, design flow, mapping algorithm
43Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng NTPT: on the end-to-end traffic prediction in the on-chip networks. Search on Bibsonomy DAC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF end-to-end traffic prediction, network-on-chip, many-core
43Brett Feero, Partha Pratim Pande Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
43Shirish Bahirat, Sudeep Pasricha Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors. Search on Bibsonomy CODES+ISSS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF photonic interconnect, network-on-chip, chip multiprocessor
43Faizal Arya Samman, Thomas Hollstein, Manfred Glesner Flexible parallel pipeline network-on-chip based on dynamic packet identity management. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi Quarc: A Novel Network-On-Chip Architecture. Search on Bibsonomy ICPADS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Shan Yan, Bill Lin 0001 Design of application-specific 3D Networks-on-Chip architectures. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni Design Exploration of Optical Interconnection Networks for Chip Multiprocessors. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
43Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek Transaction-Based Communication-Centric Debug. Search on Bibsonomy NOCS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis Networks on chips for high-end consumer-electronics TV system architectures. Search on Bibsonomy DATE Designers' Forum The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Calin Ciordas, Andreas Hansson 0001, Kees Goossens, Twan Basten A Monitoring-Aware Network-on-Chip Design Flow. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Heikki Kariniemi, Jari Nurmi On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Krishnan Srinivasan, Karam S. Chatha A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Luciano Ost, Aline Mello 0001, José Palma 0002, Fernando Gehm Moraes, Ney Calazans MAIA: a framework for networks on chip generation and verification. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Stefano Santi, Bill Lin 0001, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti On the impact of traffic statistics on quality of service for networks on chip. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
Displaying result #1 - #100 of 2674 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][8][9][10][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license