Search results for "NoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
116	Jinwen Xi, Peixin Zhong	A Transaction-Level NoC Simulation Platform with Architecture-Level Dynamic and Leakage Energy Models.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	network-on-chip, SystemC, energy model
111	Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo	Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.	NOCS	2007	DBLP DOI BibTeX RDF
107	Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginosar, Avinoam Kolodny	The Power of Priority: NoC Based Distributed Cache Coherency.	NOCS	2007	DBLP DOI BibTeX RDF
95	Avinoam Kolodny	Networks on chips: keeping up with Rent's rule and Moore's law.	SLIP	2007	DBLP DOI BibTeX RDF	routing, timing, interconnect, power, on-chip network, wires
95	Jiang Xu 0001, Wayne H. Wolf, Jörg Henkel, Srimat T. Chakradhar	A methodology for design, modeling, and analysis of networks-on-chip.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
86	Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah	Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.	NOCS	2008	DBLP DOI BibTeX RDF
78	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing application-specific networks on chips with floorplan information.	ICCAD	2006	DBLP DOI BibTeX RDF	networks on chips, topology, floorplan, deadlock-free routing
73	Mike Brugge, Mohammed A. S. Khalid	Design and evaluation of a parameterizable NoC router for FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, architecture, system-on-chip, network-on-chip, design space exploration, router
73	Thuan Le, Mohammed Khalid	NoC prototyping on FPGAs: A case study using an image processing benchmark.	EIT	2009	DBLP DOI BibTeX RDF
73	Lazaros Papadopoulos, Dimitrios Soudris	System-Level Application-Specific NoC Design for Network and Multimedia Applications.	PATMOS	2007	DBLP DOI BibTeX RDF
72	Jia Li 0022, Qiang Xu 0001, Yu Hu 0001, Xiaowei Li 0001	Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.	DELTA	2008	DBLP DOI BibTeX RDF	NoC channel utilization, test wrapper, interleaved test scheduling
64	Julien Delorme	An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture.	PATMOS	2007	DBLP DOI BibTeX RDF
64	Shan Tang, Qiang Xu 0001	A multi-core debug platform for NoC-based systems.	DATE	2007	DBLP DOI BibTeX RDF
63	Henrique Cota de Freitas, Philippe Olivier Alexandre Navaux	On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routers.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	adaptable topologies, programmable NoC routers, networks-on-chip, reconfigurable computing, crossbar switch
63	Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina	xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures.	PDP	2008	DBLP DOI BibTeX RDF	NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
61	Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar R. Iyer 0001, Mazin S. Yousif, Chita R. Das	Performance and power optimization through data compression in Network-on-Chip architectures.	HPCA	2008	DBLP DOI BibTeX RDF
61	Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
61	Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin Li 0018, Li-Shiuan Peh	Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
61	Xin Wang, Tapani Ahonen, Jari Nurmi	Applying CDMA Technique to Network-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
61	Prabhat Avasare, Vincent Nollet, Jean-Yves Mignolet, Diederik Verkest, Henk Corporaal	Centralized end-to-end flow control in a best-effort network-on-chip.	EMSOFT	2005	DBLP DOI BibTeX RDF	run-time communication management, network-on-chip
61	Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani	A Network on Chip Architecture and Design Methodology.	ISVLSI	2002	DBLP DOI BibTeX RDF	System on Chip, IP, Platform based design, On-chip communication
59	Dragomir Milojevic, Luc J. M. Montperrus, Diederik Verkest	Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Multi-processor systems-on-chip (MPSoC), Real-time video encoding, AVC/H.264, Low-power VLSI implementation, decoding, Networks-on-chip (NoC)
59	Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach	A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application.	NOCS	2008	DBLP DOI BibTeX RDF	NoC testing, QDI asynchronous logic, Network-on-Chip, DfT, testability, NoC, Design-for-Test, GALS, SoC testing, testing methodology, on-chip communication, Globally Asynchronous - Locally Synchronous
58	Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano	3-D NoC on Inductive Wireless Interconnect.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
58	Vasilis F. Pavlidis, Eby G. Friedman	Physical Analysis of NoC Topologies for 3-D Integrated Systems.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
55	Jeremy Chan, Sri Parameswaran	NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
55	Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park	A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem.	ASP-DAC	2008	DBLP DOI BibTeX RDF
55	Chang Wu, Yubai Li, Song Chai, Zhongming Yang	Lottery Router: A Customized Arbitral Priority NOC Router.	CSSE (3)	2008	DBLP DOI BibTeX RDF
55	José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne	On the Potential of NoC Virtualization for Multicore Chips.	CISIS	2008	DBLP DOI BibTeX RDF
55	Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit	Fast, Accurate and Detailed NoC Simulations.	NOCS	2007	DBLP DOI BibTeX RDF
55	Théodore Marescaux, Erik Brockmeyer, Henk Corporaal	The Impact of Higher Communication Layers on NoC Supported MP-SoCs.	NOCS	2007	DBLP DOI BibTeX RDF
55	Lazaros Papadopoulos, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris	Application - specific NoC platform design based on System Level Optimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
55	Graham Schelle, Jeff Fifield, Dirk Grunwald	A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects.	FPL	2007	DBLP DOI BibTeX RDF
55	Balasubramanian Sethuraman, Ranga Vemuri	A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures.	VLSI Design	2007	DBLP DOI BibTeX RDF
55	Érika F. Cota, Chunsheng Liu	Constraint-Driven Test Scheduling for NoC-Based Systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
55	Edith Beigné, Pascal Vivet	Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture.	ASYNC	2006	DBLP DOI BibTeX RDF
55	Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli	NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	architecture, Systems-on-chip, mapping, networks on chip, synthesis
55	Wooyoung Jang, David Z. Pan	Application-aware NoC design for efficient SDRAM access.	DAC	2010	DBLP DOI BibTeX RDF	QoS, memory, flow control, router, NoC, on-chip communication
54	Pavel Ghosh, Arunabha Sen	Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints.	SAC	2010	DBLP DOI BibTeX RDF	greedy randomized heuristic, multi-processor system-on-chip (MPSoC), integer linear program, network-on-chip (NoC), voltage islanding
52	Hamid Hajabdolali Bazzaz, Marjan Sirjani, Ramtin Khosravi, Shamim Taheri	Modeling networking issues of network-on-chip: a coloured petri nets approach.	SimuTools	2009	DBLP DOI BibTeX RDF	modeling, network-on-chip, coloured petri nets
52	Vasilis F. Pavlidis, Eby G. Friedman	3-D Topologies for Networks-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
52	Martin Schoeberl	A Time-Triggered Network-on-Chip.	FPL	2007	DBLP DOI BibTeX RDF
52	Mahmut T. Kandemir, Ozcan Ozturk 0001, Vijay Degalahal	Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings.	VLSI Design	2007	DBLP DOI BibTeX RDF
52	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	Linear-programming-based techniques for synthesis of network-on-chip architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
52	Srinivasan Murali, Martijn Coenen, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	Mapping and configuration methods for multi-use-case networks on chips.	ASP-DAC	2006	DBLP DOI BibTeX RDF	guaranteed throughput, multiple application platforms, systems on chips, networks on chips, reconfiguration, dynamic, use-cases, voltage scaling, frequency scaling, best effort
52	Mário P. Véstias, Horácio C. Neto	Area and performance optimization of a generic network-on-chip architecture.	SBCCI	2006	DBLP DOI BibTeX RDF	FPGA, system-on-chip, network-on-chip
52	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
52	Calin Ciordas, Twan Basten, Andrei Radulescu, Kees Goossens, Jef L. van Meerbergen	An event-based monitoring service for networks on chip.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	monitoring, debugging, Networks-on-Chip
52	Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha	A Power and Performance Model for Network-on-Chip Architectures.	DATE	2004	DBLP DOI BibTeX RDF
52	Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde	Operating-system controlled network on chip.	DAC	2004	DBLP DOI BibTeX RDF	operating system, network on chip, MP-SoC
52	Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen	Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs.	DAC	2006	DBLP DOI BibTeX RDF	application-specific designs, low-power, NOC, SOC
51	Shouyi Yin, Leibo Liu, Shaojun Wei	Buffer planning for application-specific networks-on-chip design.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	buffer planning, optimization, design automation, networks-on-chip (NoC)
51	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
47	Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee, Puru Choudhary, Diana Marculescu, Michael Kaufman, Peter Nelson	Challenges and Promising Results in NoC Prototyping Using FPGAs.	IEEE Micro	2007	DBLP DOI BibTeX RDF	FPGAs, interconnection network, network on chip, computer systems organization, computer system implementation
47	Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi	Using the inter- and intra-switch regularity in NoC switch testing.	DATE	2007	DBLP DOI BibTeX RDF
47	Ewerson Carvalho, Ney Calazans, Fernando Moraes 0001	Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
47	Mehdi Modarressi, Hamid Sarbazi-Azad	Power-aware mapping for reconfigurable NoC architectures.	ICCD	2007	DBLP DOI BibTeX RDF
47	Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi	An Analytical Model for Reliability Evaluation of NoC Architectures.	IOLTS	2007	DBLP DOI BibTeX RDF
47	Mahmoud Moadeli, Alireza Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua	An Analytical Performance Model for the Spidergon NoC.	AINA	2007	DBLP DOI BibTeX RDF
47	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors.	ICSAMOS	2006	DBLP DOI BibTeX RDF
47	Partha Pratim Pande, Haibo Zhu, Amlan Ganguly, Cristian Grecu	Energy Reduction through Crosstalk Avoidance Coding in NoC Paradigm.	DSD	2006	DBLP DOI BibTeX RDF	crosstalk avoidance codes, interconnect energy, networks on chip, crosstalk, wormhole switching
47	Rickard Holsmark, Maurizio Palesi, Shashi Kumar	Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions.	DSD	2006	DBLP DOI BibTeX RDF	Application Specific Routing, Networks on Chip, Routing Algorithms, Deadlock, Wormhole Switching
47	Krishnan Srinivasan, Karam S. Chatha	Layout aware design of mesh based NoC architectures.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	network-on-chip, automated design, mesh topology
47	Calin Ciordas, Kees Goossens, Andrei Radulescu, Twan Basten	NoC monitoring: impact on the design flow.	ISCAS	2006	DBLP DOI BibTeX RDF
47	Catherine H. Gebotys, Robert J. Gebotys	A Framework for Security on NoC Technologies.	ISVLSI	2003	DBLP DOI BibTeX RDF
47	Mahmut T. Kandemir, Ozcan Ozturk 0001, Sai Prashanth Muralidhara	Dynamic thread and data mapping for NoC based CMPs.	DAC	2009	DBLP DOI BibTeX RDF	mapping, dynamic, CMP, thread, NoC, data
47	Itamar Cohen, Ori Rottenstreich, Isaac Keslassy	Statistical Approach to NoC Design.	NOCS	2008	DBLP DOI BibTeX RDF	T-Plot, NoC, statistical approach, capacity allocation, traffic matrices
47	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.	SPAA	2008	DBLP DOI BibTeX RDF	manycore chips, submesh allocation, algorithm, noc, temperature
47	Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva	Cache coherency communication cost in a NoC-based MPSoC platform.	SBCCI	2007	DBLP DOI BibTeX RDF	cache coherence, MPSoC, NoC, directory
47	Daniel Barcelos, Eduardo Wenzel Brião, Flávio Rech Wagner	A hybrid memory organization to enhance task migration and dynamic task allocation in NoC-based MPSoCs.	SBCCI	2007	DBLP DOI BibTeX RDF	energy, MPSoC, NoC, task migration, memory organization
47	Samuel Evain, Jean-Philippe Diguet	Efficient space-time noc path allocation based on mutual exclusion and pre-reservation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	guarantied traffic, path allocation, NOC, CAD tool
46	Mohammad Reza Kakoee, Igor Loi, Luca Benini	A new physical routing approach for robust bundled signaling on NoC links.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	NoC global link routing, bundled routing, delay matching, pin placement, robust signaling, wire length variability, bus routing
46	Leandro Fiorin, Gianluca Palermo, Slobodan Lukovic, Cristina Silvano	A data protection unit for NoC-based architectures.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	multiprocessor system-on-chip (MPSoC), security, embedded systems, data protection, network-on-chip (NoC)
45	Ahmed Al-Maashri, Guangyu Sun 0003, Xiangyu Dong, Yuan Xie 0001, Narayanan Vijaykrishnan	Influence of Stacked 3D Memory/Cache Architectures on GPUs.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Abbas Sheibanyrad, Frédéric Pétrot	Asynchronous 3D-NoCs Making Use of Serialized Vertical Links.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Axel Jantsch, Matthew Grange, Dinesh Pamunuwa	The Promises and Limitations of 3-D Integration.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli	3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Shan Yan, Bill Lin 0001	Design of Application-Specific 3D Networks-on-Chip Architectures.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Brett Stanley Feero, Partha Pratim Pande	Three-Dimensional Networks-on-Chip: Performance Evaluation.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Erik Jan Marinissen	Testing 3D Stacked ICs Containing Through-Silicon Vias.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Chuan Seng Tan	Three-Dimensional Integration of Integrated Circuits - an Introduction.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
45	Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson	Design and Computer Aided Design of 3DIC.	3D Integration for NoC-based SoC Architectures	2011	DBLP DOI BibTeX RDF
43	Vincenzo Rana, Donatella Sciuto	A novel design framework for the design of reconfigurable systems based on NoCs.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	network-on-chip, reconfigurable computing, design flow, mapping algorithm
43	Yoshi Shih-Chieh Huang, Kaven Chun-Kai Chou, Chung-Ta King, Shau-Yin Tseng	NTPT: on the end-to-end traffic prediction in the on-chip networks.	DAC	2010	DBLP DOI BibTeX RDF	end-to-end traffic prediction, network-on-chip, many-core
43	Brett Feero, Partha Pratim Pande	Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
43	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
43	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Flexible parallel pipeline network-on-chip based on dynamic packet identity management.	IPDPS	2008	DBLP DOI BibTeX RDF
43	Mahmoud Moadeli, Wim Vanderbauwhede, Ali Shahrabi	Quarc: A Novel Network-On-Chip Architecture.	ICPADS	2008	DBLP DOI BibTeX RDF
43	Shan Yan, Bill Lin 0001	Design of application-specific 3D Networks-on-Chip architectures.	ICCD	2008	DBLP DOI BibTeX RDF
43	Michele Petracca, Benjamin G. Lee, Keren Bergman, Luca P. Carloni	Design Exploration of Optical Interconnection Networks for Chip Multiprocessors.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Networks-on-Chip, Interconnection, Chip Multiprocessors, Optics
43	Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek	Transaction-Based Communication-Centric Debug.	NOCS	2007	DBLP DOI BibTeX RDF
43	Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod	Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms.	ASP-DAC	2007	DBLP DOI BibTeX RDF
43	Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud	Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations.	ISQED	2007	DBLP DOI BibTeX RDF
43	Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo	Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
43	Frits Steenhof, Harry Duque, Björn Nilsson, Kees Goossens, Rafael Peset Llopis	Networks on chips for high-end consumer-electronics TV system architectures.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
43	Calin Ciordas, Andreas Hansson 0001, Kees Goossens, Twan Basten	A Monitoring-Aware Network-on-Chip Design Flow.	DSD	2006	DBLP DOI BibTeX RDF
43	Heikki Kariniemi, Jari Nurmi	On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips.	FPL	2006	DBLP DOI BibTeX RDF
43	Krishnan Srinivasan, Karam S. Chatha	A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures.	ISQED	2006	DBLP DOI BibTeX RDF
43	Luciano Ost, Aline Mello 0001, José Palma 0002, Fernando Gehm Moraes, Ney Calazans	MAIA: a framework for networks on chip generation and verification.	ASP-DAC	2005	DBLP DOI BibTeX RDF
43	Stefano Santi, Bill Lin 0001, Ljupco Kocarev, Gian Mario Maggio, Riccardo Rovatti, Gianluca Setti	On the impact of traffic statistics on quality of service for networks on chip.	ISCAS (3)	2005	DBLP DOI BibTeX RDF