Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
160 | Rajesh Garg, Sunil P. Khatri |
Generalized buffering of PTL logic stages using Boolean division. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
132 | Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Logic synthesis for large pass transistor circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 663-670, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
logic synthesis, BDD, Pass transistor logic |
127 | Geun Rae Cho, Tom Chen 0001 |
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2), pp. 229-242, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
121 | Geun Rae Cho, Tom Chen 0001 |
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 3rd International Symposium on Quality of Electronic Design, ISQED 2002, San Jose, CA, USA, March 18-21, 2002, pp. 458-463, 2002, IEEE Computer Society, 0-7695-1561-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic |
110 | Congguang Yang, Maciej J. Ciesielski |
Synthesis for Mixed CMOS/PTl Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 750, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
110 | P. S. Thiagarajan |
A Trace Consistent Subset of PTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONCUR ![In: CONCUR '95: Concurrency Theory, 6th International Conference, Philadelphia, PA, USA, August 21-24, 1995, Proceedings, pp. 438-452, 1995, Springer, 3-540-60218-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
99 | Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen |
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 1631-1634, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
93 | Debasis Samanta, Ajit Pal |
Synthesis of Low Power High Performance Dual-VT PTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 85-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
93 | Geun Rae Cho, Tom Chen 0001 |
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 513-, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
93 | Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien |
A Method for Synthesizing Area Efficient Multilevel PTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 516-519, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
multilevel logic synthesis, logic synthesis, Pass transistor logic |
83 | Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen |
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2433-2436, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
83 | Geun Rae Cho, Tom Chen 0001 |
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA, pp. 55-60, 2003, IEEE Computer Society, 0-7695-1881-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
83 | Christoph Scholl 0001, Bernd Becker 0001 |
On the Generation of Multiplexer Circuits for Pass Transistor Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 372-378, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
77 | Arunita Jaekel, Graham A. Jullien, Subir Bandyopadhyay |
Multilevel Factorization Technique for Pass Transistor Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 339-340, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
algebraic factorization, PTL networks, pass transistor logic |
77 | Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu |
BDD decomposition for mixed CMOS/PTL logic circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5649-5652, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
66 | Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen |
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2022-2025, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
66 | Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji |
Technology mapping for high-performance static CMOS and pass transistor logic designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(5), pp. 577-589, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
60 | Geun Rae Cho, Tom Chen 0001 |
On The Impact of Technology Scaling On Mixed PTL/Static Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 322-326, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
50 | Shaoning Pang, Tao Ban, Youki Kadobayashi, Nikola K. Kasabov |
Spanning SVM Tree for Personalized Transductive Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (1) ![In: Artificial Neural Networks - ICANN 2009, 19th International Conference, Limassol, Cyprus, September 14-17, 2009, Proceedings, Part I, pp. 913-922, 2009, Springer, 978-3-642-04273-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
50 | Zhenhua Duan, Cong Tian |
A Unified Model Checking Approach with Projection Temporal Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 10th International Conference on Formal Engineering Methods, ICFEM 2008, Kitakyushu-City, Japan, October 27-31, 2008. Proceedings, pp. 167-186, 2008, Springer, 978-3-540-88193-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Ming-Hsien Tsai 0001, Bow-Yaw Wang |
Formalization of CTL* in Calculus of Inductive Constructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASIAN ![In: Advances in Computer Science - ASIAN 2006. Secure Software and Related Issues, 11th Asian Computing Science Conference, Tokyo, Japan, December 6-8, 2006, Revised Selected Papers, pp. 316-330, 2006, Springer, 978-3-540-77504-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler |
Minimization of the expected path length in BDDs based on local changes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 865-870, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Arindam Mukherjee 0001, Malgorzata Marek-Sadowska |
Wave steering to integrate logic and physical syntheses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(1), pp. 105-120, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Mutlu Avci, Tülay Yildirim |
A coding method for 123 decision diagram pass transistor logic circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 189-192, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Hong Jo Ahn, Mohammed Ismail 0001 |
GHz programmable dual-modulus prescaler for multi-standard wireless applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 137-140, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner |
Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 477-480, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Rupesh S. Shelar, Sachin S. Sapatnekar |
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 87-92, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Low Power, Logic Synthesis, Pass Transistor Logic |
33 | Hai Zhou 0001, Adnan Aziz |
Buffer minimization in pass transistor logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5), pp. 693-697, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | John A. Keane, Walter Hussak |
A Method of Verification in Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 4-7 January, 2000, Maui, Hawaii, USA, 2000, IEEE Computer Society, 0-7695-0493-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
33 | Ramaswamy Ramanujam |
Trace Consistency and Inevitablity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, 16th Conference, Hyderabad, India, December 18-20, 1996, Proceedings, pp. 250-261, 1996, Springer, 3-540-62034-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
33 | Mohsin Ahmed, G. Venkatesh |
A Propositional Dense Time Logic (Based on Nested Sequences). ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAPSOFT ![In: TAPSOFT'93: Theory and Practice of Software Development, International Joint Conference CAAP/FASE, Orsay, France, April 13-17, 1993, Proceedings, pp. 584-598, 1993, Springer, 3-540-56610-4. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
ordinal trees, Temporal logic, dense time |
33 | Eric Nassor, Guy Vidal-Naquet |
Suitability of the Propositional Temporal Logic to Express Properties of Real-Time Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STACS ![In: STACS 92, 9th Annual Symposium on Theoretical Aspects of Computer Science, Cachan, France, February 13-15, 1992, Proceedings, pp. 59-70, 1992, Springer, 3-540-55210-3. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
33 | A. A. Aaby, K. T. Narayana |
Propositional Temporal Interval Logic is PSPACE Complete. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CADE ![In: 9th International Conference on Automated Deduction, Argonne, Illinois, USA, May 23-26, 1988, Proceedings, pp. 218-237, 1988, Springer, 3-540-19343-X. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
33 | D. Lippert |
Interval Temporal Logic and Star-Free Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSL ![In: CSL '88, 2nd Workshop on Computer Science Logic, Duisburg, Germany, October 3-7, 1988, Proceedings, pp. 187-198, 1988, Springer, 3-540-51659-X. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
28 | Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider |
A comparative study of CMOS gates with minimum transistor stacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007, pp. 93-98, 2007, ACM, 978-1-59593-816-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates |
28 | Leomar S. da Rosa Jr., Felipe S. Marques 0001, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis |
Fast disjoint transistor networks from BDDs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 137-142, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
PTL, unateness, BDDs, switch theory, CMOS gates |
28 | Farn Wang, Aloysius K. Mok, E. Allen Emerson |
Formal Specification of Ssynchronous Distributed Real-Time Systems by APTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSE ![In: Proceedings of the 14th International Conference on Software Engineering, Melbourne, Australia, May 11-15, 1992., pp. 188-198, 1992, ACM Press, 0-89791-504-6. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
PTL |
27 | Clare Dixon, Michael Fisher 0001, Boris Konev |
Is There a Future for Deductive Temporal Verification? ![Search on Bibsonomy](Pics/bibsonomy.png) |
TIME ![In: 13th International Symposium on Temporal Representation and Reasoning (TIME 2006), 15-17 June 2006, Budapest, Hungary, pp. 11-18, 2006, IEEE Computer Society, 0-7695-2617-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fragments of PTL, deductive verification, clausal temporal resolution, complexity |
27 | Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, Gaurav Kumar |
Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Perform. Eng. ![In: Int. J. Perform. Eng. 18(1), pp. 22, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour |
Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Circuits Devices Syst. ![In: IET Circuits Devices Syst. 16(6), pp. 437-460, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001 |
Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(18), pp. 2292001:1-2292001:2, December 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001 |
High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 31(11), pp. 2250200:1-2250200:16, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | Frederico Santos de Oliveira, Marcelo de Carvalho, Pedro Henrique Tancredo Campos, Anderson da Silva Soares, Arnaldo Cândido Júnior, Ana Cláudia Rodrigues Da Silva Quirino |
PTL-AI Furnas Dataset: A Public Dataset for Fault Detection in Power Transmission Lines Using Aerial Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIBGRAPI ![In: 35th SIBGRAPI Conference on Graphics, Patterns and Images, SIBGRAPI 2022, Natal, Brazil, October 24-27, 2022, pp. 7-12, 2022, IEEE, 978-1-6654-5385-1. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
27 | M. Rahimi, M. B. Ghaznavi-Ghoushchi |
A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 113, pp. 105086, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Xiaoliang Zheng, Gongping Wu |
Kinodynamic planning with reachability prediction for PTL maintenance robot. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Syst. Control. Eng. ![In: J. Syst. Control. Eng. 235(8), 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Anju Rajput, Tripti Dua, Renu Kumawat, Avireni Srinivasulu |
Novel CMOS and PTL Based Half Subtractor Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iSES ![In: IEEE International Symposium on Smart Electronic Systems, iSES 2021, Jaipur, India, December 18-22, 2021, pp. 165-168, 2021, IEEE, 978-1-7281-8753-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
27 | Ming Tong, He Bai 0010, Xing Yue, Haili Bu |
PTL-LTM model for complex action recognition using local-weighted NMF and deep dual-manifold regularized NMF with sparsity constraint. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 32(17), pp. 13759-13781, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
27 | Youngjoo Kim, Soondo Hong |
Two Picker Cooperation Strategies for Zone Picking Systems With PTL Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 106059-106070, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
27 | Chandan Kumar Jha 0001, Joycee Mekie |
Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 22nd Euromicro Conference on Digital System Design, DSD 2019, Kallithea, Greece, August 28-30, 2019, pp. 174-181, 2019, IEEE, 978-1-7281-2862-7. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
27 | Georg Zetzsche |
PTL-separability and closures for WQOs on words. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1802.07397, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
27 | Xiaodong Yu, Hongbin Dong |
PTL-CFS based deep convolutional neural network model for remote sensing classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computing ![In: Computing 100(8), pp. 773-785, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
27 | Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee |
Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018, pp. 190-195, 2018, IEEE Computer Society, 978-1-5386-7377-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
27 | Jesús Manuel Almendros-Jiménez, Luis Iribarne, Jesús J. López-Fernández, Ángel Mora Segura |
PTL: A model transformation language based on logic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Log. Algebraic Methods Program. ![In: J. Log. Algebraic Methods Program. 85(2), pp. 332-366, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
27 | Richard Booth 0001, Giovanni Casini, Thomas Meyer 0002, Ivan José Varzinczak |
What Does Entailment for PTL Mean? ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAAI Spring Symposia ![In: 2015 AAAI Spring Symposia, Stanford University, Palo Alto, California, USA, March 22-25, 2015, 2015, AAAI Press. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
27 | Gyu Sang Choi, Byung-Won On, Kwonhue Choi, Sungwon Yi |
PTL: PRAM translation layer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 37(1), pp. 24-32, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
27 | Zili Shao, Naehyuck Chang, Nikil D. Dutt |
PTL: PCM Translation Layer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012, pp. 380-385, 2012, IEEE Computer Society, 978-1-4673-2234-8. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
27 | Robin Jun Yang, Qiong Luo 0001 |
PTL: Partitioned Logging for Database Storage on Flash Solid State Drives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WAIM Workshops ![In: Web-Age Information Management - WAIM 2012 International Workshops: GDMM, IWSN, MDSP, USDM, and XMLDM Harbin, China, August 18-20, 2012 Proceedings, pp. 99-108, 2012, Springer, 978-3-642-33049-0. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
27 | Richard Booth 0001, Thomas Meyer 0002, Ivan José Varzinczak |
PTL: A Propositional Typicality Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JELIA ![In: Logics in Artificial Intelligence - 13th European Conference, JELIA 2012, Toulouse, France, September 26-28, 2012. Proceedings, pp. 107-119, 2012, Springer, 978-3-642-33352-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
27 | Chi-Chou Kao |
BDD-based synthesis for mixed CMOS/PTL logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 39(9), pp. 923-932, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
27 | Damien Henry |
PTL, a new sequencer dedicated to graphical scores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMC ![In: Proceedings of the 2004 International Computer Music Conference, ICMC 2004, Miami, Florida, USA, November 1-6, 2004, 2004, Michigan Publishing. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
27 | Debasis Samanta, M. C. Dharmadeep, Ajit Pal |
Synthesis of high performance low power PTL circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 209-212, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Geun Rae Cho, Tom Chen 0001 |
Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEAL ![In: Recent Advances in Simulated Evolution and Learning [extended and revised papers selected from the 4th Asia-Pacific Conference on Simulated Evolution and Learning, SEAL 2002, 18-22 November 2002, Singapore]., pp. 446-465, 2002, World Scientific, 978-981-238-952-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Geun Rae Cho, Tom Chen 0001 |
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWLS ![In: 11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA., pp. 289-294, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
27 | Geun Rae Cho, Tom Chen 0001 |
On Mixed PTL/Static Logic for Low-power and High-speed Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 12(3), pp. 399-406, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Annabelle McIver, Carroll Morgan |
Almost-Certain Eventualities and Abstract Probabilities in the Temporal Logic PTL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CATS ![In: Computing: The Australasian Theory Symposium, CATS 2001, Gold Coast, Australia, January 29-30, 2001, pp. 12-40, 2001, Elsevier. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Luca Macchiarulo, Luca Benini, Enrico Macii |
On-the-fly layout generation for PTL macrocells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 546-551, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
27 | Anton Betten, Adalbert Kerber, Axel Kohnert, Reinhard Laue, Alfred Wassermann |
The Discovery of Simple 7-Designs with Automorphism Group PTL (2, 32). ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAECC ![In: Applied Algebra, Algebraic Algorithms and Error-Correcting Codes, 11th International Symposium, AAECC-11, Paris, France, July 17-22, 1995, Proceedings, pp. 131-145, 1995, Springer, 3-540-60114-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
17 | Clare Dixon, Michael Fisher 0001, Boris Konev |
Temporal Logic with Capacity Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FroCoS ![In: Frontiers of Combining Systems, 6th International Symposium, FroCoS 2007, Liverpool, UK, September 10-12, 2007, Proceedings, pp. 163-177, 2007, Springer, 978-3-540-74620-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ilya Obridko, Ran Ginosar |
Minimal Energy Asynchronous Dynamic Adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(9), pp. 1043-1047, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
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17 | P. W. Chandana Prasad, Bruce Mills, Ali Assi 0001, S. M. N. Arosha Senanayake, V. C. Prasad |
Evaluation time Estimation for Pass Transistor Logic circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 422-428, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai |
High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 614-617, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Rupesh S. Shelar, Sachin S. Sapatnekar |
BDD decomposition for delay oriented pass transistor logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(8), pp. 957-970, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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17 | Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis |
Exact lower bound for the number of switches in series to implement a combinational logic cell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 357-362, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Paul Horng-Jyh Wu, Jin-Cheon Na, Christopher S. G. Khoo |
NLP Versus IR Approaches to Fuzzy Name Searching in Digital Libraries. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECDL ![In: Research and Advanced Technology for Digital Libraries, 8th European Conference, ECDL 2004, Bath, UK, September 12-17, 2004, Proceedings, pp. 145-156, 2004, Springer, 3-540-23013-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Michael A. Riepe, Karem A. Sakallah |
Transistor placement for noncomplementary digital VLSI cell synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 8(1), pp. 81-107, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Cell Synthesis, Euler graphs, noncomplementary circuits, sequence pair optimization, transistor chaining, transistor placement, digital circuits, benchmark circuits |
17 | Ben C. Moszkowski |
A Hierarchical Completeness Proof for Propositional Temporal Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Verification: Theory and Practice ![In: Verification: Theory and Practice, Essays Dedicated to Zohar Manna on the Occasion of His 64th Birthday, pp. 480-523, 2003, Springer, 3-540-21002-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
17 | Carsten Lutz, Holger Sturm, Frank Wolter, Michael Zakharyaschev |
Tableaux for Temporal Description Logic with Constant Domains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCAR ![In: Automated Reasoning, First International Joint Conference, IJCAR 2001, Siena, Italy, June 18-23, 2001, Proceedings, pp. 121-136, 2001, Springer, 3-540-42254-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
17 | Stephan Merz |
Weak Alternating Automata in Isabelle/HOL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Theorem Proving in Higher Order Logics, 13th International Conference, TPHOLs 2000, Portland, Oregon, USA, August 14-18, 2000, Proceedings, pp. 424-441, 2000, Springer, 3-540-67863-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
17 | S. Purushothaman Iyer, Murali Narasimha |
Probabilistic Lossy Channel Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAPSOFT ![In: TAPSOFT'97: Theory and Practice of Software Development, 7th International Joint Conference CAAP/FASE, Lille, France, April 14-18, 1997, Proceedings, pp. 667-681, 1997, Springer, 3-540-62781-2. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
17 | Parosh Aziz Abdulla, Bengt Jonsson 0001 |
Undecidable Verification Problems for Programs with Unreliable Channels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP ![In: Automata, Languages and Programming, 21st International Colloquium, ICALP94, Jerusalem, Israel, July 11-14, 1994, Proceedings, pp. 316-327, 1994, Springer, 3-540-58201-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
17 | Gjalt G. de Jong |
An Automata Theoretic Approach to Temporal Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 3rd International Workshop, CAV '91, Aalborg, Denmark, July, 1-4, 1991, Proceedings, pp. 477-487, 1991, Springer, 3-540-55179-4. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|