Search results for "PTL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
160	Rajesh Garg, Sunil P. Khatri	Generalized buffering of PTL logic stages using Boolean division.	ISCAS	2006	DBLP DOI BibTeX RDF
132	Premal Buch, Amit Narayan, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	Logic synthesis for large pass transistor circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	logic synthesis, BDD, Pass transistor logic
127	Geun Rae Cho, Tom Chen 0001	Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
121	Geun Rae Cho, Tom Chen 0001	Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications.	ISQED	2002	DBLP DOI BibTeX RDF	Mixed PTL/Static, Lower-Power Technology Mapping, Logic Synthesis, Pass Transistor Logic
110	Congguang Yang, Maciej J. Ciesielski	Synthesis for Mixed CMOS/PTl Logic.	DATE	2000	DBLP DOI BibTeX RDF
110	P. S. Thiagarajan	A Trace Consistent Subset of PTL.	CONCUR	1995	DBLP DOI BibTeX RDF
99	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
93	Debasis Samanta, Ajit Pal	Synthesis of Low Power High Performance Dual-VT PTL Circuits.	VLSI Design	2004	DBLP DOI BibTeX RDF
93	Geun Rae Cho, Tom Chen 0001	On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.	VLSI Design	2003	DBLP DOI BibTeX RDF
93	Subir Bandyopadhyay, Arunita Jaekel, Graham A. Jullien	A Method for Synthesizing Area Efficient Multilevel PTL Circuits.	VLSI Design	1997	DBLP DOI BibTeX RDF	multilevel logic synthesis, logic synthesis, Pass transistor logic
83	Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen	An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
83	Geun Rae Cho, Tom Chen 0001	Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic.	ISQED	2003	DBLP DOI BibTeX RDF
83	Christoph Scholl 0001, Bernd Becker 0001	On the Generation of Multiplexer Circuits for Pass Transistor Logic.	DATE	2000	DBLP DOI BibTeX RDF
77	Arunita Jaekel, Graham A. Jullien, Subir Bandyopadhyay	Multilevel Factorization Technique for Pass Transistor Logic.	VLSI Design	1996	DBLP DOI BibTeX RDF	algebraic factorization, PTL networks, pass transistor logic
77	Yen-Tai Lai, Yung-Chuan Jiang, Hong-Ming Chu	BDD decomposition for mixed CMOS/PTL logic circuit synthesis.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
66	Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen	Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.	ISCAS	2008	DBLP DOI BibTeX RDF
66	Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji	Technology mapping for high-performance static CMOS and pass transistor logic designs.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
60	Geun Rae Cho, Tom Chen 0001	On The Impact of Technology Scaling On Mixed PTL/Static Circuits.	ICCD	2002	DBLP DOI BibTeX RDF
50	Shaoning Pang, Tao Ban, Youki Kadobayashi, Nikola K. Kasabov	Spanning SVM Tree for Personalized Transductive Learning.	ICANN (1)	2009	DBLP DOI BibTeX RDF
50	Zhenhua Duan, Cong Tian	A Unified Model Checking Approach with Projection Temporal Logic.	ICFEM	2008	DBLP DOI BibTeX RDF
33	Ming-Hsien Tsai 0001, Bow-Yaw Wang	Formalization of CTL* in Calculus of Inductive Constructions.	ASIAN	2006	DBLP DOI BibTeX RDF
33	Rüdiger Ebendt, Wolfgang Günther 0001, Rolf Drechsler	Minimization of the expected path length in BDDs based on local changes.	ASP-DAC	2004	DBLP DOI BibTeX RDF
33	Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	Wave steering to integrate logic and physical syntheses.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
33	Mutlu Avci, Tülay Yildirim	A coding method for 123 decision diagram pass transistor logic circuit synthesis.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
33	Hong Jo Ahn, Mohammed Ismail 0001	GHz programmable dual-modulus prescaler for multi-standard wireless applications.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
33	Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner	Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
33	Rupesh S. Shelar, Sachin S. Sapatnekar	An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Low Power, Logic Synthesis, Pass Transistor Logic
33	Hai Zhou 0001, Adnan Aziz	Buffer minimization in pass transistor logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
33	John A. Keane, Walter Hussak	A Method of Verification in Design.	HICSS	2000	DBLP DOI BibTeX RDF
33	Ramaswamy Ramanujam	Trace Consistency and Inevitablity.	FSTTCS	1996	DBLP DOI BibTeX RDF
33	Mohsin Ahmed, G. Venkatesh	A Propositional Dense Time Logic (Based on Nested Sequences).	TAPSOFT	1993	DBLP DOI BibTeX RDF	ordinal trees, Temporal logic, dense time
33	Eric Nassor, Guy Vidal-Naquet	Suitability of the Propositional Temporal Logic to Express Properties of Real-Time Systems.	STACS	1992	DBLP DOI BibTeX RDF
33	A. A. Aaby, K. T. Narayana	Propositional Temporal Interval Logic is PSPACE Complete.	CADE	1988	DBLP DOI BibTeX RDF
33	D. Lippert	Interval Temporal Logic and Star-Free Expressions.	CSL	1988	DBLP DOI BibTeX RDF
28	Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider	A comparative study of CMOS gates with minimum transistor stacks.	SBCCI	2007	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, technology mapping, switch theory, logical effort, CMOS gates
28	Leomar S. da Rosa Jr., Felipe S. Marques 0001, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	Fast disjoint transistor networks from BDDs.	SBCCI	2006	DBLP DOI BibTeX RDF	PTL, unateness, BDDs, switch theory, CMOS gates
28	Farn Wang, Aloysius K. Mok, E. Allen Emerson	Formal Specification of Ssynchronous Distributed Real-Time Systems by APTL.	ICSE	1992	DBLP DOI BibTeX RDF	PTL
27	Clare Dixon, Michael Fisher 0001, Boris Konev	Is There a Future for Deductive Temporal Verification?	TIME	2006	DBLP DOI BibTeX RDF	fragments of PTL, deductive verification, clausal temporal resolution, complexity
27	Sandeep Dhariwal, Reeba Korah, Ravi Shankar Mishra, Gaurav Kumar	Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications.	Int. J. Perform. Eng.	2022	DBLP DOI BibTeX RDF
27	Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour	Tolerant and low power subtractor with 4: 2 compressor and a new TG-PTL-float full adder cell.	IET Circuits Devices Syst.	2022	DBLP DOI BibTeX RDF
27	Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001	Erratum: High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
27	Avadhoot Khairnar, Bhavuk Chauhan, Geetanjali Sharma, Amit M. Joshi 0001	High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic.	J. Circuits Syst. Comput.	2022	DBLP DOI BibTeX RDF
27	Frederico Santos de Oliveira, Marcelo de Carvalho, Pedro Henrique Tancredo Campos, Anderson da Silva Soares, Arnaldo Cândido Júnior, Ana Cláudia Rodrigues Da Silva Quirino	PTL-AI Furnas Dataset: A Public Dataset for Fault Detection in Power Transmission Lines Using Aerial Images.	SIBGRAPI	2022	DBLP DOI BibTeX RDF
27	M. Rahimi, M. B. Ghaznavi-Ghoushchi	A fanout-improved Parallel Prefix Adder with full-swing PTL cells and Graded Bit Efficiency.	Microelectron. J.	2021	DBLP DOI BibTeX RDF
27	Xiaoliang Zheng, Gongping Wu	Kinodynamic planning with reachability prediction for PTL maintenance robot.	J. Syst. Control. Eng.	2021	DBLP DOI BibTeX RDF
27	Anju Rajput, Tripti Dua, Renu Kumawat, Avireni Srinivasulu	Novel CMOS and PTL Based Half Subtractor Designs.	iSES	2021	DBLP DOI BibTeX RDF
27	Ming Tong, He Bai 0010, Xing Yue, Haili Bu	PTL-LTM model for complex action recognition using local-weighted NMF and deep dual-manifold regularized NMF with sparsity constraint.	Neural Comput. Appl.	2020	DBLP DOI BibTeX RDF
27	Youngjoo Kim, Soondo Hong	Two Picker Cooperation Strategies for Zone Picking Systems With PTL Technology.	IEEE Access	2020	DBLP DOI BibTeX RDF
27	Chandan Kumar Jha 0001, Joycee Mekie	Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based Designs.	DSD	2019	DBLP DOI BibTeX RDF
27	Georg Zetzsche	PTL-separability and closures for WQOs on words.	CoRR	2018	DBLP BibTeX RDF
27	Xiaodong Yu, Hongbin Dong	PTL-CFS based deep convolutional neural network model for remote sensing classification.	Computing	2018	DBLP DOI BibTeX RDF
27	Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee	Error Correctable Approximate Multiplier with Area/Power Efficient Design Through Mixed CMOS/PTL.	DSD	2018	DBLP DOI BibTeX RDF
27	Jesús Manuel Almendros-Jiménez, Luis Iribarne, Jesús J. López-Fernández, Ángel Mora Segura	PTL: A model transformation language based on logic programming.	J. Log. Algebraic Methods Program.	2016	DBLP DOI BibTeX RDF
27	Richard Booth 0001, Giovanni Casini, Thomas Meyer 0002, Ivan José Varzinczak	What Does Entailment for PTL Mean?	AAAI Spring Symposia	2015	DBLP BibTeX RDF
27	Gyu Sang Choi, Byung-Won On, Kwonhue Choi, Sungwon Yi	PTL: PRAM translation layer.	Microprocess. Microsystems	2013	DBLP DOI BibTeX RDF
27	Zili Shao, Naehyuck Chang, Nikil D. Dutt	PTL: PCM Translation Layer.	ISVLSI	2012	DBLP DOI BibTeX RDF
27	Robin Jun Yang, Qiong Luo 0001	PTL: Partitioned Logging for Database Storage on Flash Solid State Drives.	WAIM Workshops	2012	DBLP DOI BibTeX RDF
27	Richard Booth 0001, Thomas Meyer 0002, Ivan José Varzinczak	PTL: A Propositional Typicality Logic.	JELIA	2012	DBLP DOI BibTeX RDF
27	Chi-Chou Kao	BDD-based synthesis for mixed CMOS/PTL logic.	Int. J. Circuit Theory Appl.	2011	DBLP DOI BibTeX RDF
27	Damien Henry	PTL, a new sequencer dedicated to graphical scores.	ICMC	2004	DBLP BibTeX RDF
27	Debasis Samanta, M. C. Dharmadeep, Ajit Pal	Synthesis of high performance low power PTL circuits.	ASP-DAC	2003	DBLP DOI BibTeX RDF
27	Geun Rae Cho, Tom Chen 0001	Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications.	SEAL	2002	DBLP DOI BibTeX RDF
27	Geun Rae Cho, Tom Chen 0001	On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis.	IWLS	2002	DBLP BibTeX RDF
27	Geun Rae Cho, Tom Chen 0001	On Mixed PTL/Static Logic for Low-power and High-speed Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
27	Annabelle McIver, Carroll Morgan	Almost-Certain Eventualities and Abstract Probabilities in the Temporal Logic PTL.	CATS	2001	DBLP DOI BibTeX RDF
27	Luca Macchiarulo, Luca Benini, Enrico Macii	On-the-fly layout generation for PTL macrocells.	DATE	2001	DBLP DOI BibTeX RDF
27	Anton Betten, Adalbert Kerber, Axel Kohnert, Reinhard Laue, Alfred Wassermann	The Discovery of Simple 7-Designs with Automorphism Group PTL (2, 32).	AAECC	1995	DBLP DOI BibTeX RDF
17	Clare Dixon, Michael Fisher 0001, Boris Konev	Temporal Logic with Capacity Constraints.	FroCoS	2007	DBLP DOI BibTeX RDF
17	Ilya Obridko, Ran Ginosar	Minimal Energy Asynchronous Dynamic Adders.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
17	P. W. Chandana Prasad, Bruce Mills, Ali Assi 0001, S. M. N. Arosha Senanayake, V. C. Prasad	Evaluation time Estimation for Pass Transistor Logic circuits.	DELTA	2006	DBLP DOI BibTeX RDF
17	Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai	High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability.	APCCAS	2006	DBLP DOI BibTeX RDF
17	Rupesh S. Shelar, Sachin S. Sapatnekar	BDD decomposition for delay oriented pass transistor logic synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
17	Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis	Exact lower bound for the number of switches in series to implement a combinational logic cell.	ICCD	2005	DBLP DOI BibTeX RDF
17	Paul Horng-Jyh Wu, Jin-Cheon Na, Christopher S. G. Khoo	NLP Versus IR Approaches to Fuzzy Name Searching in Digital Libraries.	ECDL	2004	DBLP DOI BibTeX RDF
17	Michael A. Riepe, Karem A. Sakallah	Transistor placement for noncomplementary digital VLSI cell synthesis.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Cell Synthesis, Euler graphs, noncomplementary circuits, sequence pair optimization, transistor chaining, transistor placement, digital circuits, benchmark circuits
17	Ben C. Moszkowski	A Hierarchical Completeness Proof for Propositional Temporal Logic.	Verification: Theory and Practice	2003	DBLP DOI BibTeX RDF
17	Carsten Lutz, Holger Sturm, Frank Wolter, Michael Zakharyaschev	Tableaux for Temporal Description Logic with Constant Domains.	IJCAR	2001	DBLP DOI BibTeX RDF
17	Stephan Merz	Weak Alternating Automata in Isabelle/HOL.	TPHOLs	2000	DBLP DOI BibTeX RDF
17	S. Purushothaman Iyer, Murali Narasimha	Probabilistic Lossy Channel Systems.	TAPSOFT	1997	DBLP DOI BibTeX RDF
17	Parosh Aziz Abdulla, Bengt Jonsson 0001	Undecidable Verification Problems for Programs with Unreliable Channels.	ICALP	1994	DBLP DOI BibTeX RDF
17	Gjalt G. de Jong	An Automata Theoretic Approach to Temporal Logic.	CAV	1991	DBLP DOI BibTeX RDF