Search results for "RSP"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
86	Randall S. Janka, Linda M. Wills	Combining Virtual Benchmarking with Rapid System Prototyping for Real-Time Embedded Multiprocessor Signal Processing System Codesign.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	signal processor, specification and design methodology, middleware, multiprocessor, embedded, rapid prototyping, codesign
61	M. Ümit Uyar, Jianliang Zheng, Mariusz A. Fecko, Sunil Samtani, Phillip T. Conrad	Evaluation of architectures for reliable server pooling in wired and wireless environments.	IEEE J. Sel. Areas Commun.	2004	DBLP DOI BibTeX RDF
61	Steve Carr 0001, Philip H. Sweany	Automatic data partitioning for the agere payload plus network processor.	CASES	2004	DBLP DOI BibTeX RDF	scheduling, partitioning, network processors
61	Randall S. Janka, Linda M. Wills, Lewis Benton Baumstark Jr.	Virtual Benchmarking and Model Continuity in Prototyping Embedded Multiprocessor Signal Processing Systems.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	model continuity, open-standards middleware, specification and design methodology, Hardware/software codesign
53	Fernando A. Kuipers, Ariel Orda, Danny Raz, Piet Van Mieghem	A Comparison of Exact and epsilon-Approximation Algorithms for Constrained Routing.	Networking	2006	DBLP DOI BibTeX RDF	RSP algorithms, performance evaluation, QoS routing
50	Tae Jong Choi, Chang Wook Ahn	An improved LSHADE-RSP algorithm with the Cauchy perturbation: iLSHADE-RSP.	Knowl. Based Syst.	2021	DBLP DOI BibTeX RDF
50	Tae Jong Choi, Chang Wook Ahn	An Improved LSHADE-RSP Algorithm with the Cauchy Perturbation: iLSHADE-RSP.	CoRR	2020	DBLP BibTeX RDF
50	Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir	Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
45	Natalino G. Busá, Ghiath Alkadi, Michael J. Verberne, Rafael Peset Llopis, Sethuraman Ramanatha	RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
44		IEEE International Workshop on Rapid System Prototyping, RSP 2022, Shanghai, China, October 13, 2022	RSP	2022	DBLP DOI BibTeX RDF
44	Arthur Vianès, Frédéric Pétrot, Frédéric Rousseau 0001	A Case for Second-Level Software Cache Coherency on Many-Core Accelerators.	RSP	2022	DBLP DOI BibTeX RDF
44	Z. Ning, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet	Enhancing embedded AI-based object detection using multi-view approach.	RSP	2022	DBLP DOI BibTeX RDF
44	Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler	ANN-based Performance Estimation of Embedded Software for RISC-V Processors.	RSP	2022	DBLP DOI BibTeX RDF
44	Jakob Wenzel 0002, Christian Hochberger	Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis.	RSP	2022	DBLP DOI BibTeX RDF
44	Gabriel Rutsch, Maximilian Groebner, Anthony Sanders, Konrad Maier, Wolfgang Ecker	A framework that enables systematic analysis of mixed-signal applications on FPGA.	RSP	2022	DBLP DOI BibTeX RDF
44	Martim Rosado, Stavros Mallios, Pedro Tomás, Nuno Roma, André David	Early prototyping and testing of CERN LHC CMS high-granularity calorimeter slow-control system.	RSP	2022	DBLP DOI BibTeX RDF
44	Ritwik Sinha, Seyed Alireza Damghani, Kenneth B. Kent	Machine Learning-Based Hard/Soft Logic Trade-offs in VTR.	RSP	2022	DBLP DOI BibTeX RDF
44	Dominique Heller, Mostafa Rizk, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet	Marine Objects Detection Using Deep Learning on Embedded Edge Devices.	RSP	2022	DBLP DOI BibTeX RDF
44	Seungyeop Kang, Sungjoo Yoo	TernaryNeRF: Quantizing Voxel Grid-based NeRF Models.	RSP	2022	DBLP DOI BibTeX RDF
44		IEEE International Workshop on Rapid System Prototyping, RSP 2021, Paris, France, October 14, 2021	RSP	2021	DBLP DOI BibTeX RDF
44	Felipe Göhring de Magalhães, Mahdi Nikdast, Fabiano Hessel, Odile Liboiron-Ladouceur, Gabriela Nicolescu	HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks.	RSP	2021	DBLP DOI BibTeX RDF
44	Harpreet Kaur, Georgiy Krylov, Seyed Alireza Damghani, Kenneth B. Kent	Heterogeneous Logic Implementation for Adders in VTR.	RSP	2021	DBLP DOI BibTeX RDF
44	Theo Soriano, David Novo, Pascal Benoit	An FPGA-based Emulation Platform for Edge Computing Node Design Exploration.	RSP	2021	DBLP DOI BibTeX RDF
44	Bruno Ferres, Olivier Muller, Frédéric Rousseau 0001	Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration.	RSP	2021	DBLP DOI BibTeX RDF
44	Kevin Mambu, Henri-Pierre Charles, Julie Dumas, Maha Kooli	Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator.	RSP	2021	DBLP DOI BibTeX RDF
44	Loïc France, Florent Bruguier, Maria Mushtaq, David Novo, Pascal Benoit	Implementing Rowhammer Memory Corruption in the gem5 Simulator.	RSP	2021	DBLP DOI BibTeX RDF
44	Nils Büscher, Daniel Gis, Johann-Peter Wolff, Christian Haubelt	Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping Platform.	RSP	2021	DBLP DOI BibTeX RDF
44	Théotime Bollengier, Loïc Lagadec, Ciprian Teodorov	Prototyping FPGA through overlays.	RSP	2021	DBLP DOI BibTeX RDF
44	Soobeom Kim, Seunghwan Cho, Eunhyeok Park, Sungjoo Yoo	FPGA Prototyping of Systolic Array-based Accelerator for Low-Precision Inference of Deep Neural Networks.	RSP	2021	DBLP DOI BibTeX RDF
44	Kevin Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker 0001, Max E. Kramer, Clemens Reichmann	Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation.	RSP	2021	DBLP DOI BibTeX RDF
44		International Workshop on Rapid System Prototyping, RSP 2020, Hamburg, Germany, September 24-25, 2020	RSP	2020	DBLP BibTeX RDF
44	Jean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot	(System)Verilog to Chisel Translation for Faster Hardware Design.	RSP	2020	DBLP DOI BibTeX RDF
44	Jérémy Nadal, Amer Baghdadi	FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding.	RSP	2020	DBLP DOI BibTeX RDF
44	Erwan Moréac, El Mehdi Abdali, François Berry, Dominique Heller, Jean-Philippe Diguet	Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAV.	RSP	2020	DBLP DOI BibTeX RDF
44	Chen Wu, Virginie Fresse, Benoît Suffran, Hubert Konik	Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing cluster.	RSP	2020	DBLP DOI BibTeX RDF
44	Erwan Lenormand, Thierry Goubier, Loïc Cudennec, Henri-Pierre Charles	A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management.	RSP	2020	DBLP DOI BibTeX RDF
44	Xuzhi Zhang, Narendra Prabhu, Russell Tessier	NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks.	RSP	2020	DBLP DOI BibTeX RDF
44	José D. Domingues, Fábio D. L. Coutinho, Pedro M. C. Marques, Samuel Santos Pereira, Hugerles S. Silva, Arnaldo S. R. Oliveira	MPSoC Fast Prototyping of a Reconfigurable DU Downlink Transmission Chain for 5G New Radio.	RSP	2020	DBLP DOI BibTeX RDF
44	Seyed Alireza Damghani, Jean-Philippe Legault, Kenneth B. Kent	Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin II.	RSP	2020	DBLP DOI BibTeX RDF
44	Daniel Gis, Nils Büscher, Christian Haubelt	Advanced Debugging Architecture for Smart Inertial Sensors using Sensor-in-the-Loop.	RSP	2020	DBLP DOI BibTeX RDF
44		Proceedings of the 30th International Workshop on Rapid System Prototyping, RSP 2019, New York, NY, USA, October 17-18, 2019.	RSP	2019	DBLP DOI BibTeX RDF
44	Artur Rataj, Etienne Borde	Fast and robust modelling using a direct translation from a robotic application to its abstracted behaviour.	RSP	2019	DBLP DOI BibTeX RDF
44	Keita Miura, Shota Tokunaga, Noriyuki Ota, Yoshiharu Tange, Takuya Azumi	Autoware Toolbox: MATLAB/Simulink Benchmark Suite for ROS-based Self-driving Software Platform.	RSP	2019	DBLP DOI BibTeX RDF
44	Louis Bonicel, Roland Bohrer, Benoit Leprettre, Frédéric Rousseau 0001, Frédéric Pétrot	Multi-Triggered Embedded Software Code Generation for Electrical Metering and Protection Applications.	RSP	2019	DBLP DOI BibTeX RDF
44	Derek Yu, Michael Vaquier, Evan Laflamme, Gabrielle Doucette-Poirier, Justin Tremblay, Brett H. Meyer	ARINC-825TBv2: A Hardware-in-the-Ioop Simulation Platform for Aerospace Security Research.	RSP	2019	DBLP DOI BibTeX RDF
44	Charles Hartsell, Nagabhushan Mahadevan, Shreyas Ramakrishna, Abhishek Dubey, Theodore Bapty, Taylor T. Johnson, Xenofon D. Koutsoukos, Janos Sztipanovits, Gabor Karsai	CPS Design with Learning-Enabled Components: A Case Study.	RSP	2019	DBLP DOI BibTeX RDF
44	Amira Guesmi, Ihsen Alouani, Mouna Baklouti, Tarek Frikha, Mohamed Abid, Atika Rivenq	HEAP: A Heterogeneous Approximate Floating-Point Multiplier for Error Tolerant Applications.	RSP	2019	DBLP DOI BibTeX RDF
44	Josue V. Quiroga, Martí Torrents, Nehir Sönmez, Dimitris Theodoropoulos, Ferad Zyulkyarov, Mario Nemirovsky	Evaluation of a Rack-Scale Disaggregated Memory Prototype for Cloud Data Centers.	RSP	2019	DBLP DOI BibTeX RDF
44	Tobias Strauch	Combining Simulation and FPGA Based Verification to an Affordable and Ultra-Fast Multi-Billion-Gate Verification System.	RSP	2019	DBLP DOI BibTeX RDF
44	Riyane Sid Lakhdar, Henri-Pierre Charles, Maha Kooli	Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization.	RSP	2019	DBLP DOI BibTeX RDF
44	Scott Young, Alexandrea Demmings, Nasrin Eshraghi Ivari, Jean-Philippe Legault, Kenneth B. Kent	Verilog Loop Unrolling, Module Generation, Part-Select and Arithmetic Right Shift Support in Odin II.	RSP	2019	DBLP DOI BibTeX RDF
44	Salah Eddine Saidi, Amir Charif, Tanguy Sassolas, Pierre-Guillaume Le Guay, Henrique Vicente Souza, Nicolas Ventroux	Fast Virtual Prototyping of Cyber-Physical Systems using SystemC and FMI: ADAS Use Case.	RSP	2019	DBLP DOI BibTeX RDF
44		2018 International Symposium on Rapid System Prototyping, RSP 2018, Torino, Italy, October 4-5, 2018	RSP	2018	DBLP BibTeX RDF
44	Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara	Synthesis of Full Hardware Implementation of RTOS-Based Systems.	RSP	2018	DBLP DOI BibTeX RDF
44	Dongyoung Kim, Soobeom Kim, Sungjoo Yoo	FPGA Prototyping of Low-Precision Zero-Skipping Accelerator for Neural Networks.	RSP	2018	DBLP DOI BibTeX RDF
44	Mehran Goli, Jannis Stoppe, Rolf Drechsler	Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques.	RSP	2018	DBLP DOI BibTeX RDF
44	Stefano Aldegheri, Nicola Bombieri	Rapid Prototyping of Embedded Vision Systems: Embedding Computer Vision Applications into Low-Power Heterogeneous Architectures.	RSP	2018	DBLP DOI BibTeX RDF
44	Maxime France-Pillois, Jérôme Martin, Frédéric Rousseau 0001	Accurate MPSoC Prototyping Platform and Methodology for the Studying of the Linux Synchronization Barrier Slowdown Issues.	RSP	2018	DBLP DOI BibTeX RDF
44	Thomas Baumela, Olivier Gruber, Olivier Muller, Frédéric Pétrot	Message-Oriented Devices on FPGAs.	RSP	2018	DBLP DOI BibTeX RDF
44	Muhammad Waqas 0003, Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam	Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper.	RSP	2018	DBLP DOI BibTeX RDF
44	Jean-Philippe Legault, Panagiotis Patros, Kenneth B. Kent	Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA.	RSP	2018	DBLP DOI BibTeX RDF
44	Rodrigo Schmitt Meurer, Antônio Augusto Fröhlich, Jomi Fred Hübner	Ambient Intelligence for the Internet of Things Through Context-Awareness.	RSP	2018	DBLP DOI BibTeX RDF
44	Fearghal Morgan, Declan O'Loughlin, Jeremy Audiger, Yohan Boyer, Niall Timlin-Canning, Krzysztof Kepa, Seamus Cawley, Ian Gallivan, László Bakó, Frank Callaly	Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC.	RSP	2018	DBLP DOI BibTeX RDF
44	Yawen Wu, Yinan Sun, Zhenge Jia, Lefan Zhang, Yongpan Liu, Jingtong Hu	Prototyping Energy Harvesting Powered Systems with Nonvolatile Processor (Invited Paper).	RSP	2018	DBLP DOI BibTeX RDF
44	Alexandre Chabot, Ihsen Alouani, Smaïl Niar, Réda Nouacer	A Comprehensive Fault Injection Strategy for Embedded Systems Reliability Assessment.	RSP	2018	DBLP DOI BibTeX RDF
44	Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Cinzia Bernardeschi	PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing.	RSP	2018	DBLP DOI BibTeX RDF
44	Kevin Verniers, Liesbet Van der Perre, Nobby Stevens	Assessment of a BeagleBone Black High Sampling Rate Digital Waveform Generator.	RSP	2018	DBLP DOI BibTeX RDF
44	Tristan Delizy, Stephane Gros, Kevin Marquet, Matthieu Moy, Tanguy Risset, Guillaume Salagnac	Estimating the Impact of Architectural and Software Design Choices on Dynamic Allocation of Heterogeneous Memories.	RSP	2018	DBLP DOI BibTeX RDF
44	William L. Harrison, Gerard Allwein	Semantics-Directed Prototyping of Hardware Runtime Monitors.	RSP	2018	DBLP DOI BibTeX RDF
44	Sungjoo Yoo, Fabiano Hessel, Frédéric Rousseau 0001, Kenneth B. Kent, Kyoungwoo Lee (eds.)	International Symposium on Rapid System Prototyping, RSP 2017, Shortening the Path from Specification to Prototype, October 19-20, 2017, Seoul, South Korea.	RSP	2017	DBLP DOI BibTeX RDF
44	Gyeongmin Lee, Seonyeong Heo, Bongjun Kim, Jong Kim 0001, Hanjun Kim 0001	Rapid prototyping of IoT applications with Esperanto compiler.	RSP	2017	DBLP DOI BibTeX RDF
44	Tiago Mück, Bryan Donyanavard, Nikil D. Dutt	PoIiCym: rapid prototyping of resource management policies for HMPs.	RSP	2017	DBLP DOI BibTeX RDF
44	Wooseok Yi, Junki Park, Jae-Joon Kim	GeCo: classification restricted Boltzmann machine hardware for on-chip learning.	RSP	2017	DBLP DOI BibTeX RDF
44	Sean Seeley, Vidya Sankaranaryanan, Zack Deveau, Panagiotis Patros, Kenneth B. Kent	Simulation-based circuit-activity estimation for FPGAs containing hard blocks.	RSP	2017	DBLP DOI BibTeX RDF
44	Michael Witterauf, Frank Hannig, Jürgen Teich	Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.	RSP	2017	DBLP DOI BibTeX RDF
44	Péter Völgyesi, Abhishek Dubey, Timothy Krentz, István Madari, Mary Metelko, Gabor Karsai	Time synchronization services for low-cost fog computing applications.	RSP	2017	DBLP DOI BibTeX RDF
44	Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama	Binary synthesis implementing external interrupt handler as independent module.	RSP	2017	DBLP DOI BibTeX RDF
44	Maha Kooli, Henri-Pierre Charles, Clément Touzet, Bastien Giraud, Jean-Philippe Noël	Software platform dedicated for in-memory computing circuit evaluation.	RSP	2017	DBLP DOI BibTeX RDF
44	Miho Shimizu, Nagisa Ishiura, Sayuri Ota, Wakako Nakano	Speculative execution in distributed controllers for high-level synthesis.	RSP	2017	DBLP DOI BibTeX RDF
44	Daniel Mueller-Gritschneder, Keerthikumara Devarajegowda, Martin Dittrich, Wolfgang Ecker, Marc Greim, Ulf Schlichtmann	The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.	RSP	2017	DBLP DOI BibTeX RDF
44	Imane Hafnaoui, Chao Chen, Rabeh Ayari, Gabriela Nicolescu, Giovanni Beltrame	An analysis of random cache effects on real-time multi-core scheduling algorithms.	RSP	2017	DBLP DOI BibTeX RDF
44	Jeonggyu Jang, Hoeseok Yang	Executable dataflow benchmark generation technique for multi-core embedded systems.	RSP	2017	DBLP DOI BibTeX RDF
44	Saideep Tiku, Sudeep Pasricha	Energy-efficient and robust middleware prototyping for smart mobile computing.	RSP	2017	DBLP DOI BibTeX RDF
44	Minato Yokota, Kaoru Saso, Yuko Hara-Azumi	One-instruction set computer-based multicore processors for energy-efficient streaming data processing.	RSP	2017	DBLP DOI BibTeX RDF
44	Arief Wicaksana, Alban Bourge, Olivier Muller, Arif Sasongko, Frédéric Rousseau 0001	Prototyping dynamic task migration on heterogeneous reconfigurable systems.	RSP	2017	DBLP DOI BibTeX RDF
44		2016 International Symposium on Rapid System Prototyping, RSP 2016, Pittsburg, PA, USA, October 6-7, 2016	RSP	2016	DBLP BibTeX RDF
44	Lothar Thiele, Felix Sutton, Romain Jacob, Roman Lim, Reto Da Forno, Jan Beutel	On platforms for CPS - adaptive, predictable and efficient.	RSP	2016	DBLP DOI BibTeX RDF
44	Corentin Damman, Gregory Edison, Fabrice Guet, Eric Noulard, Luca Santinelli, Jérôme Hugues	Architectural performance analysis of FPGA synthesized LEON processors.	RSP	2016	DBLP DOI BibTeX RDF
44	Ayoub Nouri, Rahma Ben Atitallah, Anca Molnos, Christian Fabre, Frédéric Heitzmann, Olivier Debicki	Transforming VHDL descriptions into formal component-based models.	RSP	2016	DBLP DOI BibTeX RDF
44	William L. Harrison, Adam M. Procter, Gerard Allwein	Model-driven design & synthesis of the SHA-256 cryptographic hash function in rewire.	RSP	2016	DBLP DOI BibTeX RDF
44	Panagiotis Patros, Kenneth B. Kent	Automatic detection and elision of reset sub-circuits.	RSP	2016	DBLP DOI BibTeX RDF
44	Akramul Azim	Overloads in compositional embedded real-time control systems.	RSP	2016	DBLP DOI BibTeX RDF
44	Xiang Chen 0010, Jiachen Mao, Kent W. Nixon, Yiran Chen 0001	MORPh: mobile OLED power friendly camera system.	RSP	2016	DBLP DOI BibTeX RDF
44	Paulo Cezar Dantas, Andrea Sarmento, Adriano Sarmento	A HW/SW embedded system for accelerating diagnosis of glaucoma from eye fundus images.	RSP	2016	DBLP DOI BibTeX RDF
44	Rabeh Ayari, Imane Hafnaoui, Giovanni Beltrame, Gabriela Nicolescu	Schedulability-guided exploration of multi-core systems.	RSP	2016	DBLP DOI BibTeX RDF
44	Takeshi Ohkawa, Kazushi Yamashina, Takuya Matsumoto, Kanemitsu Ootsu, Takashi Yokota	Architecture exploration of intelligent robot system using ros-compliant FPGA component.	RSP	2016	DBLP DOI BibTeX RDF
44	Kasra Moazzemi, Chen-Ying Hsieh, Nikil D. Dutt	HAMEX: heterogeneous architecture and memory exploration framework.	RSP	2016	DBLP DOI BibTeX RDF
44	Arief Wicaksana, Adrien Prost-Boucle, Olivier Muller, Frédéric Rousseau 0001, Arif Sasongko	On-board non-regression test of HLS tools targeting FPGA.	RSP	2016	DBLP DOI BibTeX RDF
44	Umer Farooq 0001, Roselyne Chotin-Avot, Muhammad Moazam Azeem, Maminionja Ravoson, Mariem Turki, Habib Mehrez	Inter-FPGA routing environment for performance exploration of multi-FPGA systems.	RSP	2016	DBLP DOI BibTeX RDF
44	Onur Mutlu	Keynote: rethinking memory system design.	RSP	2016	DBLP DOI BibTeX RDF