Search results for "RTR"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
126	Steve Guccione	Run-Time Reconfiguration at Xilinx.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
95	Jim Harkin, T. Martin McGinnity, Liam P. Maguire	Modeling and optimizing run-time reconfiguration using evolutionary computation.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	FPGAs, Evolutionary computing, partitioning, run-time reconfiguration
92	Stefan Ihmor, Wolfram Hardt	Runtime Reconfigurable Interfaces - The RTR-IFB Approach.	IPDPS	2004	DBLP DOI BibTeX RDF
79	Rawat Siripokarpirom	Platform Development for Run-Time Reconfigurable Co-Emulation.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
79	James D. Hadley, Brad L. Hutchings	Design methodologies for partially reconfigured systems.	FCCM	1995	DBLP DOI BibTeX RDF
76	Ray Bittner, Peter M. Athanas	Computing kernels implemented with a wormhole RTR CCM.	FCCM	1997	DBLP DOI BibTeX RDF
63	Cláudio F. Lima, Carlos M. Fernandes 0001, Fernando G. Lobo	Investigating restricted tournament replacement in ECGA for non-stationary environments.	GECCO	2008	DBLP DOI BibTeX RDF	restricted tournament replacement, genetic algorithms, estimation of distribution algorithms, niching, diversity preservation, non-stationary environments
63	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt, Juanjo Noguera	Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures.	DAC	2007	DBLP DOI BibTeX RDF
63	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures.	ASP-DAC	2006	DBLP DOI BibTeX RDF	granularity selection, linear placement, scheduling, data-parallelism, partial dynamic reconfiguration
63	Peter Bellows, Brad L. Hutchings	Designing Run-Time Reconfigurable Systems with JHDL.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FPGAs, image processing, CAD, configurable computing
63	Cynthia Cousineau, François Laperle, Yvon Savaria	Design of a JTAG Based Run Time Reconfigurable System.	FCCM	1999	DBLP DOI BibTeX RDF
63	James G. Eldredge, Brad L. Hutchings	Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
60	Valery Afanasiev, Dmitry Baigozin, Ilia Kazanski, Sergey Fomin, Stanislav V. Klimenko	RTR-trees for space robotics behavior simulation and visualization.	Vis. Comput.	2007	DBLP DOI BibTeX RDF	Robotics, Computer animation, Motion simulation
59	Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger	An 8x8 run-time reconfigurable FPGA embedded in a SoC.	DAC	2008	DBLP DOI BibTeX RDF	FPGA, RTR
47	Jochen Strunk, Toni Volkmer, Klaus Stephan, Wolfgang Rehm, Heiko Schick	Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA.	IPDPS	2009	DBLP DOI BibTeX RDF
47	Yuan Wang, Feng Xu 0007, Jian Lü 0001	Establishing recommendation trust relationships for internetwares.	ACM SIGSOFT Softw. Eng. Notes	2006	DBLP DOI BibTeX RDF	trust, recommendation, internetware
47	Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt	Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable Architectures.	FCCM	2005	DBLP DOI BibTeX RDF
47	Beverly Yang, Tyson Condie, Sepandar D. Kamvar, Hector Garcia-Molina	Non-Cooperation in Competitive P2P Networks.	ICDCS	2005	DBLP DOI BibTeX RDF
47	Brian Leonard, Jeff Young, Ron Sass	Online placement infrastructure to support run-time reconfiguration.	FPGA	2004	DBLP DOI BibTeX RDF
47	Kazuyuki Maruo, Masayoshi Ichikawa, Naoto Miyamoto, Leo Karnan, Takahiro J. Yamaguchi, Koji Kotani, Tadahiro Ohmi	A Dynamically-Reconfigurable Image Recognition Processor.	IPDPS	2004	DBLP DOI BibTeX RDF
47	Nitin Srivastava, Jerry L. Trahan, Ramachandran Vaidyanathan, Suresh Rai	Adaptive Image Filtering Using Run-Time Reconfiguration.	IPDPS	2003	DBLP DOI BibTeX RDF	adaptive image filtering, image processing, run-time reconfiguration
47	Tero Rissa, Milan Vasilko, Jarkko Niittylahti	System-Level Modelling and Implementation Technique for Run-Time Reconfigurable Systems.	FCCM	2002	DBLP DOI BibTeX RDF
47	Jean-Paul Heron, Roger F. Woods, Sakir Sezer, Richard H. Turner	Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	reconfiguration framework, dynamic reconfiguration, FIR filtering, FPGA implementation, high speed arithmetic
47	Oswaldo Cadenas, Graham M. Megson	A n-Bit Reconfigurable Scalar Quantiser.	FPL	2001	DBLP DOI BibTeX RDF
47	Scott McMillan, Steve Guccione	Partial Run-Time Reconfiguration Using JRTR.	FPL	2000	DBLP DOI BibTeX RDF
47	Brandon Blodget	Pre-route Assistant: A Routing Tool for Run-Time Reconfiguration.	FPL	2000	DBLP DOI BibTeX RDF
44	Weisheng Zhao, Eric Belhaire, Claude Chappert, Bernard Dieny, Guillaume Prenat	TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	Look-Up Table (LUT), MTJ, TAS, multi-context configuration, nonvolatile, Simulation, FPGA, architecture, low power, dynamical reconfiguration, flip-flop, MRAM
44	Valery Afanasiev, Dmitry Baigozin, Ilia Kazanski, Sergey Fomin, Stanislav V. Klimenko	RTR-Trees for Space Robotics Behavior Simulation and Visualization.	CW	2006	DBLP DOI BibTeX RDF
44	Min Xu, Mark D. Hill, Rastislav Bodík	A regulated transitive reduction (RTR) for longer memory race recording.	ASPLOS	2006	DBLP DOI BibTeX RDF	race recording, multithreading, determinism
43	Alireza Shoa, Shahram Shirani	Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	FPGA, DSP, Run-Time Reconfiguration (RTR)
43	Edson L. Horta, Sergio Takeo Kofuji	A Run-Time Reconfigurable ATM Switch.	IPDPS	2002	DBLP DOI BibTeX RDF	Partial RTR, ATM Switch, Reconfigurable Logic
32	Esam El-Araby, Iván González 0004, Tarek A. El-Ghazawi	Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	field programmable gate arrays (FPGA), High performance computing, reconfigurable computing, dynamic partial reconfiguration
32	Pil Woo Chun, Lev Kirischian	Architecture Synthesis Methodology for Run-Time Reconfigurable Systems.	CSE (2)	2009	DBLP DOI BibTeX RDF
32	Kolin Paul, Joël Porquet, Josep Llosa	Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.	DSD	2007	DBLP DOI BibTeX RDF
32	Esam El-Araby, Iván González, Tarek A. El-Ghazawi	Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing.	HPRCTA	2007	DBLP DOI BibTeX RDF	field programmable gate arrays (FPGA), high performance computing, reconfigurable computing, dynamic partial reconfiguration
32	Carlos Nahas, Ricardo Villalobos Guevara, Voicu Groza	Temporal Placement for Run-Time Reconfiguration.	CCECE	2006	DBLP DOI BibTeX RDF
32	Björn Griese, Erik Vonnahme, Mario Porrmann, Ulrich Rückert 0001	Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures.	FPL	2004	DBLP DOI BibTeX RDF
32	Peter Zipf, Manfred Glesner, Christine Bauer 0002, Hans Wojtkowiak	Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension.	FPL	2002	DBLP DOI BibTeX RDF
32	Edson L. Horta, John W. Lockwood, Sergio Takeo Kofuji	Using PARBIT to Implement Partial Run-Time Reconfigurable Systems.	FPL	2002	DBLP DOI BibTeX RDF
32	Michael J. Wirthlin, Brad L. Hutchings	Improving functional density using run-time circuit reconfiguration [FPGAs].	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
28	Wen-Ze Shao, Hai-Song Deng, Qi Ge, Li-Qian Wang	RTR-DPD: reweighted tikohonov regularization for blind deblurring via dual principles of discriminativeness.	Multidimens. Syst. Signal Process.	2023	DBLP DOI BibTeX RDF
28	P. Mohan Anand, P. V. Sai Charan, Hrushikesh Chunduri, Sandeep K. Shukla	RTR-Shield: Early Detection of Ransomware Using Registry and Trap Files.	ISPEC	2023	DBLP DOI BibTeX RDF
28	Haoyu Yi, Weidong Jiang, Xinyu Zhang 0010, Kai Huo	Quartic Optimization for Ambiguity Function Shaping via RTR Algorithm under ADPM Framework.	ICCT	2022	DBLP DOI BibTeX RDF
28	Fabrizio Ivan Apollonio, Riccardo Foschi, Marco Gaiani, Simone Garagnani	How to Analyze, Preserve, and Communicate Leonardo's Drawing? A Solution to Visualize in RTR Fine Art Graphics Established from "the Best Sense".	ACM Journal on Computing and Cultural Heritage	2021	DBLP DOI BibTeX RDF
28	Byron Navas, Ingo Sander, Johnny Öberg	Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs.	ReCoSoC	2015	DBLP DOI BibTeX RDF
28	Ying Zheng, David Shan-Hill Wong, Yanwei Wang, Huajing Fang	Takagi-Sugeno Model Based Analysis of EWMA RtR Control of Batch Processes With Stochastic Metrology Delay and Mixed Products.	IEEE Trans. Cybern.	2014	DBLP DOI BibTeX RDF
28	Byron Navas, Johnny Öberg, Ingo Sander	On providing scalable self-healing adaptive fault-tolerance to RTR SoCs.	ReConFig	2014	DBLP DOI BibTeX RDF
28	Kyoungha Kim, Ik-hyeon Jang, Yanggon Kim	Evaluating the performance impact of RTR-BIRD in origin validation.	RACS	2014	DBLP DOI BibTeX RDF
28	D. Ling, Y. Zheng, H. J. Fang, H. J. Fan, J. Zhao	ANOVA model based moving window approach for RtR control in high-mix semiconductor manufacturing industry.	ECC	2013	DBLP DOI BibTeX RDF
28	Matthias Wählisch, Fabian Holler, Thomas C. Schmidt, Jochen H. Schiller	Updates from the Internet Backbone: An RPKI/RTR Router Implementation, Measurements, and Analysis	NDSS	2013	DBLP BibTeX RDF
28	Huang Lu, Jie Li 0002, Zhongping Dong, Yusheng Ji	CRDMAC: An Effective Circular RTR Directional MAC Protocol for Wireless Ad Hoc Networks.	MSN	2011	DBLP DOI BibTeX RDF
28	Guo Yi, David Atienza, Antonio Rius, Serni Ribo, Carles Ferrer 0001	HTPCP: GNSS-R multi-channel cross-correlation waveforms post-processing solution for GOLD-RTR instrument.	AHS	2010	DBLP DOI BibTeX RDF
28	Stefan Ihmor, Wolfram Hardt	Runtime reconfigurable interfaces: the RTR-IFB approach.	Int. J. Embed. Syst.	2006	DBLP DOI BibTeX RDF
28	Farshid Farshadjam, Mehdi Dehghan 0001, Mahmood Fathy, Majid Ahmadi	A new compression based approach for reconfiguration overhead reduction in virtex based RTR systems.	Comput. Electr. Eng.	2006	DBLP DOI BibTeX RDF
28	V. O. Afanasiev	Trees and linked lists with variable ordering relations (RTR structures).	Program. Comput. Softw.	2006	DBLP DOI BibTeX RDF
28	Oliver Diessel, Shannon Koh	Enabling RTR for industry.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
28	Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon	Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
28	Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos	A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management.	FPL	2004	DBLP DOI BibTeX RDF
28	Camel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber	Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System Design.	IPDPS	2003	DBLP DOI BibTeX RDF
28	Meenakshi Kaul, Ranga Vemuri	Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures.	IPPS/SPDP Workshops	1999	DBLP DOI BibTeX RDF
28	Richard H. Turner, Roger F. Woods, Sakir Sezer, Jean-Paul Heron	A Virtual Hardware Handler for RTR Systems.	FCCM	1999	DBLP DOI BibTeX RDF
28	Joni da Silva Fraga, Jean-Marie Farines, Olinto Furtado	RTR model: an approach for dealing with real-time programming in open distributed systems.	WORDS	1997	DBLP DOI BibTeX RDF
28	Olinto J. V. Furtado	RTR - uma abordagem reflexiva para programação de aplicações tempo real.		1997	RDF
28	John J. Wallace, Walter W. Barnes	Designing for Ultrahigh Availability: The Unix RTR Operating System.	Computer	1984	DBLP DOI BibTeX RDF
27	Lev Kirischian, Victor Dumitriu, Pil Woo Chun	Virtualization of Computing Resources in RCS for Multi-task Stream Applications.	ReConFig	2009	DBLP DOI BibTeX RDF	Virtual component, component relocation, on-chip assembly, FPGA, Reconfigurable systems, Run-time reconfiguration (RTR), Virtual processor, Resources virtualization
27	Ian Robertson, James Irvine 0001	A design flow for partially reconfigurable hardware.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	dynamically reconfigurable logic (DRL), FPGA, power estimation, run-time reconfiguration (RTR), Viterbi decoder, configuration control
27	Philippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber	Hardware Partitioning Software for Dynamically Reconfigurable SoC Design.	IWSOC	2003	DBLP DOI BibTeX RDF	FPGA Dynamic Reconfiguration RTR SOC
27	Edson L. Horta, John W. Lockwood, David E. Taylor, David B. Parlour	Dynamic hardware plugins in an FPGA with partial run-time reconfiguration.	DAC	2002	DBLP DOI BibTeX RDF	FPG, partial RTR, platform computing, Internet, routing, network, modularity, reconfiguration, IP, hardware, packet
16	Mark Hauschild, Martin Pelikan	Network crossover performance on NK landscapes and deceptive problems.	GECCO	2010	DBLP DOI BibTeX RDF	estimation of distribution algorithms, bayesian optimization algorithm, crossover operators, efficiency enhancement, hierarchical boa, learning from experience
16	Christian S. Jensen, Hua Lu 0001, Bin Yang 0002	Indexing the Trajectories of Moving Objects in Symbolic Indoor Space.	SSTD	2009	DBLP DOI BibTeX RDF
16	Yoann Guillemenet, Lionel Torres, Gilles Sassatelli, Nicolas Bruchon, Ilham Hassoune	A non-volatile run-time FPGA using thermally assisted switching MRAMS.	FPL	2008	DBLP DOI BibTeX RDF
16	Michail Maniatakos, Songhua Xu, Willard L. Miranker	Constraint-Based Placement and Routing for FPGAs Using Self-Organizing Maps.	ICTAI (2)	2008	DBLP DOI BibTeX RDF
16	Ting Liu 0007, Camel Tanougast, Serge Weber	A framework of architectural synthesis for dynamically reconfigurable FPGAs.	SoCC	2008	DBLP DOI BibTeX RDF
16	Aric D. Blumer, Cameron D. Patterson	Hardware/Software Process Migration and RTL Simulation.	FPL	2007	DBLP DOI BibTeX RDF
16	Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley	Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.	FPL	2007	DBLP DOI BibTeX RDF
16	Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon	New non-volatile FPGA concept using Magnetic Tunneling Junction.	ISVLSI	2006	DBLP DOI BibTeX RDF
16	Nicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon	Magnetic tunnelling junction based FPGA.	FPGA	2006	DBLP DOI BibTeX RDF	magnetic tunneling junction, FPGA, non volatility
16	Sara Román Navarro, Hortensia Mecha, Daniel Mozos, Julio Septién	Partition Based Dynamic 2D HW Multitasking Management.	DSD	2006	DBLP DOI BibTeX RDF
16	Krzysztof Tchon, Janusz Jakubiak	A repeatable inverse kinematics algorithm with linear invariant subspaces for mobile manipulators.	IEEE Trans. Syst. Man Cybern. Part B	2005	DBLP DOI BibTeX RDF
16	Remy Eskinazi Sant'Anna, Manoel Eusébio de Lima, Paulo Romero Martins Maciel	A left-edge algorithm approach for scheduling and allocation of hardware contexts in dynamically reconfigurable architectures.	FPGA	2004	DBLP DOI BibTeX RDF
16	Marcos R. Boschetti, Sergio Bampi, Ivan Saraiva Silva	Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters.	FPL	2004	DBLP DOI BibTeX RDF
16	L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti 0001	A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAs.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
16	Richard H. Turner, Roger F. Woods	Design Flow for Efficient FPGA Reconfiguration.	FPL	2003	DBLP DOI BibTeX RDF
16	Markus Weinhardt, Wayne Luk	Pipeline vectorization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
16	Camel Tanougast, Yves Berviller, Serge Weber	Optimization of Motion Estimator for Run-Time-Reconfiguration Implementation.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
16	Lörinc Antoni, Régis Leveugle, Béla Fehér	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.	DFT	2000	DBLP DOI BibTeX RDF
16	Célio Estevan Morón	Designing Adaptable Real-Time Fault-Tolerant Parallel Systems.	IPPS	1996	DBLP DOI BibTeX RDF
16	Chunsik Yi, Steven Graham	Real-Time Reasoning with PROLOG.	SIGSMALL/PC Symposium	1990	DBLP DOI BibTeX RDF	Prolog