Search results for "SEU"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
113	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs.	ISQED	2007	DBLP DOI BibTeX RDF
108	Rajesh Garg, Charu Nagpal, Sunil P. Khatri	A fast, analytical estimator for the SEU-induced pulse width in combinational designs.	DAC	2008	DBLP DOI BibTeX RDF	single event upset (SEU), model, analysis
94	Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Majid Sarrafzadeh	Soft Error-Aware Power Optimization Using Gate Sizing.	PATMOS	2007	DBLP DOI BibTeX RDF
81	Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh	General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
73	Rajesh Garg, Sunil P. Khatri	Efficient analytical determination of the SEU-induced pulse shape.	ASP-DAC	2009	DBLP DOI BibTeX RDF
73	Mahdi Fazeli, Ahmad Patooghy, Seyed Ghassem Miremadi, Alireza Ejlali	Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies.	DSN	2007	DBLP DOI BibTeX RDF
73	Ying Huang, Chunyuan Zhang, Dong Liu 0022, Yi Li, Sheng-xin Weng	The Design on SEU-Tolerant Information Processing System of the On-Board-Computer.	APPT	2007	DBLP DOI BibTeX RDF	Dual Fault-Tolerant, Triple Module Redundancy, Cost-Off-The-Shelf, Field Programmable Gate Array, Single-Event-Upsets
73	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
73	Liang Wang 0024, Suge Yue, Yuanfu Zhao, Long Fan	An SEU-Tolerant Programmable Frequency Divider.	ISQED	2007	DBLP DOI BibTeX RDF
73	Wonjin Jang, Alain J. Martin	SEU-Tolerant QDI Circuits.	ASYNC	2005	DBLP DOI BibTeX RDF
73	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
68	Ahmad Patooghy, Mahdi Fazeli, Seyed Ghassem Miremadi	A Low-Power and SEU-Tolerant Switch Architecture for Network on Chips.	PRDC	2007	DBLP DOI BibTeX RDF	SEU-Tolerance, Power Consumption, NoC
67	Thara Rejimon, Sanjukta Bhanja	A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
59	Rajesh Garg, Sunil P. Khatri	A novel, highly SEU tolerant digital circuit design approach.	ICCD	2008	DBLP DOI BibTeX RDF
59	Makoto Sugihara	SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems.	ISQED	2008	DBLP DOI BibTeX RDF	Heterogeneous Multiprocessor Systems, Reliability, Task Scheduling, Soft Error, Single Event Upset
55	Cristiana Bolchini, Davide Quarta, Marco D. Santambrogio	SEU mitigation for sram-based fpgas through dynamic partial reconfiguration.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault detection, SEU, partial dynamic reconfiguration
54	Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sarrafzadeh	Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems.	ISQED	2008	DBLP DOI BibTeX RDF
49	Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	SEE tolerance, SEU tolerance, SET tolerance, Asynchronous circuit
46	Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi	SEU hardened clock regeneration circuits.	ISQED	2009	DBLP DOI BibTeX RDF
46	Roystein Oliveira, Aditya Jagirdar, Tapan J. Chakraborty	A TMR Scheme for SEU Mitigation in Scan Flip-Flops.	ISQED	2007	DBLP DOI BibTeX RDF
46	Luca Schiano, Marco Ottavi, Fabrizio Lombardi	Markov Models of Fault-Tolerant Memory Systems under SEU.	MTDT	2004	DBLP DOI BibTeX RDF
46	Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto	Automated Synthesis of SEU Tolerant Architectures from OO Descriptions.	IOLTW	2002	DBLP DOI BibTeX RDF
42	Emmanuel Touloupis, James A. Flint, Vassilios A. Chouliaras, David D. Ward	Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	fault modeling and simulation, fault tolerance, fault injection, soft error, SEU, microprocessor test
41	Laura Frigerio, Matteo Alan Radaelli, Fabio Salice	Convolutional Coding for SEU mitigation.	ETS	2008	DBLP DOI BibTeX RDF	SEU mitigation, convolutional coding
41	Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger	Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.	ISLPED	2005	DBLP DOI BibTeX RDF	single event upset (SEU), dynamic voltage scaling (DVS), information redundancy
41	Harry Hollander, Bradley S. Carlson, Toby D. Bennett	Synthesis of SEU-tolerant ASICs using concurrent error correction.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	radiation hardening (electronics), SEU-tolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction
40	Denis Bouyssou, Marc Pirlot	On some ordinal models for decision making under uncertainty.	Ann. Oper. Res.	2008	DBLP DOI BibTeX RDF	Subjective expected utility, Conjoint measurement, Nontransitive preferences, Likely dominance model, Decision under uncertainty
40	Eze Kamanu, Pratapa Reddy, Kenneth Hsu, Marcin Lukowiak	A New Architecture for Single-Event Detection & Reconfiguration of SRAM-based FPGAs.	HASE	2007	DBLP DOI BibTeX RDF
40	Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell	Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.	ISVLSI	2007	DBLP DOI BibTeX RDF
40	Haruhiko Kaneko, Eiji Fujiwara	Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks.	DFT	2007	DBLP DOI BibTeX RDF
40	Thara Rejimon, Sanjukta Bhanja	Wide Limited Switch Dynamic Logic Circuit Implementations.	VLSI Design	2006	DBLP DOI BibTeX RDF
40	Gilson I. Wirth, Michele G. Vieira, Egas Henes Neto, Fernanda Gusmão de Lima Kastensmidt	Single event transients in combinatorial circuits.	SBCCI	2005	DBLP DOI BibTeX RDF	soft errors, integrated circuits, single event transients
40	Maya B. Gokhale, Paul S. Graham, Darrel Eric Johnson, Nathan Rollins, Michael J. Wirthlin	Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
40	Lörinc Antoni, Régis Leveugle, Béla Fehér	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.	DFT	2002	DBLP DOI BibTeX RDF
38	Peng Li, Wei Guo, Zhenyu Zhao, Minxuan Zhang, Quan Deng	SEU hardened layout design for SRAM cells based on SEU reversal.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
38	Cinzia Bernardeschi, Luca Cassano, Andrea Domenici	SEU-X: A SEu un-excitability prover for SRAM-FPGAs.	IOLTS	2012	DBLP DOI BibTeX RDF
38	Riadul Islam	A highly reliable SEU hardened latch and high performance SEU hardened flip-flop.	ISQED	2012	DBLP DOI BibTeX RDF
36	Franz X. Ruckerbauer, Georg Georgakos	Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena.	IOLTS	2007	DBLP DOI BibTeX RDF	NSER, ASER, multi-bit upset, soft errors and radiation, CMOS, SRAM, SEU
35	Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro	Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	error tolerant system, single event upset (SEU), Digital SignalProcessing (DSP), fault-tolerance, sigma-delta
34	Maria Carmela Raguso, Marco Mastrogiuseppe, Roberto Seu	Clutter Detection and Surface/Subsurface Slope Determination by Combination of Repeat-Pass Sounder Orbits Applied to SHARAD Data.	IEEE Geosci. Remote. Sens. Lett.	2022	DBLP DOI BibTeX RDF
34	Letizia Gambacorta, Maria Carmela Raguso, Marco Mastrogiuseppe, Roberto Seu	UWB Processing Applied to Multifrequency Radar Sounders: The Case of MARSIS and Comparison With SHARAD.	IEEE Trans. Geosci. Remote. Sens.	2022	DBLP DOI BibTeX RDF
34	Cai Wang, Soo Yeon Kim, Yein Song, Sungho Kim, Minsik Choi, Donghoon Seu, Myung Hwan Yun	Text Mining for Exploring UX Issues of Qualitative Think Aloud Data on EV Sound.	IEEM	2022	DBLP DOI BibTeX RDF
34	Valerio Poggiali, Marco Mastrogiuseppe, Alexander Gerard Hayes, Roberto Seu, Joseph Peter Mullen, Samuel Patrick Dennis Birch, Maria Carmela Raguso	High-Resolution Topography of Titan Adapting the Delay/Doppler Algorithm to the Cassini RADAR Altimeter Data.	IEEE Trans. Geosci. Remote. Sens.	2019	DBLP DOI BibTeX RDF
34	Sara Zaher, Davide Lonardoni, Fabio Boi, Giovanni Pietro Seu, Gian Nicola Angotzi, Paolo Meloni, Luca Berdondini	A Closed-Loop System Processing High-Density Electrical Recordings and Visual Stimuli to Study Retinal Circuits Properties.	NER	2019	DBLP DOI BibTeX RDF
34	Giovanni Pietro Seu	Exploiting All-Programmable System on Chips for Closed-Loop Real-Time Neural Interfaces.		2019	RDF
34	Giovanni Pietro Seu, Gian Nicola Angotzi, Fabio Boi, Luigi Raffo, Luca Berdondini, Paolo Meloni	Exploiting All Programmable SoCs in Neural Signal Analysis: A Closed-Loop Control for Large-Scale CMOS Multielectrode Arrays.	IEEE Trans. Biomed. Circuits Syst.	2018	DBLP DOI BibTeX RDF
34	Elvira Musico, Claudio Cesaroni, Luca Spogli, John Peter Merryman Boncori, Giorgiana De Franceschi, Roberto Seu	The Total Electron Content From InSAR and GNSS: A Midlatitude Study.	IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens.	2018	DBLP DOI BibTeX RDF
34	Maria Carmela Raguso, Lorenzo Piazzo, Marco Mastrogiuseppe, Roberto Seu, Roberto Orosei	Resolution Enhancement and Interference Suppression for Planetary Radar Sounders.	EUSIPCO	2018	DBLP DOI BibTeX RDF
34	Kyung-Seu Cho, Jae-Moo Lee	Influence of smartphone addiction proneness of young children on problematic behaviors and emotional intelligence: Mediating self-assessment effects of parents using smartphones.	Comput. Hum. Behav.	2017	DBLP DOI BibTeX RDF
34	Simona Ibba, Andrea Pinna 0002, Matteo Seu, Filippo Eros Pani	CitySense: blockchain-oriented smart cities.	XP Workshops	2017	DBLP DOI BibTeX RDF
34	Giovanni Pietro Seu, Gian Nicola Angotzi, Giuseppe Tuveri, Luigi Raffo, Luca Berdondini, Alessandro Maccione, Paolo Meloni	On-FPGA Real-Time Processing of Biological Signals From High-Density MEAs: a Design Space Exploration.	IPDPS Workshops	2017	DBLP DOI BibTeX RDF
34	Marco Restano, Roberto Seu, Giovanni Picardi	A Phase-Gradient-Autofocus Algorithm for the Recovery of MARSIS Subsurface Data.	IEEE Geosci. Remote. Sens. Lett.	2016	DBLP DOI BibTeX RDF
34	Marco Mastrogiuseppe, Alexander Hayes 0002, Valerio Poggiali, Roberto Seu, Jonathan I. Lunine, J. D. Hofgartner	Radar Sounding Using the Cassini Altimeter: Waveform Modeling and Monte Carlo Approach for Data Inversion of Observations of Titan's Seas.	IEEE Trans. Geosci. Remote. Sens.	2016	DBLP DOI BibTeX RDF
34	Giuseppe Tuveri, Paolo Meloni, Francesca Palumbo, Giovanni Pietro Seu, Igor Loi, Francesco Conti 0001, Luigi Raffo	On-the-fly adaptivity for process networks over shared-memory platforms.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
34	Lorenzo Piazzo, Maria Carmela Raguso, Luca Calzoletti, Roberto Seu, Bruno Altieri	Least Squares Time-Series Synchronization in Image Acquisition Systems.	IEEE Trans. Image Process.	2016	DBLP DOI BibTeX RDF
34	Lorenzo Bruzzone, Jeffrey J. Plaut, Giovanni Alberti, Donald D. Blankenship, Francesca Bovolo, Bruce A. Campbell, Adamo Ferro, Yonggyu Gim, Wlodek Kofman, Goro Komatsu, William McKinnon, Giuseppe Mitri, Roberto Orosei, G. Wesley Patterson, Dirk Plettemeier, Roberto Seu	RIME: Radar for Icy Moon Exploration.	IGARSS	2013	DBLP DOI BibTeX RDF
34	Valerio Poggiali, Marco Mastrogiuseppe, Mattia Callegari, Riccardo Martufi, Roberto Seu, Domenico Casarano, Luca Pasolli, Claudia Notarnicola	Synergy of Cassini SAR and altimeter acquisitions for the retrieval of dune field characteristics on Titan.	SAR	2012	DBLP DOI BibTeX RDF
34	Marco Restano, Marco Mastrogiuseppe, Arturo Masdea, Giovanni Picardi, Roberto Seu	Shallow Radar (SHARAD) investigations over Sinus Meridiani.	IGARSS	2012	DBLP DOI BibTeX RDF
34	Renato Croci, Roberto Seu, Enrico Flamini, Enrico Russo	The SHAllow RADar (SHARAD) Onboard the NASA MRO Mission.	Proc. IEEE	2011	DBLP DOI BibTeX RDF
34	Seu Keow Cheng, Booi Hon Kam	A conceptual framework for analysing risk in supply networks.	J. Enterp. Inf. Manag.	2008	DBLP DOI BibTeX RDF
34	Marco Iorio, Franco Fois, Riccardo Mecozzi, Roberto Seu, Giovanni Picardi	GPR missions on mars.	IGARSS	2007	DBLP DOI BibTeX RDF
34	Renato Croci, Franco Fois, Mauro Guelfi, Paolo Noschese, Riccardo Mecozzi, Roberto Seu	Calibration of the SHARAD Instrument.	IGARSS	2007	DBLP DOI BibTeX RDF
34	Franco Fois, Riccardo Mecozzi, Marco Iorio, Diego Calabrese, Ornella Bombaci, Clau Catallo, Anna Croce, Renato Croci, Mauro Guelfi, Enrico M. Zampolini, Domenico Ravasi, Massimo Molteni, Paolo Ruggeri, Antonella Ranieri, M. Ottavianelli, Enrico Flamini, Giovanni Picardi, Roberto Seu, Daniela Biccari, Roberto Orosei, Marci Cartacci, Andrea Cicchetti, Arturo Masdea, Emmanuele Giacomoni, Marco Cutigni, Marco Provenziani, Oreste Fuga, Giovanni Alberti, Stefania Mattei, Claudio Papa, Paolo Marras, Barbara Tattarletti, Danilo Vicari, Francesco Bonaventura, Tobia Paterno, Antonio Di Placido, Antonio Morlupi	Comparison between MARSIS & SHARAD results.	IGARSS	2007	DBLP DOI BibTeX RDF
34	Franco Fois, Renato Croci, Roberto Seu, Giovanni Picardi, Enrico Flamini	Performance results of the SHARAD instrument.	IGARSS	2007	DBLP DOI BibTeX RDF
34	Renato Croci, Franco Fois, Diego Calabrese, Enrico M. Zampolini, Roberto Seu, Giovanni Picardi, Enrico Flamini	SHARAD design and operation.	IGARSS	2007	DBLP DOI BibTeX RDF
34	Jai Hyun Seu, Byung-Keun Song, Heung Shik Kim	Simulation of Artificial Life Model in Game Space.	AIS	2004	DBLP DOI BibTeX RDF
34	Daniela Biccari, Diego Calabrese, Donald A. Gurnett, Richard L. Huff, L. Marinangeli, Rolando L. Jordan, Erling Nielsen, G. G. Ori, Giovanni Picardi, Jeffrey J. Plaut, F. Provvedi, Roberto Seu, Enrico M. Zampolini	VENUS Subsurface Ionosphere Radar Sounder: VENSIS.	3DPVT	2004	DBLP DOI BibTeX RDF
34	Daniela Biccari, Giovanni Picardi, Roberto Seu	Mars high resolution Shallow Radar (SHARAD) for the MRO 2005 mission.	IGARSS	2002	DBLP DOI BibTeX RDF
34	Daniela Biccari, Donald A. Gurnett, William T. K. Johnson, Richard L. Huff, L. Marinangeli, Rolando L. Jordan, Erling Nielsen, G. G. Ori, Giovanni Picardi, Jeffrey J. Plaut, F. Provvedi, Roberto Seu, Enrico M. Zampolini	Venus radar for subsurface and ionosphere sounding (VENSIS).	IGARSS	2002	DBLP DOI BibTeX RDF
34	Roger Lundqvist, Leighton R. Barnden, Seu Som, Ewert Bengtsson, Lennart Thurfjell	An Evaluative Study of Simulated Annealing Based MRI-SPECT Brain Scan Registration.	VIIP	2001	DBLP BibTeX RDF
34	Tan Hock-Guan, Lua Seu-Kea	Web-based Object Oriented Multimedia Assessment System.	WebNet	1999	DBLP BibTeX RDF
34	Tan Hock-Guan, Lua Seu-Kea	Innovative use of IT to support Competency Based Learning Paradigm - The Ngee Ann's Perspectives.	WebNet	1999	DBLP BibTeX RDF
32	Cristiana Bolchini, Antonio Miele, Fabio Rebaudengo, Fabio Salice, Donatella Sciuto, Luca Sterpone, Massimo Violante	Software and Hardware Techniques for SEU Detection in IP Processors.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Hardware/software techniques, Single-event upset faults, Reliability, Fault injection
32	Alireza Ejlali, Bashir M. Al-Hashimi	SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.	NOCS	2008	DBLP DOI BibTeX RDF
32	Laura Frigerio, Matteo Alan Radaelli, Fabio Salice	A Generalized Approach for the Use of Convolutional Coding in SEU Mitigation.	DFT	2008	DBLP DOI BibTeX RDF
32	Arthur Pereira Frantz, Maico Cassel, Fernanda Lima Kastensmidt, Érika F. Cota, Luigi Carro	Crosstalk- and SEU-Aware Networks on Chips.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	fault tolerance. energy-aware systems, network on chip, crosstalk, single-event upset, hardware-software codesign
32	Luca Sterpone, Massimo Violante	Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.	ETS	2007	DBLP DOI BibTeX RDF
32	Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena	A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors.	IOLTS	2007	DBLP DOI BibTeX RDF
32	Shahin Golshan, Elaheh Bozorgzadeh	Single-Event-Upset (SEU) Awareness in FPGA Routing.	DAC	2007	DBLP DOI BibTeX RDF
32	Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi	Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
32	Arthur Pereira Frantz, Luigi Carro, Érika F. Cota, Fernanda Lima Kastensmidt	Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers.	IOLTS	2006	DBLP DOI BibTeX RDF
32	Sajid Baloch, Tughrul Arslan, Adrian Stoica	Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices.	ISQED	2006	DBLP DOI BibTeX RDF
32	Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil	Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
32	David de Andrés, José Albaladejo, Lenin Lemus, Pedro J. Gil	Fast Run-Time Reconfiguration for SEU Injection.	EDCC	2005	DBLP DOI BibTeX RDF
32	Nicolas Renaud	How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family.	IOLTS	2005	DBLP DOI BibTeX RDF
32	Raoul Velazco, R. Ecoffet, F. Faure	How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight.	IOLTS	2005	DBLP DOI BibTeX RDF
32	Guillaume Hubert, Nadine Buard, Cécile Weulersse, Thierry Carrière, Marie-Catherine Palau, Jean-Marie Palau, Damien Lambert, Jacques Baggio, Frederic Wrobel, Frédéric Saigné, Rémi Gaillard	A Review of DASIE Code Family: Contribution to SEU/MBU Understanding.	IOLTS	2005	DBLP DOI BibTeX RDF
32	Kartik Mohanram	Closed-Form Simulation and Robustness Models for SEU-Tolerant Design.	VTS	2005	DBLP DOI BibTeX RDF
32	Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori	Analyzing SEU Effects in SRAM-based FPGAs.	IOLTS	2003	DBLP DOI BibTeX RDF
32	Fernanda Gusmão de Lima Kastensmidt, Luigi Carro, Raoul Velazco, Ricardo Augusto da Luz Reis	Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller.	IOLTW	2002	DBLP DOI BibTeX RDF
32	Alfredo Benso, Stefano Martinetto, Paolo Prinetto, Riccardo Mariani	An SEU Injection Tool to Evaluate DSP-Based Architectures for Space Applications.	ICCD	2000	DBLP DOI BibTeX RDF
27	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
27	Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello	An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.	ARC	2009	DBLP DOI BibTeX RDF	FPGA, Space, Reconfigurable System, Single Event Upsets, Avionics
27	Rui Gong, Kui Dai, Zhiying Wang 0003	A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.	DFT	2008	DBLP DOI BibTeX RDF
27	Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan	Single Event Upset Detection and Correction.	ICIT	2007	DBLP DOI BibTeX RDF
27	Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew	Soft Error Mitigation in Switch Modules of SRAM-based FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi	Error Tolerance of DNA Self-Healing Assemblies by Puncturing.	DFT	2007	DBLP DOI BibTeX RDF
27	Yanxia Wu, Guochang Gu, Shaobin Huang, Jun Ni	Control Flow Checking Algorithm using Soft-based Intra-/Inter-block Assigned-Signature.	IMSCCS	2007	DBLP DOI BibTeX RDF
27	Gilson I. Wirth, Ivandro Ribeiro, Michele G. Vieira, Fernanda Gusmão de Lima Kastensmidt	Single event transients in dynamic logic.	SBCCI	2006	DBLP DOI BibTeX RDF	integrated circuits, dynamic logic, single event transients
27	Chong Zhao, Sujit Dey	Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO).	ISQED	2006	DBLP DOI BibTeX RDF