Search results for "Synthesis"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Mark Genoe, Paul Vanoostende, Geert van Wauwe	On the use of VHDL-based behavioral synthesis for telecom ASIC design.	ISSS	1995	DBLP DOI BibTeX RDF	Alcatel-Bell, RTL-synthesizable description, behavioral synthesis tools, hardware CAD tool, system level design methodology, telecom ASIC design, telecom system hardware design, high level synthesis, VHDL, VHDL, application specific integrated circuits, ASIC, logic synthesis, integrated circuit design, hardware description languages, integrated logic circuits, behavioral synthesis, telecommunication computing, hardware software codesign, design complexities
54	Greg Stitt, Frank Vahid	Binary synthesis.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Binary synthesis, synthesis from software binaries, FPGA, hardware/software codesign, hardware/software partitioning, configurable logic, warp processors
51	Sylvain Lefebvre 0001, Hugues Hoppe	Appearance-space texture synthesis.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	RTT synthesis, anisometric synthesis, exemplar-based synthesis, feature-based synthesis, dimensionality reduction, surface textures
51	John Williams, Mark J. Clement	Distributed Polyphonic Music Synthesis.	HPDC	1997	DBLP DOI BibTeX RDF	polyphonic music synthesis, music synthesis, distributed music synthesis, Csound music synthesis package, multiple servers, networks, music, communication protocols, distributed multimedia
48	Jan Madsen, Bjarne Hald	An approach to interface synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	channel optimization, client-side interface description, client/server module synthesis, communication events formalization, existing module reuse, multiple client/server environment, one-sided interface description, server interface description, software reusability, application program interfaces, client-server systems, subroutines, interface synthesis, point-to-point communication
48	Ilya Issenin, Nikil D. Dutt	Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	customized memory hierarchy, hierarchical TDMA buses, data reuse, multiprocessor system-on-chip, communication synthesis
47	Jian Liu, Jicheng Fu, Yansheng Zhang, Farokh B. Bastani, I-Ling Yen, Ann T. Tai, Savio N. Chau	Deductive Glue Code Synthesis for Embedded Software Systems Based on Code Patterns.	ISORC	2006	DBLP DOI BibTeX RDF	Automated code synthesis, Deductive code synthesis, Real-time system, Code patterns
45	Alessandro Balboni, William Fornaciari, Massimo Vincenzi, Donatella Sciuto	The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.	ISSS	1996	DBLP DOI BibTeX RDF	virtual instruction set, control-dominated hardware-software system, retargetable code synthesis, real-time systems, embedded systems, software development, performance estimation, embedded computing, software synthesis, real-time constraints, system synthesis, static scheduling
45	Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen	A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.	VLSI Design	1996	DBLP DOI BibTeX RDF	Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM
44	Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki	A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	high-level synthesis for testability, systematic flexible synthesis, testability methodology, industrial tools, pragmatic synthesis, AMICAL synthesis, programmable test pattern generation, BUS-based circuit, embedded test paths, high level synthesis, design for testability, BIST, automatic generation, data path, scan path
44	Chih-Tung Chen, Kayhan Küçükçakar	High-level scheduling model and control synthesis for a broad range of design applications.	ICCAD	1997	DBLP DOI BibTeX RDF	multi-phase clocking, relative scheduling, architectural power optimization, high-level synthesis, pipelining, multi-threading, behavioral synthesis, control synthesis, architectural synthesis, scheduling model
44	H. Fatih Ugurdag, Thomas E. Fuhrman	Autocircuit: a clock edge general behavioral synthesis system with a direct path to physical datapath.	ICCD	1996	DBLP DOI BibTeX RDF	Autocircuit, clock edge general behavioral synthesis system, physical datapaths, next-generation synthesis tool, behavioral HDL input descriptions, data-flow representations, use-trees, raw-states, word-oriented synthesis, unique parameterized netlist representation, high level synthesis, high-level design
44	Ti-Yen Yen, Wayne H. Wolf	Communication synthesis for distributed embedded systems.	ICCAD	1995	DBLP DOI BibTeX RDF	analysis algorithm, real-time systems, embedded systems, CAD, distributed processing, distributed embedded systems, interprocess communication, delay bounds, system buses, communication links, co-synthesis, synthesis algorithm, hardware-software co-synthesis
42	Jean-Marc Daveau, Tarek Ben Ismail, Ahmed Amine Jerraya	Synthesis of system-level communication by an allocation-based approach.	ISSS	1995	DBLP DOI BibTeX RDF	allocation-based approach, high level primitives, interconnected processes, protocol selection, system-level communication synthesis, protocols, high level synthesis, systems analysis, cost function, interface synthesis, communication control
42	Eike Grimpe, Frank Oppenheimer	Extending the SystemC synthesis subset by object-oriented features.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	C/C++ based design, object-orientation, high-level synthesis, SystemC, system level design, hardware description language, hardware synthesis
41	Ali Dasdan	Efficient algorithms for debugging timing constraint violations.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	over-constraint resolution, scheduling, high-level synthesis, constraint satisfaction, timing constraints, behavioral synthesis, rate analysis
41	Miodrag Potkonjak, Wayne H. Wolf	Cost optimization in ASIC implementation of periodic hard-real time systems using behavioral synthesis techniques.	ICCAD	1995	DBLP DOI BibTeX RDF	allocation algorithms, behavioral synthesis techniques, datapath synthesis criteria, multiple computational tasks, multiple-task examples, periodic hard-real time systems, real-time systems, high level synthesis, logic design, application specific integrated circuits, circuit CAD, circuit optimisation, cost optimization, rate-monotonic scheduling, task sharing, synthesis algorithm, ASIC implementation
40	Mihhail Matskin, Enn Tyugu	Strategies of Structural Synthesis of Programs.	ASE	1997	DBLP DOI BibTeX RDF	structural program synthesis strategies, deductive program synthesis method, compositional programming, decidable logical calculus, PSPACE complexity, independent subtasks, iteration synthesis, regular data structures, heuristics, programming environments, structured programming, proof search, search efficiency
40	Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja	Incorporating testability considerations in high-level synthesis.	J. Electron. Test.	1994	DBLP DOI BibTeX RDF	Automatic synthesis of testable designs, loop breaking, high-level synthesis, binding, synthesis for testability
40	Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken	Manufacturability and Testability Oriented Synthesis.	VLSI Design	2000	DBLP DOI BibTeX RDF	Synthesis Optimization, CAD, System on Chip, Design for Manufacturability, High Level Test Synthesis
40	Bharat P. Dave, Niraj K. Jha	COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures.	VLSI Design	1998	DBLP DOI BibTeX RDF	scheduling, distributed systems, embedded systems, hierarchy, allocation, system synthesis, hardware-software co-synthesis
40	Saurabh Srivastava 0001, Sumit Gulwani, Jeffrey S. Foster	From program verification to program synthesis.	POPL	2010	DBLP DOI BibTeX RDF	proof-theoretic program synthesis, verification
40	J. C. Hwang, C. W. Huang, C. T. Cheng	The Development of Load Characteristics Information Network System to Improve the Estimated Efficiency of Load Synthesis in Taipower.	ICICIC (1)	2006	DBLP DOI BibTeX RDF	load survey, load synthesis, network database, customer management
40	Vijay Raghunathan, Srivaths Ravi 0001, Ganesh Lakshminarayana	High-Level Synthesis with Variable-Latency Components.	VLSI Design	2000	DBLP DOI BibTeX RDF	variable latency units, data dependent computation, area-delay tradeoffs, High-level synthesis, performance optimization
40	Oliver Bringmann 0001, Wolfgang Rosenstiel, Annette Muth, Georg Färber, Frank Slomka, Richard Hofmann	Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Synthesis Methodology, Configurable VHDL Components, VHDL, Rapid Prototyping, SDL
39	James D. Edge, Adrian Hilton 0001, Philip J. B. Jackson	Model-based synthesis of visual speech movements from 3D video.	SIGGRAPH Posters	2009	DBLP DOI BibTeX RDF
38	Raul Camposano	Behavior-Preserving Transformations for High-Level Synthesis.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
38	Hirozumi Yamaguchi, Khaled El-Fakih, Gregor von Bochmann, Teruo Higashino	Protocol synthesis and re-synthesis with optimal allocation of resources based on extended Petri nets.	Distributed Comput.	2003	DBLP DOI BibTeX RDF	Protocol re-synthesis, Distributed system, Petri net, Service specification, Protocol specification, Protocol synthesis
37	Farhana Sheikh, Andreas Kuehlmann, Kurt Keutzer	Minimum-power retiming for dual-supply CMOS circuits.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF	dual-supply, retiming theory, low-power, synthesis, low-power design
37	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha	Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	design for hierarchical testability, gate-level sequential test generation, controller data path circuits, large data path bit-widths, minimal test hardware, system-level test set, logic testing, high level synthesis, high level synthesis, integrated circuit testing, design for testability, design for testability, automatic testing, logic CAD, integrated circuit design, behavioral synthesis, logic gates, register-transfer level design, RTL circuits
37	Hideyuki Mizuno, Satoshi Takahashi	Unit selection using k-nearest neighbor search for concatenative speech synthesis.	IUCS	2009	DBLP DOI BibTeX RDF	concatenative speech synthesis, synthesis unit selection, nearest neighbor search, text to speech
37	Sylvain Lefebvre 0001, Hugues Hoppe	Parallel controllable texture synthesis.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	Gaussian stack, coordinate jitter, data amplification, neighborhood matching, runtime content synthesis, synthesis magnification
37	Byoungro So, Pedro C. Diniz, Mary W. Hall	Using estimates from behavioral synthesis tools in compiler-directed design space exploration.	DAC	2003	DBLP DOI BibTeX RDF	synthesis techniques for reconfigurable computing, field-programmable-gate-array, high-level synthesis, rapid prototyping, design space exploration
37	Bharat P. Dave, Niraj K. Jha	CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures.	DATE	1998	DBLP DOI BibTeX RDF	aperiodic task graphs, scheduling, distributed systems, embedded systems, allocation, system synthesis, hardware-software co-synthesis
37	S. C. Chan, Andrew K. C. Wong	Synthesis and Recognition of Sequences.	IEEE Trans. Pattern Anal. Mach. Intell.	1991	DBLP DOI BibTeX RDF	sequences synthesis, sequences recognition, hierarchical sequence synthesis procedure, taxonomic hierarchy, unsupervised classification procedure, pattern recognition, probability, alignment, supervised classification, alphabet
36	Viktor Kuncak, Mikaël Mayer, Ruzica Piskac, Philippe Suter	Complete functional synthesis.	PLDI	2010	DBLP DOI BibTeX RDF	bapa, synthesis procedure, decision procedure, presburger arithmetic
36	Jason Cong, Kirill Minkovich	Optimality Study of Logic Synthesis for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
36	Bernd Finkbeiner, Sven Schewe	Semi-automatic Distributed Synthesis.	ATVA	2005	DBLP DOI BibTeX RDF
36	Reinaldo A. Bergamaschi	Bridging the domains of high-level and logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
36	Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid	On the efficiency of formal synthesis-experimental results.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
36	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
35	Miodrag Potkonjak, Anantha P. Chandrakasan	Synthesis and selection of DCT algorithms using behavioral synthesis-based algorithm space exploration.	ICIP	1995	DBLP DOI BibTeX RDF	DCT algorithms, behavioral synthesis-based algorithm space exploration, high level synthesis tools, behavioral design space, IC implementation, image processing, image processing, high level synthesis, discrete cosine transforms, discrete cosine transform, application specific integrated circuits, circuit layout CAD, video processing, fast algorithms, video signal processing, digital signal processing chips, design space
35	Herman Schmit, Donald E. Thomas	Array mapping in behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	array grouping, array mapping, memory components, memory design space, schedule length, scheduling, data structures, memory architecture, hardware description languages, binding, behavioral synthesis, access times, design representation, hardware synthesis, synthesis tool
35	Frank Vahid	Procedure exlining: a transformation for improved system and behavioral synthesis.	ISSS	1995	DBLP DOI BibTeX RDF	VHDL transformation tool, distinct computation, procedure exlining, procedure inlining, redundant sequences, statements, formal specification, distributed processing, VHDL, hardware description languages, remote procedure calls, behavioral synthesis, behavioral specification, system synthesis, procedure calls, synthesis tools
35	P. A. Subrahmanyam	What's in a Timing Discipline? Considerations in the Specification and Synthesis of Systems with Interacting Asynchronous and Synchronous Components.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
35	Mukund Sivaraman, Shail Aditya	Cycle-time aware architecture synthesis of custom hardware accelerators.	CASES	2002	DBLP DOI BibTeX RDF	embedded hardware architecture synthesis, operator chaining, target clock period, timing during scheduling, high-level synthesis, timing analysis, delay analysis, clock frequency
33	Alex Orailoglu	Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.	ICCD	1996	DBLP DOI BibTeX RDF	microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
33	Ahmad Abualsamid, Raed Alqadi, Parameswaran Ramanathan	Distributed synthesis of real-time computer systems.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	engineering workstations, distributed synthesis, design library, processor estimation, application constraints, suitable architecture identification, application task scheduling, runtime speedup, scheduling, real-time systems, computational complexity, parallelization, CAD, distributed processing, high level synthesis, high-level synthesis, software libraries, workstation network, real-time computer systems, resource estimation, component library
33	Nilanjan Mukherjee 0001, H. Kassab, Janusz Rajski, Jerzy Tyszer	Arithmetic built-in self test for high-level synthesis.	VTS	1995	DBLP DOI BibTeX RDF	arithmetic built-in self test, data path architectures, arithmetic blocks, compact test responses, testable circuit synthesis, logic testing, built-in self test, high level synthesis, high-level synthesis, integrated circuit testing, logic CAD, testability, abstract level, test vectors, state coverage
33	Steven D. Johnson	Manipulating Logical Organization with System Factorizations.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF
33	Sumit Gulwani	Dimensions in program synthesis.	PPDP	2010	DBLP DOI BibTeX RDF	deductive synthesis, inductive synthesis, sat solving, smt solving, machine learning, genetic programming, programming by demonstration, belief propagation, programming by examples, probabilistic inference
33	Lech Józwiak, Artur Chojnacki, Aleksander Slusarczyk	High-Quality Circuit Synthesis for Modern Technologies.	ISQED	2008	DBLP DOI BibTeX RDF	nano CMOS technologies, high-speed and low-power circuits, information-driven synthesis, multi-objective optimization, circuit synthesis
33	Ganesh Ramanarayanan, Kavita Bala	Constrained Texture Synthesis via Energy Minimization.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	detail synthesis, image analogies, Texture synthesis, super-resolution
33	Girish Venkataramani, Tiberiu Chelcea, Seth Copen Goldstein, Tobias Bjerregaard	SOMA: a tool for synthesizing and optimizing memory accesses in ASICs.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	high-level synthesis, memory synthesis
33	Minjie Zhang, Chengqi Zhang	Potential Cases, Methodologies, and Strategies of Synthesis of Solutions in Distributed Expert Systems.	IEEE Trans. Knowl. Data Eng.	1999	DBLP DOI BibTeX RDF	Distributed expert systems, synthesis of solutions, synthesis strategies, inductive methods, methodologies, analysis methods
33	Oleg Golubitsky, Sean M. Falconer, Dmitri Maslov	Synthesis of the optimal 4-bit reversible circuits.	DAC	2010	DBLP DOI BibTeX RDF	quantum computing, logic synthesis, reversible circuits
33	Li-Yi Wei, Jianwei Han, Kun Zhou 0001, Hujun Bao, Baining Guo, Heung-Yeung Shum	Inverse texture synthesis.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	GPU techniques, texture mapping, texture synthesis
33	Rastislav Bodík	Software synthesis with sketching.	PEPM	2008	DBLP DOI BibTeX RDF	synthesis
33	Jason Cong, Kirill Minkovich	Optimality study of logic synthesis for LUT-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	optimization, logic synthesis, technology mapping, Boolean logic, FPGA lookup table
33	Chuanliang Xia	Analysis of Properties of Petri Synthesis Net.	TAMC	2006	DBLP DOI BibTeX RDF	liveness and boundedness, Petri nets, synthesis, analysis
33	Steve Zelinka, Michael Garland	Jump map-based interactive texture synthesis.	ACM Trans. Graph.	2004	DBLP DOI BibTeX RDF	Interactive texture synthesis, jump maps, texturing surfaces
33	U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee	An algorithm for synthesis of large time-constrained heterogeneous adaptive systems.	ACM Trans. Design Autom. Electr. Syst.	2001	DBLP DOI BibTeX RDF	delay/cost table, hierarchical control data-flow graph, time-constrained synthesis, pipelining, reconfigurable computing, mixed integer linear programming, list scheduling
32	Krishnendu Chatterjee, Thomas A. Henzinger	Assume-Guarantee Synthesis.	TACAS	2007	DBLP DOI BibTeX RDF
32	Orna Kupferman, Nir Piterman, Moshe Y. Vardi	Safraless Compositional Synthesis.	CAV	2006	DBLP DOI BibTeX RDF
32	Keoncheol Shin, Taewhan Kim	Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
32	Yuan Yun, Liping Wang 0001, Liwen Guan	Dimensional synthesis of a 3-DOF parallel manipulator.	SMC (6)	2004	DBLP DOI BibTeX RDF
32	Áprád Furka	Combinatorial synthesis on macroscopic solid support units.	RECOMB	2003	DBLP DOI BibTeX RDF
32	Abderrazek Jemai, Polen Kission, Ahmed Amine Jerraya	Architectural Simulation in the Context of Behavioral Synthesis.	DATE	1998	DBLP DOI BibTeX RDF
32	Anand Raghunathan, Niraj K. Jha	SCALP: an iterative-improvement-based low-power data path synthesis system.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
31	Steffen Peter, Tony Givargis	Generation and Verification of Timing Attack Resilient Schedules During the High-Level Synthesis of Integrated Circuits.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
31	Wei Hu 0008, Armaiti Ardeshiricham, Lingjuan Wu, Ryan Kastner	Integrating Information Flow Tracking into High-Level Synthesis Design Flow.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
31	Sheikh Ariful Islam, Srinivas Katkoori	Behavioral Synthesis of Key-Obfuscated RTL IP.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
31	Anirban Sengupta, Mahendra Rathor	Hardware (IP) Watermarking During Behavioral Synthesis.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
31	S. T. Choden Konigsmark, Wei Ren, Martin D. F. Wong, Deming Chen	High-Level Synthesis for Minimizing Power Side-Channel Information Leakage.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
31	Christian Pilato, Donatella Sciuto, Francesco Regazzoni 0001, Siddharth Garg, Ramesh Karri	Protecting Hardware IP Cores During High-Level Synthesis.	Behavioral Synthesis for Hardware Security	2022	DBLP DOI BibTeX RDF
31	Ernst-Rüdiger Olderog, Bernhard Steffen, Wang Yi 0001	Model Checking, Synthesis, and Learning.	Model Checking, Synthesis, and Learning	2021	DBLP DOI BibTeX RDF
31	André Inácio Reis, Jody M. A. Matos	Physical Awareness Starting at Technology-Independent Logic Synthesis.	Advanced Logic Synthesis	2018	DBLP DOI BibTeX RDF
31	Leon Stok	EDA3.0: Implications to Logic Synthesis.	Advanced Logic Synthesis	2018	DBLP DOI BibTeX RDF
31	Bijoy Antony Jose, Sandeep K. Shukla	MRICDF: A Polychronous Model for Embedded Software Synthesis.	Synthesis of Embedded Software	2010	DBLP DOI BibTeX RDF
31	Sven Schewe	Software Synthesis is Hard - and Simple.	Software Synthesis	2009	DBLP BibTeX RDF
31	Rastislav Bodík, Orna Kupferman, Douglas R. Smith, Eran Yahav	09501 Abstracts Collection - Software Synthesis.	Software Synthesis	2009	DBLP BibTeX RDF
31	Luc De Raedt, Thomas G. Dietterich, Lise Getoor, Kristian Kersting, Stephen H. Muggleton	07161 Abstracts Collection -- Probabilistic, Logical and Relational Learning - A Further Synthesis.	Probabilistic, Logical and Relational Learning - A Further Synthesis	2007	DBLP BibTeX RDF
31	Henry A. Kautz, Wolfgang Thomas, Moshe Y. Vardi	05241 Abstracts Collection - Synthesis and Planning.	Synthesis and Planning	2005	DBLP BibTeX RDF
31	Henry A. Kautz, Wolfgang Thomas, Moshe Y. Vardi	05241 Executive Summary - Synthesis and Planning.	Synthesis and Planning	2005	DBLP BibTeX RDF
31	E. T. Kapuya, M. D. Edwards	Microarchitecture/Microcode Synthesis from VHDL.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer	Data Part Optimizations in the CALLAS Synthesis Environment.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	J. F. M. Theeuwen, H. M. A. M. Arts, Jos T. J. van Eijndhoven, H. J. H. Sleuters, J. H. P. Wijdeven	Module Generation in an Architectural Synthesis Environment.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	James Pardey	The Synthesis of a Parallel Controller from a Petri Net Model.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Inhag Park, Kevin O'Brien, Ahmed Amine Jerraya	AMICAL: Architectural Synthesis based on VHDL.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Andreas Münzner	BADGE - A synthesis tool for customized arithmetic building blocks.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	H. Belhadj, Laurent Gerbaux, Marie-Claude Bertrand, Gabriele Saucier	Specification and Synthesis of Communicating Finite State Machines.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	ChiLai Huang, Joseph Lis, Michael Quayle, Saurin Shroff	RTL Controller Synthesis.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Laurent Gerbaux, Régis Leveugle, Gabriele Saucier	Synthesis of large controllers using ROM or PLA generators.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Peter Marwedel	Implementations of IF-statements in the TODOS microarchitecture synthesis system.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	A. G. Jost, L. F. Wang, S. Periyalwar, William Robertson 0001	Automatic Layout Synthesis of Pipelined Multipliers for Systolic Arrays.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Alan J. Coppola, Marek A. Perkowski, Robert Anderson, Jeffrey S. Freedman, Edmund Pierzchala	Tokenized State Machine Model for Synthesis of Sequential Circuits into EPLDs and FPGAs.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Anne Mignotte, Marie-Claude Bertrand, Michel Crastes de Paulet, Jérôme Rampon, Gabriele Saucier	ASYL: A Control Driven RTL Synthesis System using Library Blocks.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Pierre Abouzeid, Régis Leveugle, Gabriele Saucier	Logic Synthesis for Automatic Layout.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Farhad Mavaddat	Data-Path Synthesis as Grammar Inference.	Synthesis for Control Dominated Circuits	1992	DBLP BibTeX RDF
31	Geoffrey M. Brown, Miriam Leeser	From Programs to Transistors: Verifying Hardware Synthesis Tools.	Hardware Specification, Verification and Synthesis	1989	DBLP DOI BibTeX RDF