Search results for "Triple-Modular"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
58	Zhe Zhang, Daxin Liu 0001, Zhengxian Wei, Changsong Sun	Research on Triple Modular Redundancy Dynamic Fault-Tolerant System Model.	IMSCCS (1)	2006	DBLP DOI BibTeX RDF	Dynamic fault-tolerant, Triple-Modular, Model, Reliability
58	Subhasish Mitra, Edward J. McCluskey	Word Voter: A New Voter Design for Triple Modular Redundant Systems.	VTS	2000	DBLP DOI BibTeX RDF	Word-Voter, TMR-Simplex, data integrity, Triple Modular redundancy (TMR), Voter
53	John C. Ramirez, Rami G. Melhem	Reducing Message Overhead in TMR Systems.	ICDCS	1999	DBLP DOI BibTeX RDF	reduced communication overhead, distributed systems, voting, triple modular redundancy, fault masking
47	Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique.	DFT	2006	DBLP DOI BibTeX RDF
45	John F. Wakerly	Transient Failures in Triple Modular Redundancy Systems with Sequential Modules.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	intermittent failures, synchronization, Fault-tolerant computing, sequential machines, triple modular redundancy, microcomputers, N-modular redundancy, transient failures
40	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
40	Paul D. Ezhilchelvan, Francisco V. Brasileiro, Neil A. Speirs	A Timeout-Based Message Ordering Protocol for a Lightweight Software Implementation of TMR Systems.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	process replication, physical and logical clocks, fault tolerance, agreement, Byzantine failures, Triple Modular Redundancy (TMR), message ordering
40	Paul D. Ezhilchelvan, Isi Mitrani, Santosh K. Shrivastava	A Performance Evaluation Study of Pipeline TMR Systems.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	pipeline TMR systems, concurrent replicated processing, processor failure rates, performance evaluation, performance evaluation, distributed system, distributed processing, redundancy, computer simulations, majority voting, triple modular redundant
30	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
30	Conrado Pilotto, José Rodrigo Azambuja, Fernanda Lima Kastensmidt	Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications.	SBCCI	2008	DBLP DOI BibTeX RDF	fault tolerance, FPGA, TMR, dynamic partial reconfiguration
30	Timothy J. Dysart, Peter M. Kogge	System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata.	DFT	2008	DBLP DOI BibTeX RDF
30	Wei Chen 0009, Rui Gong, Kui Dai, Fang Liu 0002, Zhiying Wang 0003	Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems.	CIT	2006	DBLP DOI BibTeX RDF
30	Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.	DATE	2005	DBLP DOI BibTeX RDF
30	Tongquan Wei, Kaijie Wu 0001, Ramesh Karri, Alex Orailoglu	Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.	ASP-DAC	2005	DBLP DOI BibTeX RDF
30	Michael J. Wirthlin	Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement.	FPGA	2004	DBLP DOI BibTeX RDF
29	Rui Gong, Wei Chen 0009, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	SEE tolerance, SEU tolerance, SET tolerance, Asynchronous circuit
29	Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.	Quadruple Time Redundancy Adders.	DFT	2003	DBLP DOI BibTeX RDF
28	Atin Mukherjee 0001, Anindya Sundar Dhar	Triple transistor based triple modular redundancy with embedded voter circuit.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
27	Cecilia Metra, Michele Favalli, Bruno Riccò	Compact and low power on-line self-testing voting scheme.	DFT	1997	DBLP DOI BibTeX RDF	on-line self-testing voting scheme, fault-tolerant techniques, reliability, power consumption, majority voting, triple modular redundancy, area overhead, majority logic, TMR systems
27	Dhiraj K. Pradhan, Nitin H. Vaidya	Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	roll-forward checkpointing scheme, active processing modules, duplex system redundancy, fault tolerant computing, redundancy, multiprocessing systems, fault-tolerant architecture, triple modular redundant system, multiprocessor environment
27	Kang G. Shin, Hagbae Kim	A Time Redundancy Approach to TMR Failures Using Fault-State Likelihoods.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	time redundancy approach, TMR failures, fault-state likelihoods, processing modules, disagreement detector, system reconfiguration, adaptive recovery method, fault tolerant computing, redundancy, digital simulation, simulation results, Bayes methods, voters, triple modular redundant system, Bayes theorem
27	John C. Sutton, Jon G. Bredeson	Minimal Redundant Logic for High Reliability and Irredundant Testability.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	Completely testable for single and multiple faults, control inputs and outputs, multilevel fan out free circuits, redundant connections, static logic hazard, triple modular redundancy
27	Daniel Davies, John F. Wakerly	Synchronization and Matching in Redundant Systems.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	N-modular redundancy (NMR), signal selection, synchronization, fault-tolerant computing, clocks, triple modular redundancy (TMR), microcomputers, Asynchronous networks, voters
27	C. V. Ramamoorthy, Yih-Wu Han	Reliability Analysis of Systems with Concurrent Error Detection.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	critical reliability of detector, detector redundant system, hybrid (N, S), N-tuple modular redundant system, reconfiguration switch, validating gate, Availability, subsystem, triple modular redundant system
27	Daniel P. Siewiorek	Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Compensating module failures, mission time improvement, triple modular redundancy (TMR), fault equivalence, fault dominance
25	Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube	A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.	DFT	2007	DBLP DOI BibTeX RDF
25	Debayan Bhaduri, Sandeep K. Shukla	NANOLAB: A Tool for Evaluating Reliability of Defect-Tolerant Nano Architectures.	ISVLSI	2004	DBLP DOI BibTeX RDF
25	Debayan Bhaduri, Sandeep K. Shukla	NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	CTMR, defect-tolerant architecture, nanotechnology, granularity, TMR, PRISM
25	Masaki Watanabe, Minoru Watanabe	Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation.	APCCAS	2019	DBLP DOI BibTeX RDF
21	Hüseyin Aysan, Sasikumar Punnekkat, Radu Dobrin	VTV - A Voting Strategy for Real-Time Systems.	PRDC	2008	DBLP DOI BibTeX RDF
21	Rui Gong, Kui Dai, Zhiying Wang 0003	Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.	PRDC	2008	DBLP DOI BibTeX RDF
18	Aleksa N. Maksimovic, Vojkan Nikolic, Dejan Vidojevic, Dragan M. Randelovic, Slavisa M. Djukanovic, Dragan M. Randjelovic	Using Triple Modular Redundancy for Threshold Determination in DDOS Intrusion Detection Systems.	IEEE Access	2024	DBLP DOI BibTeX RDF
18	Minoru Watanabe	Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock.	ISCAS	2023	DBLP DOI BibTeX RDF
18	Yu Xie, Wen-Yue Yu, Ning Zhang, He Chen, Yizhuang Xie	Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm.	DFT	2023	DBLP DOI BibTeX RDF
18	Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri	Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors.	IEEE Access	2022	DBLP DOI BibTeX RDF
18	Alan Torres-Alvarado, Luis Alberto Morales-Rosales, Ignacio Algredo-Badillo, Francisco López-Huerta, Mariana Lobato Báez, Juan Carlos López Pimentel	An SHA-3 Hardware Architecture against Failures Based on Hamming Codes and Triple Modular Redundancy.	Sensors	2022	DBLP DOI BibTeX RDF
18	Sami Sattar, Glenn E. R. Cowan	Single-Event Transient Tolerant Optical Receiver Using Triple Modular Redundancy.	ISCAS	2022	DBLP DOI BibTeX RDF
18	Lawrence T. Clark, Alen Duvnjak, Clifford Young-Sciortino, Matthew Cannon, John S. Brunhaver, Sapan Agarwal, Jereme Neuendank, Donald Wilson, Hugh J. Barnaby, Matthew J. Marinella	Self-correcting Flip-flops for Triple Modular Redundant Logic in a 12-nm Technology.	ISCAS	2022	DBLP DOI BibTeX RDF
18	Srinivas Katkoori, Sheikh Ariful Islam, Sujana Kakarla	Partial evaluation based triple modular redundancy for single event upset mitigation.	Integr.	2021	DBLP DOI BibTeX RDF
18	Ivan Babic, Aleksandar Miljkovic, Milan Cabarkapa, Vojkan Nikolic, Aleksandar Dordevic, Milan Randelovic, Dragan M. Randelovic	Triple Modular Redundancy Optimization for Threshold Determination in Intrusion Detection Systems.	Symmetry	2021	DBLP DOI BibTeX RDF
18	Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini	Side-Channel Attacks on Triple Modular Redundancy Schemes.	CoRR	2021	DBLP BibTeX RDF
18	Marco Bozzano, Alessandro Cimatti, Marco Gario, David Jones, Cristian Mattarei	Model-based Safety Assessment of a Triple Modular Generator with xSAP.	Formal Aspects Comput.	2021	DBLP DOI BibTeX RDF
18	Felipe Almeida, Levent Aksoy, Jaan Raik, Samuel Pagliarini	Side-Channel Attacks on Triple Modular Redundancy Schemes.	ATS	2021	DBLP DOI BibTeX RDF
18	Oliver Schrape, Anselm Breitenreiter, Carsten Schulze, Steffen Zeidler 0001, Milos Krstic	Radiation-Hardness-by-Design Latch-based Triple Modular Redundancy Flip-Flops.	LASCAS	2021	DBLP DOI BibTeX RDF
18	Bastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard 0001	Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing.	IOLTS	2021	DBLP DOI BibTeX RDF
18	Tooba Arifeen, Abdus Sami Hassan, Jeong-A Lee	Approximate Triple Modular Redundancy: A Survey.	IEEE Access	2020	DBLP DOI BibTeX RDF
18	Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Junchao Chen 0001, Milan Babic, Milos Krstic	Double cell upsets mitigation through triple modular redundancy.	Microelectron. J.	2020	DBLP DOI BibTeX RDF
18	Oliver Schrape, Marko S. Andjelkovic, Anselm Breitenreiter, Alexey Balashov, Milos Krstic	Design Concept for Radiation-Hardening of Triple Modular Redundancy TSPC Flip-Flops.	DSD	2020	DBLP DOI BibTeX RDF
18	Khaza Anuarul Hoque, Otmane Aït Mohamed, Yvon Savaria	Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs.	Reliab. Eng. Syst. Saf.	2019	DBLP DOI BibTeX RDF
18	Dimitris Agiakatsikas	High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms.		2019	RDF
18	Dmitriy V. Efanov	Triple Modular Sum Code as a New Code for the Tasks of Checkable Automation System Synthesis.	EWDTS	2018	DBLP DOI BibTeX RDF
18	Pietro Maris Ferreira, Martin Schaeffer, Adel Mezaour, Olivier Petit, Caroline Lelandais-Perrault, Gerald Charbonnier	A -40 to 250°C Triple Modular Redundancy Temperature Sensor for Turbofan Engines.	SBCCI	2018	DBLP DOI BibTeX RDF
18	Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt	Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits.	LATS	2018	DBLP DOI BibTeX RDF
18	Martin Krcma, Zdenek Kotásek, Jakub Lojda	Triple modular redundancy used in field programmable neural networks.	EWDTS	2017	DBLP DOI BibTeX RDF
18	Nagendra Babu Gunti, Karthikeyan Lingasubramanian	Fault Sensitive Neutralization of Hardware Trojans Using Multi-level Triple Modular Redundancy Scheme.	iNIS	2017	DBLP DOI BibTeX RDF
18	Pan Zheng, Qi Zheng, Zhankui Zeng, Liman Yang	The signal integrity design and simulation of triple modular redundant (TMR) computer.	CIS/RAM	2017	DBLP DOI BibTeX RDF
18	Dmitrii Kuvaiskii, Oleksii Oleksenko, Pramod Bhatotia, Pascal Felber, Christof Fetzer	Elzar: Triple Modular Redundancy using Intel Advanced Vector Extensions (technical report).	CoRR	2016	DBLP BibTeX RDF
18	Dmitrii Kuvaiskii, Oleksii Oleksenko, Pramod Bhatotia, Pascal Felber, Christof Fetzer	ELZAR: Triple Modular Redundancy Using Intel AVX (Practical Experience Report).	DSN	2016	DBLP DOI BibTeX RDF
18	Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper	SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing.	FPGA	2016	DBLP DOI BibTeX RDF
18	Dragos-Ronald Rugescu, Andrei Voinescu	Gracefully degrading triple modular redundancy in FPGA design with application to harsh radiation environments.	RoEduNet	2016	DBLP DOI BibTeX RDF
18	Hongjie He, Bao-Long Guo, Yunyi Yan	Area Estimation for Triple Modular Redundancy Field Programmable Gate Arrays.	ECC	2016	DBLP DOI BibTeX RDF
18	Jeffrey Prinzie, Michiel Steyaert, Paul Leroux, Jorgen Christiansen, Paulo Moreira	A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.	A-SSCC	2016	DBLP DOI BibTeX RDF
18	Giovanni Beltrame	Triple Modular Redundancy verification via heuristic netlist analysis.	PeerJ Comput. Sci.	2015	DBLP DOI BibTeX RDF
18	Jason Muhlestein, Hariprasath Venkatram, Jon Guerber, Allen Waters, Un-Ku Moon	Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters.	ICECS	2015	DBLP DOI BibTeX RDF
18	Rahul Parhi, Chris H. Kim, Keshab K. Parhi	Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR).	ISCAS	2015	DBLP DOI BibTeX RDF
18	Gunti Nagendra Babu, Aman Khatri, Karthikeyan Lingasubramanian	Realizing a security aware triple modular redundancy scheme for robust integrated circuits.	VLSI-SoC	2014	DBLP DOI BibTeX RDF
18	Dmitry Burlyaev, Pascal Fradet, Alain Girault	Verification-guided voter minimization in triple-modular redundant circuits.	DATE	2014	DBLP DOI BibTeX RDF
18	Lucas A. Tambara, Fernanda Lima Kastensmidt, Paolo Rech, Christopher Frost 0002	Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs.	DFT	2014	DBLP DOI BibTeX RDF
18	Stefan Resch, Andreas Steininger, Christoph Scherrer	Software Composability and Mixed Criticality for Triple Modular Redundant Architectures.	SASSUR@SAFECOMP	2013	DBLP BibTeX RDF
18	Liviu Agnola, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan	Simplified selective fault tolerance technique for protection of selected inputs via triple modular redundancy systems.	SACI	2012	DBLP DOI BibTeX RDF
18	Jakob Lechner	Designing Robust GALS Circuits with Triple Modular Redundancy.	EDCC	2012	DBLP DOI BibTeX RDF
18		Scheme to minimise short effects of single-event upsets in triple-modular redundancy.	IET Comput. Digit. Tech.	2010	DBLP DOI BibTeX RDF
18	Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Is triple modular redundancy suitable for yield improvement?	IET Comput. Digit. Tech.	2009	DBLP DOI BibTeX RDF
18	Baris Baykant Alagöz	Hierarchical Triple-Modular Redundancy (H-TMR) Network For Digital Systems	CoRR	2009	DBLP BibTeX RDF
18		Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation.	AHS	2009	DBLP DOI BibTeX RDF
18	Fernanda Lima Kastensmidt, Luca Sterpone, Luigi Carro, Matteo Sonza Reorda	On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs	CoRR	2007	DBLP BibTeX RDF
18	Sungjae Lee, Jae-Il Jung, Inhwan Lee	Voting structures for cascaded triple modular redundant modules.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
18	Wei Chen 0009, Rui Gong, Fang Liu 0002, Kui Dai, Zhiying Wang 0003	Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy.	ESA	2006	DBLP BibTeX RDF
18	Hyunki Kim, Hyeuntae Lee, Keyseo Lee	The design and analysis of AVTMR (all voting triple modular redundancy) and dual-duplex system.	Reliab. Eng. Syst. Saf.	2005	DBLP DOI BibTeX RDF
18	Renato Fernandes Hentschke, Felipe S. Marques 0001, Fernanda Lima 0001, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis 0001	Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.	SBCCI	2002	DBLP BibTeX RDF
18	Kumar K. Goswami, Ravishankar K. Iyer	A Simulation-Based Study of a Triple Modular Redundant System Using DEFEND.	Fault-Tolerant Computing Systems	1991	DBLP DOI BibTeX RDF
18	Daniel L. Kiskis, Kang G. Shin	Embedding triple-modular redundancy into a hypercube architecture.	C³P	1988	DBLP DOI BibTeX RDF
18	Frank M. Pittelli, Hector Garcia-Molina	Recovery in a Triple Modular Redundant Database System.	ICDCS	1987	DBLP BibTeX RDF
18	Wil J. van Gils	A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF
18	Frank M. Pittelli, Hector Garcia-Molina	Database Processing with Triple Modular Redundancy.	Symposium on Reliability in Distributed Software and Database Systems	1986	DBLP BibTeX RDF
18	Jacob A. Abraham, Daniel P. Siewiorek	An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
18	Francis P. Mathur, Algirdas Avizienis	Reliability analysis and architecture of a hybrid-redundant digital system: generalized triple modular redundancy with self-repair.	AFIPS Spring Joint Computing Conference	1970	DBLP DOI BibTeX RDF
18	Robert E. Lyons, Wouter Vanderkulk	The Use of Triple-Modular Redundancy to Improve Computer Reliability.	IBM J. Res. Dev.	1962	DBLP DOI BibTeX RDF
17	Fernanda Lima Kastensmidt, Gustavo Neuberger, Luigi Carro, Ricardo Reis 0001	Designing and testing fault-tolerant techniques for SRAM-based FPGAs.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	fault-tolerance, FPGA
17	Gholamreza Latif Shabgahi, Stuart Bennett	Adaptive Majority Voter: A Novel Voting Algorithm for Real-Time Fault-Tolerant Control Systems.	EUROMICRO	1999	DBLP DOI BibTeX RDF
17	Jianhui Jiang, Hongbao Shi, Yinghua Min, Xiaodong Zhao	A Novel NMR Structure with Concurrent Error Location Capabilities.	PRDC	1999	DBLP DOI BibTeX RDF
13	Xin He, Afshin Abdollahi	Cost aware fault tolerant logic synthesis in presence of soft errors.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	soft error rate, reliability, linear programming
13	Miaomiao Zhang, Zhiming Liu 0001, Charles Morisset, Anders P. Ravn	Design and Verification of Fault-Tolerant Components.	Methods, Models and Tools for Fault Tolerance	2009	DBLP DOI BibTeX RDF	Fault-tolerance, model checking, abstraction, real-time embedded systems
13	Mohammad-Hamed Razmkhah, Seyed Ghassem Miremadi, Alireza Ejlali	A Micro-FT-UART for Safety-Critical SoC-Based Applications.	ARES	2009	DBLP DOI BibTeX RDF
13	Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz	Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.	SBCCI	2009	DBLP DOI BibTeX RDF	reconfigurable router, fault tolerance, reliability, network-on-chip, NoC
13	Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi	Memory Sharing Approach for TMR Softcore Processor.	ARC	2009	DBLP DOI BibTeX RDF
13	Ashay Narsale, Michael C. Huang 0001	Variation-tolerant hierarchical voltage monitoring circuit for soft error detection.	ISQED	2009	DBLP DOI BibTeX RDF
13	Lorenzo Petroli, Carlos Arthur Lang Lisbôa, Fernanda Lima Kastensmidt, Luigi Carro	Majority Logic Mapping for Soft Error Dependability.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Majority gates, Fault tolerance, SET, Majority logic
13	Luca Sterpone, M. A. Aguirre, Jonathan Noel Tombs, Hipólito Guzmán-Miranda	On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.	DATE	2008	DBLP DOI BibTeX RDF
13	Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke	The StageNet fabric for constructing resilient multicore systems.	MICRO	2008	DBLP DOI BibTeX RDF