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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 34 occurrences of 28 keywords
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Results
Found 51 publication records. Showing 51 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
65 | Tao Wang, Irene Cheng 0001 |
Generation of Unit-Width Curve Skeletons Based on Valence Driven Spatial Median (VDSM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVC (1) ![In: Advances in Visual Computing, 4th International Symposium, ISVC 2008, Las Vegas, NV, USA, December 1-3, 2008. Proceedings, Part I, pp. 1051-1060, 2008, Springer, 978-3-540-89638-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
51 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian |
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 857-862, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis |
47 | Shuming Chen, Xiangyuan Liu |
A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 75-82, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
differential-signaling, insertion methodology, on-chip interconnects, low-swing |
47 | Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner |
A linear model for high-level delay estimation in VDSM on-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1078-1081, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Shahin Nazarian, Massoud Pedram, Emre Tuncer |
An empirical study of crosstalk in VDSM technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 317-322, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
automatic test pattern generation (ATPG) tool, crosstalk induced slowdown and speedup, transition time, static timing analysis (STA), skew |
47 | Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera |
Automatic Generation of Standard Cell Library in VDSM Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 36-41, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning |
Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 565-573, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Alexander Korshak, Jyh-Chwen Lee |
An Effective Current Source Cell Model for VDSM Delay Calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 296-300, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang |
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 59-64, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
36 | Han Liang, Piyush Mishra, Kaijie Wu 0001 |
Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(2), pp. 243-252, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy |
36 | Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene |
On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 14th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2006), 2-4 August 2006, Taipei, Taiwan, pp. 71-76, 2006, IEEE Computer Society, 0-7695-2572-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra |
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 8-12, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Ali Chehab, Saurabh Patel, Rafic Z. Makki |
Scaling of iDDT Test Methods for Random Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 22(1), pp. 11-22, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
dynamic power supply current, design for current testability, resistive opens, resistive bridges, very deep sub-micron technologies, VDSM, fault simulation |
29 | Matthew J. Vowels, Necati Cihan Camgöz, Richard Bowden |
VDSM: Unsupervised Video Disentanglement with State-Space Modeling and Deep Mixtures of Experts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2103.07292, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
29 | Matthew J. Vowels, Necati Cihan Camgöz, Richard Bowden |
VDSM: Unsupervised Video Disentanglement With State-Space Modeling and Deep Mixtures of Experts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: IEEE Conference on Computer Vision and Pattern Recognition, CVPR 2021, virtual, June 19-25, 2021, pp. 8176-8186, 2021, Computer Vision Foundation / IEEE. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
29 | Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra |
An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, January 30 - February 2, 2012, pp. 163-168, 2012, IEEE, 978-1-4673-0770-3. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Mahmoud Zangeneh, Nasser Masoumi |
An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCTD ![In: 19th European Conference on Circuit Theory and Design, ECCTD 2009, Antalya, Turkey, August 23-27, 2009, pp. 470-475, 2009, IEEE, 978-1-4244-3896-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
29 | Ashok Narasimhan, Karthik Srinivasan, Ramalingam Sridhar |
A High-Performance Router Design for VDSM NoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: Proceedings 2005 IEEE International SOC Conference, September 25-28, 2005, Washington Dulles Airport, Herndon, VA, USA, pp. 301-304, 2005, IEEE, 0-7803-9264-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis |
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(4), pp. 413-421, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
single fault propagation, fault simulation, soft-errors, single event upsets |
29 | Brady Benware |
Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1418, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Soroush Abbaspour, Massoud Pedram |
Calculating the effective capacitance for the RC interconnect in VDSM technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 43-48, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Michael Nicolaidis |
Reliability Threats in VDSM - Shortcomings in Conventional Test and Fault-Tolerance Alternatives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1282, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Ichiang Lin, Chien-In Henry Chen |
Timing Challenges for Very Deep Sub-Micron (VDSM) IC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 15(3), pp. 557-562, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis |
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 3rd Latin American Test Workshop, LATW 2002, Montevideo, Uruguay, February 10-13, 2002., pp. 126-129, 2002, IEEE. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
29 | Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis |
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 99-107, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Lifeng Wu, Zhihong Liu |
Full-Chip Reliability Simulation for VDSM Integrated Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 41(9-10), pp. 1273-1278, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | David Bernard, Christian Landrault, Pascal Nouet |
Interconnect Capacitance Modelling in a VDSM CMOS Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SOC ![In: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, pp. 133-144, 2001, Kluwer, 1-4020-7148-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
29 | Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal |
Transistor Modeling for the VDSM Era. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 37-44, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
field effect transistors, parameter extraction, SPICE, device modeling |
29 | Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo |
A BIST approach for very deep sub-micron (VDSM) defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 283-291, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
29 | Kenneth D. Wagner |
Robust Scan-Based Logic Test in VDSM Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 32(11), pp. 66-74, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
18 | Yici Cai, Qiang Zhou 0001, Xianlong Hong, Rui Shi, Yang Wang |
Application of optical proximity correction technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(2), pp. 213-224, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
layout, rules-based, OPC, model-based, IC |
18 | Shantanu Dutt, Hasan Arslan |
Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 768-773, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Xiangyuan Liu, Shuming Chen |
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, pp. 91-94, 2006, ACM, 1-59593-347-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-swing interconnect, delay, power, estimation model |
18 | Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar |
A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 491-494, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
18 | Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel |
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 169-179, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
address decoders, core-cells, memory testing, dynamic faults |
18 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan |
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(5), pp. 551-561, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults |
18 | Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar |
RG-SRAM: A Low Gate Leakage Memory Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 295-296, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Virgilio Fernandez, Eby G. Friedman |
Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 612-615, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn |
An efficient algorithm for simultaneous wire permutation, inversion, and spacing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 109-112, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Daniele Rossi 0001, Martin Omaña 0001, Fabio Toma, Cecilia Metra |
Multiple Transient Faults in Logic: An Issue for Next Generation ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 352-360, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar |
A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 634-639, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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18 | Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan |
Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 266-271, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre |
Yield Analysis of Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 103-108, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski |
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1285-1294, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim |
Charge-Sharing-Problem Reduced Split-Path Domino Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 201-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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18 | Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra |
Power Consumption of Fault Tolerant Codes: the Active Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece, pp. 61-67, 2003, IEEE Computer Society, 0-7695-1968-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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18 | Eric Dupont, Michael Nicolaidis |
Robustness IPs for Reliability and Security of SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 357-364, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
18 | Yih-Chih Chou, Youn-Long Lin |
A 3-step approach for performance-driven whole-chip routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 187-191, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
18 | Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai |
Timing optimization on routed designs with incremental placementand routing characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2), pp. 188-196, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
18 | Yervant Zorian |
Yield Improvement and Repair Trade-Off for Large Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 69-70, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
silicon repair, BIST, DFM, Yield improvement |
18 | Reisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro Toyota, Kiyokazu Nishi, Akira Motohara |
Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 347-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
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