Search results for "VDSM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
65	Tao Wang, Irene Cheng 0001	Generation of Unit-Width Curve Skeletons Based on Valence Driven Spatial Median (VDSM).	ISVC (1)	2008	DBLP DOI BibTeX RDF
51	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
47	Shuming Chen, Xiangyuan Liu	A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.	NOCS	2007	DBLP DOI BibTeX RDF	differential-signaling, insertion methodology, on-chip interconnects, low-swing
47	Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner	A linear model for high-level delay estimation in VDSM on-chip interconnects.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
47	Shahin Nazarian, Massoud Pedram, Emre Tuncer	An empirical study of crosstalk in VDSM technologies.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	automatic test pattern generation (ATPG) tool, crosstalk induced slowdown and speedup, transition time, static timing analysis (STA), skew
47	Masanori Hashimoto, Kazunori Fujimori, Hidetoshi Onodera	Automatic Generation of Standard Cell Library in VDSM Technologies.	ISQED	2004	DBLP DOI BibTeX RDF
47	Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning	Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.	ITC	2003	DBLP DOI BibTeX RDF
47	Alexander Korshak, Jyh-Chwen Lee	An Effective Current Source Cell Model for VDSM Delay Calculation.	ISQED	2001	DBLP DOI BibTeX RDF
47	Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang	High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.	ICCD	2000	DBLP DOI BibTeX RDF
36	Han Liang, Piyush Mishra, Kaijie Wu 0001	Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Concurrent error detection, register-transfer level, single-event upsets, hardware redundancy
36	Hua Wang, Miguel Miranda, Francky Catthoor, Wim Dehaene	On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.	MTDT	2006	DBLP DOI BibTeX RDF
36	Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, A. H. Nieuwland, Cecilia Metra	Coding Scheme for Low Energy Consumption Fault-Tolerant Bus.	IOLTW	2002	DBLP DOI BibTeX RDF
33	Ali Chehab, Saurabh Patel, Rafic Z. Makki	Scaling of iDDT Test Methods for Random Logic Circuits.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	dynamic power supply current, design for current testability, resistive opens, resistive bridges, very deep sub-micron technologies, VDSM, fault simulation
29	Matthew J. Vowels, Necati Cihan Camgöz, Richard Bowden	VDSM: Unsupervised Video Disentanglement with State-Space Modeling and Deep Mixtures of Experts.	CoRR	2021	DBLP BibTeX RDF
29	Matthew J. Vowels, Necati Cihan Camgöz, Richard Bowden	VDSM: Unsupervised Video Disentanglement With State-Space Modeling and Deep Mixtures of Experts.	CVPR	2021	DBLP BibTeX RDF
29	Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, Charles H.-P. Wen, Jayanta Bhadra	An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology.	ASP-DAC	2012	DBLP DOI BibTeX RDF
29	Mahmoud Zangeneh, Nasser Masoumi	An analytical delay reduction strategy for buffer-inserted global interconnects in VDSM technologies.	ECCTD	2009	DBLP DOI BibTeX RDF
29	Ashok Narasimhan, Karthik Srinivasan, Ramalingam Sridhar	A High-Performance Router Design for VDSM NoCs.	SoCC	2005	DBLP DOI BibTeX RDF
29	Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis	Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	single fault propagation, fault simulation, soft-errors, single event upsets
29	Brady Benware	Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs.	ITC	2004	DBLP DOI BibTeX RDF
29	Soroush Abbaspour, Massoud Pedram	Calculating the effective capacitance for the RC interconnect in VDSM technologies.	ASP-DAC	2003	DBLP DOI BibTeX RDF
29	Michael Nicolaidis	Reliability Threats in VDSM - Shortcomings in Conventional Test and Fault-Tolerance Alternatives.	ITC	2003	DBLP DOI BibTeX RDF
29	Ichiang Lin, Chien-In Henry Chen	Timing Challenges for Very Deep Sub-Micron (VDSM) IC.	VLSI Design	2002	DBLP DOI BibTeX RDF
29	Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis	Simulating Single Event Transients in VDSM ICs for Ground Level Radiation.	LATW	2002	DBLP BibTeX RDF
29	Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis	New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs.	DFT	2002	DBLP DOI BibTeX RDF
29	Lifeng Wu, Zhihong Liu	Full-Chip Reliability Simulation for VDSM Integrated Circuits.	Microelectron. Reliab.	2001	DBLP DOI BibTeX RDF
29	David Bernard, Christian Landrault, Pascal Nouet	Interconnect Capacitance Modelling in a VDSM CMOS Technology.	VLSI-SOC	2001	DBLP BibTeX RDF
29	Michael S. Shur, Tor A. Fjeldly, Trond Ytterdal	Transistor Modeling for the VDSM Era.	ISQED	2000	DBLP DOI BibTeX RDF	field effect transistors, parameter extraction, SPICE, device modeling
29	Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo	A BIST approach for very deep sub-micron (VDSM) defects.	ITC	2000	DBLP DOI BibTeX RDF
29	Kenneth D. Wagner	Robust Scan-Based Logic Test in VDSM Technologies.	Computer	1999	DBLP DOI BibTeX RDF
18	Yici Cai, Qiang Zhou 0001, Xianlong Hong, Rui Shi, Yang Wang	Application of optical proximity correction technology.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	layout, rules-based, OPC, model-based, IC
18	Shantanu Dutt, Hasan Arslan	Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations.	DATE	2006	DBLP DOI BibTeX RDF
18	Xiangyuan Liu, Shuming Chen	Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	low-swing interconnect, delay, power, estimation model
18	Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar	A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.	VLSI Design	2006	DBLP DOI BibTeX RDF
18	Simone Borri, Magali Hage-Hassan, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	address decoders, core-cells, memory testing, dynamic faults
18	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
18	Charan Thondapu, Praveen Elakkumanan, Ramalingam Sridhar	RG-SRAM: A Low Gate Leakage Memory Design.	ISVLSI	2005	DBLP DOI BibTeX RDF
18	Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Virgilio Fernandez, Eby G. Friedman	Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Shanq-Jang Ruan, Edwin Naroska, Uwe Schwiegelshohn	An efficient algorithm for simultaneous wire permutation, inversion, and spacing.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Daniele Rossi 0001, Martin Omaña 0001, Fabio Toma, Cecilia Metra	Multiple Transient Faults in Logic: An Issue for Next Generation ICs.	DFT	2005	DBLP DOI BibTeX RDF
18	Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar	A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
18	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
18	Davide Appello, Alessandra Fudoli, Katia Giarda, Emil Gizdarski, Ben Mathew, Vincenzo Tancorre	Yield Analysis of Logic Circuits.	VTS	2004	DBLP DOI BibTeX RDF
18	Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski	Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model.	ITC	2004	DBLP DOI BibTeX RDF
18	Seoksoo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim	Charge-Sharing-Problem Reduced Split-Path Domino Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
18	Daniele Rossi 0001, Steven V. E. S. van Dijk, Richard P. Kleihorst, André K. Nieuwland, Cecilia Metra	Power Consumption of Fault Tolerant Codes: the Active Elements.	IOLTS	2003	DBLP DOI BibTeX RDF
18	Eric Dupont, Michael Nicolaidis	Robustness IPs for Reliability and Security of SoCs.	ITC	2002	DBLP DOI BibTeX RDF
18	Yih-Chih Chou, Youn-Long Lin	A 3-step approach for performance-driven whole-chip routing.	ASP-DAC	2001	DBLP DOI BibTeX RDF
18	Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai	Timing optimization on routed designs with incremental placementand routing characterization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	Yervant Zorian	Yield Improvement and Repair Trade-Off for Large Embedded Memories.	DATE	2000	DBLP DOI BibTeX RDF	silicon repair, BIST, DFM, Yield improvement
18	Reisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro Toyota, Kiyokazu Nishi, Akira Motohara	Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF