Search results for "WSI"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Moritoshi Yasunaga, I. Hachiya, K. Moki, Jung Hwan Kim	Fault-tolerant self-organizing map implemented by wafer-scale integration.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
97	Wu Jigang, Heiko Schröder, Thambipillai Srikanthan	New Architecture and Algorithms for Degradable VLSI/WSI Arrays.	COCOON	2002	DBLP DOI BibTeX RDF	Degradable VLSI/WSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm
81	Nobuhiro Tomabechi	Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems.	DFT	1999	DBLP DOI BibTeX RDF	subsystem-dividing, yield, defect-tolerant, WSI, multi-dimensional
80	Chor Ping Low	An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Degradable VLSI/WSI arrays, efficient heuristic, NP-completeness, greedy algorithm
74	C. Sul, Robert D. McLeod, Witold Pedrycz	Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
63	Yung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen	An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.	VLSI Design	1995	DBLP DOI BibTeX RDF	switching network fault diagnosis, reconfigurable VLSI/WSI array processors, switching network defects, killing error, testing circuit overhead, diagnosis time, mesh array, VLSI, parallel architectures, fault diagnosis, reconfigurable architectures, multiple faults, switching networks, wafer-scale integration, testing quality
63	Sy-Yen Kuo, Kuochen Wang	Fault diagnosis in reconfigurable VLSI and WSI processor arrays.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF	design for diagnosability, VLSI/WSI processor array, fault diagnosis, reconfiguration, yield enhancement
57	R. M. Lea, P. T. Tetnowski, M. Covic	A Reconfigurable WSI Massively Data-Parallel Processing Device for Cost-Effective 3D Sensor Data Processing.	DFT	2000	DBLP DOI BibTeX RDF
57	Chor Ping Low, Hon Wai Leong	On the reconfiguration of degradable VLSI/WSI arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
51	Nader Mir-Fakhraei	ATM switching architectures for wafer-scale integration.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
51	José G. Delgado-Frias, D. M. Green	BVE: a wafer-scale engine for differential equation computation.	ICS	1988	DBLP DOI BibTeX RDF
47	Vwani P. Roychowdhury, Jehoshua Bruck, Thomas Kailath	Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	reconfiguring processor arrays, flexible interconnection structure, array grid model, single-track switches, single-track model, parallel processing, VLSI, VLSI, fault tolerant computing, reconfiguration, polynomial time algorithm, faulty processors, WSI
47	Hee Yong Youn, Adit D. Singh	On Implementing Large Binary Tree Architectures in VLSI and WSI.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	large binary tree architectures, maximum edge length, H-tree layouts, VLSI, VLSI, layout, trees (mathematics), circuit layout CAD, processing elements, propagation delay, fault-tolerant designs, WSI, two-dimensional array
46	Yung-Yuan Chen, Shambhu J. Upadhyaya, Ching-Hwa Cheng	A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF	VLSI/WSI array processor, reconfiguration process, redundancy scheme, switch programming, yield simulation, performance analysis
46	Mingshien Wang, Michal Cutler, Stephen Y. H. Su	Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	distributed defects, VLSI/WSI mesh array processors, two-level redundancy, parallel rectangular, operation reliability, clustered defects, complexity, parallel processing, VLSI, fault tolerant computing, reconfiguration, processing elements, optimization technique, combinatorial analysis, manufacturing yield
41	Nian-Feng Tzeng	Reconfiguration and Analysis of a Fault-Tolerant Circular Butterfly Parallel System.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	fault-tolerant circular butterfly parallel system, interconnection pattern, spare processing elements, VLSI, fault tolerant computing, reconfiguration, reconfigurable architectures, multiprocessorinterconnection networks, WSI
40	M. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins	VLSI/WSI Designs for Folded Cube-Connected Cycles Architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	Building block design, fault-tolerance, reliability, parallel architecture, layout, yield
40	Yung-Yuan Chen, Ching-Hwa Cheng, Yung-Ci Chou	An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors.	EDCC	1994	DBLP DOI BibTeX RDF
40	Sy-Yen Kuo, Ing-Yi Chen	Efficient reconfiguration algorithms for degradable VLSI/WSI arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
40	Hussam Y. Abujbara, Sami A. Al-Arian	Self-testing and self-reconfiguration architecture for 2-D WSI arrays.	SPDP	1990	DBLP DOI BibTeX RDF
40	Wu Jigang, Thambipillai Srikanthan	A Run-time Reconfiguration Algorithm for VLSI Arrays.	VLSI Design	2003	DBLP DOI BibTeX RDF	Degradable VLSI/WSI array, fault-tolerance, reconfiguration, NP-completeness, greedy algorithm
34	Wu Jigang, Thambipillai Srikanthan, Heiko Schröder	Efficient reconfigurable techniques for VLSI arrays with 6-port switches.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
34	Vladimir Zadorozhny, Louiqa Raschid, Maria-Esther Vidal, Tolga Urhan, Laura Bright	Efficient evaluation of queries in a mediator for WebSources.	SIGMOD Conference	2002	DBLP DOI BibTeX RDF	World Wide Web (WWW)
34	Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim	A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI.	DFT	2000	DBLP DOI BibTeX RDF
34	Susumu Horiguchi, Masayuki Konuki	The Horizontal Rotate Crossed Cube HCQ Interconnection Network.	ISPAN	1997	DBLP DOI BibTeX RDF
34	Chienhua Chen, Dharma P. Agrawal, J. Richard Burke	dBCube: A New Class of Hierarchical Multiprocessor Interconnection Networks with Area Efficient Layout.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	dBCube, hierarchical multiprocessor interconnection networks, area efficient layout, node connectivity, compound graph, necklace, performance evaluation, VLSI, graphs, hypercube, multiprocessor interconnection networks, hierarchical networks, wafer scale integration, de Bruijn graph, hypercube topology, Communication locality
24	Sy-Yen Kuo, Sheng-Chiech Liang	Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	online error correction, two level pipelining, real-time systolic sorting arrays, online error detection, VLSI sorting arrays, functional errors, data errors, real-time systems, parallel algorithms, VLSI, sorting, error correction codes, systolic arrays, error detection codes, concurrent error detection, high-throughput, self-checking, WSI, concurrent error correction
24	Mengly Chean, José A. B. Fortes	The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	full-use-of-suitable repairs approach, fault-tolerant processor arrays, indicator vector, surplus vector, VLSI, VLSI, fault tolerant computing, interconnect, WSI, electronic engineering computing, hardware reconfiguration
24	Yinan N. Shen, Fabrizio Lombardi	Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection.	J. Electron. Test.	1990	DBLP DOI BibTeX RDF	redundant memory, diagnosis, yield, repair, WSI
24	Fred J. Meyer, Dhiraj K. Pradhan	Modeling Defect Spatial Distribution.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	defect spatial distribution modelling, center-satellite model, wafers, redundancy techniques, cluster, VLSI, fault tolerant computing, circuit CAD, fault-tolerant designs, yield models, WSI
23	Gianpaolo Bontempo, Federico Bolelli, Angelo Porrello, Simone Calderara, Elisa Ficarra	A Graph-Based Multi-Scale Approach With Knowledge Distillation for WSI Classification.	IEEE Trans. Medical Imaging	2024	DBLP DOI BibTeX RDF
23	Hong Liu, Haosen Yang, Paul J. van Diest, Josien P. W. Pluim, Mitko Veta	WSI-SAM: Multi-resolution Segment Anything Model (SAM) for histopathology whole-slide images.	CoRR	2024	DBLP DOI BibTeX RDF
23	Md. Shakhawat Hossain, Galib Muhammad Shahriar, M. M. Mahbubul Syeed, Mohammad Faisal Uddin, Mahady Hasan, Md. Sakir Hossain, Rubina Bari	Tissue Artifact Segmentation and Severity Assessment for Automatic Analysis Using WSI.	IEEE Access	2023	DBLP DOI BibTeX RDF
23	Geng Hu, Baomin Wang, Boxian Hu, Dan Chen, Lihua Hu, Cheng Li, Yu An, Guiping Hu, Guang Jia	From WSI-level to patch-level: Structure prior-guided binuclear cell fine-grained detection.	Medical Image Anal.	2023	DBLP DOI BibTeX RDF
23	Jinshan Cao	Geometric Calibration of the Whiskbroom DaQi-1 WSI Based on an Equivalent Linear-Array CCD.	IEEE Trans. Geosci. Remote. Sens.	2023	DBLP DOI BibTeX RDF
23	Philippe Weitz, Viktoria Sartor, Balazs Acs, Stephanie Robertson, Daniel Budelmann, Johan Hartman, Mattias Rantalainen	Increasing the usefulness of already existing annotations through WSI registration.	CoRR	2023	DBLP DOI BibTeX RDF
23	Seongho Keum, Sanghyun Kim, Soojeong Lee, Juho Lee 0001	Slot-Mixup with Subsampling: A Simple Regularization for WSI Classification.	CoRR	2023	DBLP DOI BibTeX RDF
23	Pedro C. Neto, Diana Montezuma, Sara Pires de Oliveira, Domingos Oliveira, João Fraga, Ana Monteiro, João C. Monteiro, Liliana Ribeiro, Sofia Gonçalves, Stefan Reinhard, Inti Zlobec, Isabel M. Pinto, Jaime S. Cardoso 0001	A CAD System for Colorectal Cancer from WSI: A Clinically Validated Interpretable ML-based Prototype.	CoRR	2023	DBLP DOI BibTeX RDF
23	Peyman Nejat, Areej Alsaafin, Ghazal Alabtah, Nneka I. Comfere, Aaron Mangold, Dennis Murphree, Patricija Zot, Saba Yasir, Joaquin J. Garcia, Hamid R. Tizhoosh	Creating an Atlas of Normal Tissue for Pruning WSI Patching Through Anomaly Detection.	CoRR	2023	DBLP DOI BibTeX RDF
23	Xiangyu Liu, Zhenyu Liu, Ye Yan, Kai Wang, Aodi Wang, Xiongjun Ye, Liwei Wang, Wei Wei 0022, Bao Li, Caixia Sun, Wei He, Xuehua Zhu, Zenan Liu, Jiangang Liu, Jian Lu, Jie Tian 0001	Development of Prognostic Biomarkers by TMB-Guided WSI Analysis: A Two-Step Approach.	IEEE J. Biomed. Health Informatics	2023	DBLP DOI BibTeX RDF
23	Anwar Khan, Seunghyeon Han, Naveed Ilyas, Yong-Moon Lee, Boreom Lee	CervixFormer: A Multi-scale swin transformer-Based cervical pap-Smear WSI classification framework.	Comput. Methods Programs Biomed.	2023	DBLP DOI BibTeX RDF
23	Namitha Guruprasad, Penny J. Barnes, Amir Akbarnejad, Gilbert Bigras, Nilanjan Ray	A Closer Look at Weak Supervision's Limitations in WSI Recurrence Score Prediction.	BIBM	2023	DBLP DOI BibTeX RDF
23	Tomé Albuquerque, Mei Ling Fang, Benedikt Wiestler, Claire Delbridge, Maria João M. Vasconcelos, Jaime S. Cardoso 0001, Peter Schüffler	Multimodal Context-Aware Detection of Glioma Biomarkers Using MRI and WSI.	MTSAIL/LEAF/AI4Treat/MMMI/REMIA@MICCAI	2023	DBLP DOI BibTeX RDF
23	Kun Wu, Yushan Zheng, Jun Shi 0006, Fengying Xie, Zhiguo Jiang	Position-Aware Masked Autoencoder for Histopathology WSI Representation Learning.	MICCAI (6)	2023	DBLP DOI BibTeX RDF
23	Baomin Wang, Geng Hu, Dan Chen, Lihua Hu, Cheng Li, Yu An, Guiping Hu, Guang Jia	From WSI-level to Patch-level: Structure Prior Guided Binuclear Cell Fine-grained Detection.	CoRR	2022	DBLP DOI BibTeX RDF
23	Juan I. Pisula, Katarzyna Bozek	Language models are good pathologists: using attention-based sequence reduction and text-pretrained transformers for efficient WSI classification.	CoRR	2022	DBLP DOI BibTeX RDF
23	Ruixiang Geng, Qing Liu, Shuo Feng, Yixiong Liang	Learning Deep Pathological Features for WSI-Level Cervical Cancer Grading.	ICASSP	2022	DBLP DOI BibTeX RDF
23	Taimoor Shakeel Sheikh, Jee Yeon Kim, Migyung Cho	Refined Attention Module for WSI Cancer Diagnosis.	ICKII	2022	DBLP DOI BibTeX RDF
23	Yushan Zheng, Zhiguo Jiang, Fengying Xie, Jun Shi 0006, Haopeng Zhang 0001, Jianguo Huai, Ming Cao, Xiaomiao Yang	Diagnostic Regions Attention Network (DRA-Net) for Histopathology WSI Recommendation and Retrieval.	IEEE Trans. Medical Imaging	2021	DBLP DOI BibTeX RDF
23	Yushan Zheng, Zhiguo Jiang, Haopeng Zhang 0001, Fengying Xie, Jun Shi 0006, Chenghai Xue	Histopathology WSI Encoding based on GCNs for Scalable and Efficient Retrieval of Diagnostically Relevant Regions.	CoRR	2021	DBLP BibTeX RDF
23	Rocío del Amor, Laëtitia Launet, Adrián Colomer, Anaïs Moscardó, Andrés Mosquera-Zamudio, Carlos Monteagudo, Valery Naranjo	An Attention-based Weakly Supervised framework for Spitzoid Melanocytic Lesion Diagnosis in WSI.	CoRR	2021	DBLP BibTeX RDF
23	Daniele Perlo, Enzo Tartaglione, Luca Bertero, Paola Cassoni, Marco Grangetto	Dysplasia grading of colorectal polyps through CNN analysis of WSI.	CoRR	2021	DBLP BibTeX RDF
23	Ruiwei Feng, Xuechen Liu, Jintai Chen, Danny Z. Chen, Honghao Gao, Jian Wu 0001	A Deep Learning Approach for Colonoscopy Pathology WSI Analysis: Accurate Segmentation and Classification.	IEEE J. Biomed. Health Informatics	2021	DBLP DOI BibTeX RDF
23	Lourdes Duran-Lopez, Juan Pedro Dominguez-Morales, Antonio Felix Conde-Martin, Saturnino Vicente Diaz, Alejandro Linares-Barranco	PROMETEO: A CNN-Based Computer-Aided Diagnosis System for WSI Prostate Cancer Detection.	IEEE Access	2020	DBLP DOI BibTeX RDF
23	Neeta Kumar, Ruchika Gupta, Sanjay Gupta	Whole Slide Imaging (WSI) in Pathology: Current Perspectives and Future Directions.	J. Digit. Imaging	2020	DBLP DOI BibTeX RDF
23	P. Venkatappareddy, Brejesh Lall	A Novel Thresholding Methodology Using WSI EMD and Adaptive Homomorphic Filter.	IEEE Trans. Circuits Syst. II Express Briefs	2020	DBLP DOI BibTeX RDF
23	Linmin Pei, Wei-Wen Hsu, Ling-An Chiang, Jing-Ming Guo, Khan M. Iftekharuddin, Rivka Colen	A Hybrid Convolutional Neural Network Based-Method for Brain Tumor Classification Using mMRI and WSI.	BrainLes@MICCAI (2)	2020	DBLP DOI BibTeX RDF
23	Yushan Zheng, Zhiguo Jiang, Haopeng Zhang 0001, Fengying Xie, Jun Shi 0006, Chenghai Xue	Adaptive color deconvolution for histological WSI normalization.	Comput. Methods Programs Biomed.	2019	DBLP DOI BibTeX RDF
23	Germán Corredor, Juan D. García-Arteaga, Viviana Arias, Eduardo Romero 0001	Learning Basal Cell Carcinoma Patterns by Fusing Pathologists' WSI Navigations and Graph-Based Centrality Features.	ISBI	2019	DBLP DOI BibTeX RDF
23	Jiandong Ye, Yihao Luo, Chuang Zhu, Fang Liu, Yue Zhang	Breast Cancer Image Classification on WSI with Spatial Correlations.	ICASSP	2019	DBLP DOI BibTeX RDF
23	Haomiao Ni, Hong Liu 0007, Kuansong Wang, Xiangdong Wang, Xunjian Zhou, Yueliang Qian	WSI-Net: Branch-Based and Hierarchy-Aware Network for Segmentation and Classification of Breast Histopathological Whole-Slide Images.	MLMI@MICCAI	2019	DBLP DOI BibTeX RDF
23	Ha-Duong Ngo, Biswajit Mukhopadhyay, Piotr Mackowiak, Kevin Kröhnert, Oswin Ehrmann, Klaus-Dieter Lang	A WSi-WSiN-Pt Metallization Scheme for Silicon Carbide-Based High Temperature Microsystems.	Micromachines	2016	DBLP DOI BibTeX RDF
23	Hans-Peter Zorn, Iryna Gurevych	UKP-WSI: UKP Lab Semeval-2013 Task 11 System Description.	SemEval@NAACL-HLT	2013	DBLP BibTeX RDF
23	Ted Pedersen	Duluth-WSI: SenseClusters Applied to the Sense Induction Task of SemEval-2.	SemEval@ACL	2010	DBLP BibTeX RDF
23	David Jurgens, Keith Stevens	HERMIT: Flexible Clustering for the SemEval-2 WSI Task.	SemEval@ACL	2010	DBLP BibTeX RDF
23	Wu Jigang, Thambipillai Srikanthan	An improved reconfiguration algorithm for degradable VLSI/WSI arrays.	J. Syst. Archit.	2003	DBLP DOI BibTeX RDF
23	Wu Jigang, Thambipillai Srikanthan, Chandni R. Patel	A Low Power Algorithm for Reconfigurable VLSI/WSI Arrays.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
23	Bing Qiu 0003, Yvon Savaria, Meng Lu, Chunyan Wang 0004, Claude Thibeault	Yield Modeling of a WSI Telecom Router Architecture.	DFT	2002	DBLP DOI BibTeX RDF
23	Yoshichika Fujioka, Nobuhiro Tomabechi	Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units.	Syst. Comput. Jpn.	2000	DBLP DOI BibTeX RDF
23	Mohamed Nekili, Yvon Savaria, Guy Bois	Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
23	Jagannathan Narasimhan, Kazuo Nakajima, Chong S. Rim	A Graph Theoretical Approach for the Yield Enhancement of Reconfigurable VLSI/WSI Arrays.	Discret. Appl. Math.	1999	DBLP DOI BibTeX RDF
23	Earl E. Swartzlander Jr.	VLSI, MCM, and WSI: A Design Comparison.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
23	Stuart K. Tewksbury, Glenn H. Chapman	Guest Editorial Foreword to the Special Section on WSI'95.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
23	Chung-Han Chen	Embedding binary tree in VLSI/WSI processor array.	J. Comput. Sci. Technol.	1996	DBLP DOI BibTeX RDF
23	Nobuhiro Tomabechi	WSI oriented design for highly reliable systems based on the residue number system.	Syst. Comput. Jpn.	1996	DBLP DOI BibTeX RDF
23	Eiji Fujiwara, Masaharu Tanaka	Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation.	IEICE Trans. Inf. Syst.	1995	DBLP BibTeX RDF
23	Yung-Yuan Chen, Shambhu J. Upadhyaya	Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF
23	Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori	Hierarchical Reconfiguration of VLSI/WSI Arrays.	VLSI Design	1994	DBLP DOI BibTeX RDF
23	Claus M. Habiger, R. Mike Lea	Hybrid-WSI: A Massively Parallel Computing Technology?	Computer	1993	DBLP DOI BibTeX RDF
23	Jung H. Kim, Kemal Efe	A parallel reconfiguration algorithm for WSI/VLSI processor arrays.	Microprocess. Microsystems	1993	DBLP DOI BibTeX RDF
23	Siu-Cheung Chau	On Implementing Large Fault-Tolerant Binary Tree Architecture in WSI.	ICCI	1993	DBLP BibTeX RDF
23	Hideo Ito	A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube.	DFT	1993	DBLP BibTeX RDF
23	Chor Ping Low, Hon Wai Leong	On the Reconfiguration of Degradable VLSI/WSI Arrays.	DFT	1993	DBLP BibTeX RDF
23	Eiji Fujiwara, Masaharu Tanaka	A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation.	DFT	1993	DBLP BibTeX RDF
23	Hussam Y. Abujbara, Sami A. Al-Arian	Degrading fault model for WSI interconnection lines.	VTS	1993	DBLP DOI BibTeX RDF
23	Wojciech Maly	Prospects for WSI: A Manufacturing Perspective.	Computer	1992	DBLP DOI BibTeX RDF
23	Vijay K. Jain, Hiroomi Hikawa, David C. Keezer	An Architecture for WSI Rapid Prototyping.	Computer	1992	DBLP DOI BibTeX RDF
23	Robert W. Horst	Task-Flow Architecture for WSI Parallel Processing.	Computer	1992	DBLP DOI BibTeX RDF
23	Raja Venkateswaran, Pinaki Mazumder, K. G. Shin	Restructuring WSI hexagonal processor arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
23	Jung H. Kim, Phill K. Rhee, Dong S. Ha 0001	An optimal domain-based reconfiguration algorithm for WSI processor arrays.	Microprocess. Microprogramming	1992	DBLP DOI BibTeX RDF
23	Pinaki Mazumder	An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays.	ITC	1992	DBLP DOI BibTeX RDF
23	Wei-Kang Huang, Fabrizio Lombardi	Minimizing the cost of repairing WSI memories.	Integr.	1991	DBLP DOI BibTeX RDF
23	Y.-H. Choi	Reconfigurable VLSI/WSI multipipelines.	Parallel Comput.	1991	DBLP DOI BibTeX RDF
23	Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath	New algorithms for reconfiguring VLSI/WSI arrays.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
23	R. M. Lea	WASP: A WSI Associative String Processor.	J. VLSI Signal Process.	1991	DBLP DOI BibTeX RDF
23	Nobuhiro Tomabechi	A defect recovery method for ulsi/ wsi arithmetic operation systems based on residue number systems.	Syst. Comput. Jpn.	1991	DBLP DOI BibTeX RDF
23	Jung Hwan Kim, Phill-Kyu Rhee	A Parallel Reconfiguration Algorithm for WSI/VLSI Processor Arrays.	ICPP (1)	1991	DBLP BibTeX RDF
23	Edmond Félix Kouka, Jean-Luc Patry	Algorithms for restructuring WSI arrays of processors.	Comput. Syst. Sci. Eng.	1990	DBLP BibTeX RDF
23	Paul Anderson 0001, Paul H. J. Kelly, Phil Winterbottom	The feasibility of a general-purpose parallel computer using WSI.	Future Gener. Comput. Syst.	1990	DBLP DOI BibTeX RDF
23	Vwani P. Roychowdhury, Jehoshua Bruck	On Finding Non-Intersecting Paths in Grids and Its Application in Reconfiguring VLSI/WSI Arrays.	SODA	1990	DBLP DOI BibTeX RDF