The FacetedDBLP logo    Search for: in:

Disable automatic phrases ?     Syntactic query expansion: ?

Searching for Wiring with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1956-1973 (15) 1974-1978 (16) 1979-1981 (15) 1982-1985 (16) 1986-1987 (15) 1988-1989 (27) 1990 (17) 1991-1992 (24) 1993-1994 (27) 1995 (23) 1996 (20) 1997 (15) 1998 (57) 1999 (34) 2000 (41) 2001 (30) 2002 (41) 2003 (41) 2004 (43) 2005 (37) 2006 (63) 2007 (55) 2008 (40) 2009 (24) 2010 (16) 2011-2012 (20) 2013-2014 (30) 2015-2016 (25) 2017-2018 (24) 2019-2020 (23) 2021 (20) 2022 (20) 2023 (18) 2024 (6)
Publication types (Num. hits)
article(323) incollection(7) inproceedings(603) phdthesis(4) proceedings(1)
Venues (Conferences, Journals, ...)
GrowBag graphs for keyword ? (Num. hits/coverage)

Group by:
The graphs summarize 553 occurrences of 391 keywords

Results
Found 938 publication records. Showing 938 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
130Rosemary M. Francis, Simon W. Moore FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF tdm wiring, fpga, routing
102Katsunori Kitano, Tomoki Fukai Variability v.s. synchronicity of neuronal activity in local cortical network models with different wiring topologies. Search on Bibsonomy J. Comput. Neurosci. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Neuronal wiring, Irregular firing, Computational model, Small-world network, Synchrony
85J. T. Mowchenko, Y. Yang Optimizing wiring space in slicing floorplans. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wiring space optimisation, slicing floorplans, net density, sibling rectangles, circuit modules, routed layouts, VLSI, heuristic, network routing, circuit layout CAD, circuit optimisation, integrated circuit layout, branch and bound algorithm, wiring, IC layout
70Man-Fai Yu, Joel Darnauer, Wayne Wei-Ming Dai Interchangeable pin routing with application to package layout. Search on Bibsonomy ICCAD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF BGA, all-angle wiring, interchangeable pin routing, min-cost max-flow heuristic, multiple layers, octilinear wiring, package layout, pin redistribution, prerouted nets, rectilinear wiring, test fixture routing, triangulated routing network, CAD, NP-complete, ASIC, circuit layout CAD, speed, PGA, input output, routing problems
65Abdil Rashid Mohamed, Zebo Peng, Petru Eles A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF BIST insertion, wiring area, simulated annealing, test synthesis
63Rosemary M. Francis, Simon W. Moore, Robert D. Mullins A Network of Time-Division Multiplexed Wiring for FPGAs. Search on Bibsonomy NOCS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF time division multplexing, fpga, network-on-chip
63Steven L. Teig The X architecture: not your father's diagonal wiring. Search on Bibsonomy SLIP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
63Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. Search on Bibsonomy DATE The full citation details ... 1998 DBLP  DOI  BibTeX  RDF signature-invariance, circuit mutants, benchmarking, equivalence class
63Thomas Lengauer, Rolf Müller Robust and accurate hierarchical floorplanning with integrated global wiring. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
58Inder S. Gopal, Don Coppersmith, C. K. Wong Optimal Wiring of Movable Terminals. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF wiring channels, movable terminals, VLSI chip design, dynamic programming, optimal algorithms, Analysis of algorithms, NP-complete problems, wiring, vias
57Jae-dong Lee, Kenneth E. Batcher A bitonic sorting network with simpler flip interconnections. Search on Bibsonomy ISPAN The full citation details ... 1996 DBLP  DOI  BibTeX  RDF flip interconnections, bitonic sorting network, inter-level wiring, parity technique, Construct-BSMF, N/2 even-parity keys, interconnection scheme, perfect-shuffle interconnection, parallel algorithms, parallel architectures, multiprocessor interconnection networks, sorting
54Chin Ngai Sze, Yu-Liang Wu Improved alternative wiring scheme applying dominator relationship. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
54Ioannis G. Tollis A new approach to wiring layouts. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
48Beth L. Chen, Dmitri B. Chklovskii Placement and routing optimization in the brain. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF wiring length minimization, linear programming, neurons, synapses, C. elegans
47Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato Exploiting Wiring Resources on Interconnection Network: Increasing Path Diversity. Search on Bibsonomy PDP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF SDM, Spatial Division Multiplexing, parallel links, Networks on chip, NoCs, Wiring, Wires
47Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl Robust wiring networks for DfY considering timing constraints. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF redundant wiring, timing constraint aware, open defects, design for yield
47Abdil Rashid Mohamed, Zebo Peng, Petru Eles A Heuristic for Wiring-Aware Built-In Self-Test Synthesis. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF BIST insertion, wiring area, test synthesis
47Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2003 DBLP  DOI  BibTeX  RDF interconnect, multiple faults, adaptive diagnosis, Wiring network
47Yu-Liang Wu, Wangning Long, Hongbing Fan A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. Search on Bibsonomy VLSI Design The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Alternative wiring, Graph-based pattern matching, Logic synthesis
47Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi Two-Step Algorithms for Maximal Diagnosis of Wiring Interconnects. Search on Bibsonomy FTCS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF Interconnect, Multiple Faults, Adaptive Diagnosis, Wiring Network
47Jeffrey Z. Su, Wayne Wei-Ming Dai Post-route optimization for improved yield using a rubber-band wiring model. Search on Bibsonomy ICCAD The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Rubber-Band, Topological Wiring Even Wire Distribution, Yield, Design for Manufacturability, Spacing, Bridge Fault, Routability, Critical Area, Layout Optimization, Routing Congestion
46André DeHon Rent's rule based switching requirements. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF switching requirements, hierarchical networks, Rent's rule
46Fran Hancheck, Shantanu Dutt Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
46Soo-Young Oh, Khalid Rahmat, O. Sam Nakagawa, John Moll A Scaling Scheme and Optimization Methodology for Deep Sub-Micron Interconnect. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
45Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Müller 0003, Sven Peyer, Christian Schulte 0002 Yield Improvement by Local Wiring Redundancy. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Abdil Rashid Mohamed, Zebo Peng, Petru Eles A Wiring-Aware Approach to Minimizing Built-in Self-Test Overhead. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Paul Kartschoke, Stephen F. Geissler Timing Driven Wiring on an Advanced Microprocessor. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Wing K. Luk, Donald T. Tang, C. K. Wong Hierarchial global wiring for custom chip design. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
40Hungwen Li, Massimo Maresca Polymorphic-Torus Network. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1989 DBLP  DOI  BibTeX  RDF polymorphic-torus network, parallel fine-grained, circuit-switching capability, wiring complexity, interpackage wiring, max/min, sum operations, interconnection network, multiprocessor interconnection networks, SIMD, communication bandwidth, Boolean
39Jun-nosuke Teramae, Tomoki Fukai Local cortical circuit model inferred from power-law distributed neuronal avalanches. Search on Bibsonomy J. Comput. Neurosci. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Neuronal wiring, Cortical network development, Synchronization, Synfire chain, Cell assembly
38Martin L. Brady, Majid Sarrafzadeh Stretching a Knock-Knee Layout for Multilayer Wiring. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF knock-knee layout stretching, multilayer wiring, knock-knee mode, 4/3 approximation algorithm, VLSI, VLSI, NP-complete, optimal algorithm, circuit layout CAD
37Martijn T. Bennebroek Validation of wire length distribution models on commercial designs. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie Wire layer geometry optimization using stochastic wire sampling. Search on Bibsonomy SLIP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF genetic algorithms, optimization, interconnect, Rent's rule
37D. B. Polkl A Three-Layer Gridless Channel Router with Compaction. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
36Yunkyu Sohn, Jaeseung Jeong Inferring Behavioral-level Circuits of Caenorhabditis elegans from the Topology of its Wiring Diagram. Search on Bibsonomy BIBE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
36Fei He 0001, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu 0001, Jia-Guang Sun 0001 A Hierachical Method for Wiring and Congestion Prediction. Search on Bibsonomy ISVLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
36Dmitri B. Chklovskii Evolution as the blind engineer: wiring minimization in the brain. Search on Bibsonomy SLIP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
36Toru Hiyama, Yuko Ito, Satoru Isomura, Kazunobu Nojiri, Eijiro Maeda Advanced Wiring RC Timing Design Techniques for Logic LSIs in Gigahertz Era and Beyond. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
36Rony Kay, Lawrence T. Pileggi EWA: efficient wiring-sizing algorithm for signal nets and clock nets. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
36Wu-Tung Cheng, James L. Lewandowski, Eleanor Wu Optimal diagnostic methods for wiring interconnects. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
36Majid Sarrafzadeh, Dorothea Wagner, Frank Wagner 0001, Karsten Weihe Wiring Knock-Knee Layouts: A Global Appoach. Search on Bibsonomy ISAAC The full citation details ... 1992 DBLP  DOI  BibTeX  RDF
35Cher Ming Tan, Kim Peng Lim, Tai Chong Chai, Guat Cheng Lim Non-destructive identification of open circuit in wiring on organic substrate with high wiring density covered with solder resist. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
29Norio Kuji, Takako Ishihara EB-Testing-Pad Method and Its Evaluation by Actual Devices. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF E-beam tester, stacked vias, testing pads, multi level wiring, CMp, SIMOX/CMOS technology, observability
29Bin Liu, Fabrizio Lombardi, Wei-Kang Huang Testing programmable interconnect systems: an algorithmic approach. Search on Bibsonomy Asian Test Symposium The full citation details ... 2000 DBLP  DOI  BibTeX  RDF programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits
29Po-Ching Hsu, Sying-Jyan Wang Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. Search on Bibsonomy Asian Test Symposium The full citation details ... 1996 DBLP  DOI  BibTeX  RDF multiple-board system, bus emulator, wiring interconnect, testing, fault detection, diagnosis, microprocessor, printed circuit board, printed circuit testing, hierarchical testing
29Jacob Savir On shrinking wide compressors. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
28Jun Nishiyama, Hiroyuki Sugahara, Tetsuya Okada, Takashi Kunifuji, Yamato Fukuta, Masayuki Matsumoto A signal control system by optical LAN and design simplification. Search on Bibsonomy SMC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Zhuo Li 0001, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi Probabilistic Congestion Prediction with Partial Blockages. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
28Devang Jariwala, John Lillis Trunk decomposition based global routing optimization. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
28Hiroyuki Sugahara, Takashi Kunifuji, Tetsunori Hattori, Yoshiyuki Hirano, Yamato Fukuta, Masayuki Matsumoto Assurance Technologies for Signal Control System by Optical LAN. Search on Bibsonomy ICDCS Workshops The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Signal control system, E-PON, Field Controller, Optical LAN, Logical Controller
28André DeHon, Raphael Rubin Design of FPGA interconnect for multilevel metallization. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Davide Pandini, Cristiano Forzan, Livio Baldi Design Methodologies and Architecture Solutions for High-Performance Interconnects. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
28Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright Prediction of interconnect pattern density distribution: derivation, validation, and applications. Search on Bibsonomy SLIP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF interconnect network prediction, interconnect pattern density, Stochastic model, probability density function
28Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas Congestion-Aware Logic Synthesis. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
28Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
28Kenneth Rose A comprehensive look at system level model. Search on Bibsonomy SLIP The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
28David Staepelaere, Jeffrey Jue, Tal Dayan, Wayne Wei-Ming Dai SURF: Rubber-Band Routing System for Multichip Modules. Search on Bibsonomy IEEE Des. Test Comput. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
28Pierre Abouzeid, K. Sakouti, Gabriele Saucier, Franck Poirot Multilevel Synthesis Minimizing the Routing Factor. Search on Bibsonomy DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
28J. Fernando Naveda, K. C. Chang 0001, David Hung-Chang Du A new approach to multi-layer PCB routing with short vias. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
28Michael Burstein, Mary N. Youssef Timing influenced layout design. Search on Bibsonomy DAC The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
27Iris Hui-Ru Jiang, Hua-Yu Chang, Chih-Long Chang Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. Search on Bibsonomy ISPD The full citation details ... 2010 DBLP  DOI  BibTeX  RDF routing, linear programming, network flow, electromigration
27Claudius Gläser, Frank Joublin, Christian Goerick Enhancing Topology Preservation during Neural Field Development Via Wiring Length Minimization. Search on Bibsonomy ICANN (1) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
27Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. Search on Bibsonomy MICRO The full citation details ... 2007 DBLP  DOI  BibTeX  RDF non-uniform cache archi- tectures (NUCA), on-chip intercon- nects, memory hierarchies, cache models
27Dirk Niebuhr, Andreas Rausch A concept for dynamic wiring of components: correctness in dynamic adaptive systems. Search on Bibsonomy SAVCBS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF runtime testing, adaptation, component, reconfiguration, correctness, dynamic adaptive systems
27Marc Benkert, Martin Nöllenburg, Takeaki Uno, Alexander Wolff 0001 Minimizing Intra-edge Crossings in Wiring Diagrams and Public Transportation Maps. Search on Bibsonomy GD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
27Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen Wiring area optimization in floorplan-aware hierarchical power grids. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
27Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells. Search on Bibsonomy ISQED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
27Lawrence S. Baum, John H. Boose, Molly L. Boose, Carey Chaplin, Ron Provine Extracting System-Level Understanding from Wiring Diagram Manuals. Search on Bibsonomy GREC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
27Satoshi Tayu, Mineo Kaneko Characterization and computation of Steiner wiring based on Elmore's delay model. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita Chip size estimation based on wiring area. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
27Heidi M. E. Korhonen, Jussi Heikkilä 0002, Jon M. Törnwall A simulation case study of production planning and control in printed wiring board manufacturing. Search on Bibsonomy WSC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
27Jun Dong Cho Wiring space and length estimation in two-dimensional arrays. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
27Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai An Even Wiring Approach to the Ball Grid Array Package Routing. Search on Bibsonomy ICCD The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
27Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen NEWS: a net-even-wiring system for the routing on a multilayer PGA package. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
27Reiji Suda, Ryotaro Kamikawai, Yasuo Wada, Willy Hioe, Mutsumi Hosoya, Eiichi Goto QFP wiring problem-introduction and analytical considerations. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1994 DBLP  DOI  BibTeX  RDF
27Kuo-En Chang Efficient algorithms of wiring channels with movable terminals. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
27C. C. Martin, K. K. Hutchison Computer aided concurrent design for printed wiring boards. Search on Bibsonomy IEA/AIE (1) The full citation details ... 1989 DBLP  DOI  BibTeX  RDF Prolog
27Gotaro Odawara, T. Hamuro, Kazuhiko Iijima, T. Yoshino, Y. Dai A Rule-Based Placement System for Printed Wiring Boards. Search on Bibsonomy DAC The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
27Toshihiko Tada, Akihiko Hanafusa Router system for printed wiring boards of very high-speed, very large-scale computers. Search on Bibsonomy DAC The full citation details ... 1986 DBLP  DOI  BibTeX  RDF
27Gotaro Odawara, Kazuhiko Iijima, Kazutoshi Wakabayashi Knowledge-based placement technique for printed wiring boards. Search on Bibsonomy DAC The full citation details ... 1985 DBLP  DOI  BibTeX  RDF
20Aimee Rydarowski, Özge Samanci, Ali Mazalek Murmur: kinetic relief sculpture, multi-sensory display, listening machine. Search on Bibsonomy TEI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF CPU fan, mechatronic art, multi-sensory displays, information visualization, interactive art, ambient displays, wiring
20Jing Li, Tan Yan, Bo Yang 0011, Juebang Yu, Chunhui Li A packing algorithm for non-manhattan hexagon/triangle placement design by using an adaptive o-tree representation. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF O-tree representation, VLSI circuit physical design, Y- architecture, diagonal wiring, non-Manhattan layout, placement
20Jun Zhao 0005, Fred J. Meyer, Fabrizio Lombardi Adaptive Fault Detection and Diagnosis of RAM Interconnects. Search on Bibsonomy J. Electron. Test. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF interconnect, memory, diagnosis, detection, wiring
20Real G. Pomerleau, Paul D. Frazon, Griff L. Bilbro Improved Selay Prediction for On-Chip Buses. Search on Bibsonomy DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF RC wiring delay, buffer optimization, high-level synthesis, floorplanning, interconnect optimization
20Fran Hanchek, Shantanu Dutt Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1998 DBLP  DOI  BibTeX  RDF cell faults, wiring faults, Fault tolerance, Field Programmable Gate Array (FPGA), reconfiguration, yield improvement
20Man-Fai Yu, Wayne Wei-Ming Dai Single-layer fanout routing and routability analysis for Ball Grid Arrays. Search on Bibsonomy ICCAD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF package routing, ball grid array, pin grid array, planar routing, even wiring, fanout routing, routability
20Franco P. Preparata, Witold Lipski Jr. Optimal Three-Layer Channel Routing. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1984 DBLP  DOI  BibTeX  RDF multilayer wiring, VLSI design, optimal algorithms, VLSI layouts, Channel routing
18Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF structured asics, via programmable fabric
18Ling Zhang, Yulei Zhang 0002, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng High performance on-chip differential signaling using passive compensation for global communication. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
18Kaustav Banerjee Graphene based nanomaterials for VLSI interconnect and energy-storage applications. Search on Bibsonomy SLIP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF carbon nanomaterials, graphene nano-ribbons, interconnects, carbon nanotubes, passives
18Tilo Meister, Jens Lienig, Gisbert Thomke Novel Pin Assignment Algorithms for Components with Very High Pin Counts. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Shannon Koh, Oliver Diessel The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. Search on Bibsonomy FCCM The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Dmitri "Mitya" Chklovskii What can brain researchers learn from computer engineers and vice versa? Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Yulei Zhang 0002, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng On-chip high performance signaling using passive compensation. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
18Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl IntSim: A CAD tool for optimization of multilevel interconnect networks. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang ECO timing optimization using spare cells. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Min Zhao 0001, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
18Rod Adams, Lee Calcraft, Neil Davey Evolved Patterns of Connectivity in Associative Memory Models. Search on Bibsonomy IEEE ICCI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. Search on Bibsonomy MICRO The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
18Mario Chauca, Juan C. Seminario Castro, Walter Flores Matias, Eder Pacheco Aaron Control System Over Power Line. Search on Bibsonomy CONIELECOMP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF optocoupler, demodulation, power line, modulation
Displaying result #1 - #100 of 938 (100 per page; Change: )
Pages: [1][2][3][4][5][6][7][8][9][10][>>]
Valid XHTML 1.1! Valid CSS! [Valid RSS]
Maintained by L3S.
Previously maintained by Jörg Diederich.
Based upon DBLP by Michael Ley.
open data data released under the ODC-BY 1.0 license